Author: Armin Rigo <[email protected]>
Branch: arm64
Changeset: r96945:aaf0d2d39b30
Date: 2019-07-04 12:27 +0200
http://bitbucket.org/pypy/pypy/changeset/aaf0d2d39b30/
Log: probable fix (untested)
diff --git a/rpython/jit/backend/aarch64/regalloc.py
b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -1091,7 +1091,7 @@
if box.type == REF and self.rm.is_still_alive(box):
assert not noregs
assert loc.is_core_reg()
- val = loc.value
+ val = self.cpu.all_reg_indexes[loc.value]
gcmap[val // WORD // 8] |= r_uint(1) << (val % (WORD * 8))
for box, loc in self.fm.bindings.iteritems():
if box.type == REF and self.rm.is_still_alive(box):
@@ -1137,4 +1137,4 @@
if hasattr(Regalloc, methname):
func = getattr(Regalloc, methname).im_func
comp_operations[value] = func
-
\ No newline at end of file
+
_______________________________________________
pypy-commit mailing list
[email protected]
https://mail.python.org/mailman/listinfo/pypy-commit
