Author: Armin Rigo <[email protected]>
Branch:
Changeset: r97806:d81c769a2353
Date: 2019-10-18 08:29 +0200
http://bitbucket.org/pypy/pypy/changeset/d81c769a2353/
Log: Arguably, clarify the logic. The real motivation is a gcc bug, see
issue #3086
diff --git a/rpython/jit/backend/aarch64/opassembler.py
b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -808,9 +808,7 @@
# Inline a series of STR operations, starting at 'dstaddr_loc'.
#
self.mc.gen_load_int(r.ip0.value, 0)
- i = 0
- adjustment = 0
- needs_adjustment = itemsize < 8 and (startbyte % 8)
+ i = dst_i = 0
total_size = size_box.getint()
while i < total_size:
sz = itemsize
@@ -818,19 +816,19 @@
next_group += 8
if next_group <= total_size:
sz = 8
+ if dst_i % 8: # unaligned?
+ self.mc.ADD_ri(dstaddr_loc.value,
dstaddr_loc.value, dst_i)
+ dst_i = 0
if sz == 8:
- if needs_adjustment:
- self.mc.ADD_ri(dstaddr_loc.value, dstaddr_loc.value, i)
- adjustment = -i
- needs_adjustment = False
- self.mc.STR_ri(r.ip0.value, dstaddr_loc.value, i +
adjustment)
+ self.mc.STR_ri(r.ip0.value, dstaddr_loc.value, dst_i)
elif sz == 4:
- self.mc.STRW_ri(r.ip0.value, dstaddr_loc.value, i +
adjustment)
+ self.mc.STRW_ri(r.ip0.value, dstaddr_loc.value, dst_i)
elif sz == 2:
- self.mc.STRH_ri(r.ip0.value, dstaddr_loc.value, i +
adjustment)
+ self.mc.STRH_ri(r.ip0.value, dstaddr_loc.value, dst_i)
else:
- self.mc.STRB_ri(r.ip0.value, dstaddr_loc.value, i +
adjustment)
+ self.mc.STRB_ri(r.ip0.value, dstaddr_loc.value, dst_i)
i += sz
+ dst_i += sz
else:
if isinstance(size_box, ConstInt):
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