Author: Armin Rigo <ar...@tunes.org>
Branch: py3.6
Changeset: r97877:7487744729a8
Date: 2019-10-28 14:09 +0100
http://bitbucket.org/pypy/pypy/changeset/7487744729a8/
Log: hg merge default
diff --git a/pypy/tool/release/package.py b/pypy/tool/release/package.py
--- a/pypy/tool/release/package.py
+++ b/pypy/tool/release/package.py
@@ -329,6 +329,8 @@
options.no_tk = True
if os.environ.has_key("PYPY_EMBED_DEPENDENCIES"):
options.embed_dependencies = True
+ elif os.environ.has_key("PYPY_NO_EMBED_DEPENDENCIES"):
+ options.embed_dependencies = False
if not options.builddir:
# The import actually creates the udir directory
from rpython.tool.udir import udir
diff --git a/rpython/jit/backend/aarch64/opassembler.py
b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -986,7 +986,8 @@
loc_index = arglocs[1]
assert loc_index.is_core_reg()
tmp1 = r.ip1
- tmp2 = arglocs[-1] # the last item is a preallocated tmp
+ #tmp2 = arglocs[-1] -- the last item is a preallocated tmp on arm,
+ # but not here on aarch64
# lr = byteofs
s = 3 + descr.jit_wb_card_page_shift
mc.MVN_rr_shifted(r.lr.value, loc_index.value, s,
shifttype=shift.LSR)
@@ -997,10 +998,10 @@
descr.jit_wb_card_page_shift, shifttype=shift.LSR)
# set the bit
- mc.MOVZ_r_u16(tmp2.value, 1, 0)
+ mc.MOVZ_r_u16(r.ip0.value, 1, 0)
+ mc.LSL_rr(tmp1.value, r.ip0.value, tmp1.value)
mc.LDRB_rr(r.ip0.value, loc_base.value, r.lr.value)
- mc.LSL_rr(tmp2.value, tmp2.value, tmp1.value)
- mc.ORR_rr(r.ip0.value, r.ip0.value, tmp2.value)
+ mc.ORR_rr(r.ip0.value, r.ip0.value, tmp1.value)
mc.STR_size_rr(0, r.ip0.value, loc_base.value, r.lr.value)
# done
#
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