diff -r 38f60e97182c pypy/jit/backend/ppc/ppcgen/field.py
--- a/pypy/jit/backend/ppc/ppcgen/field.py	Fri Aug 12 13:29:52 2011 +0200
+++ b/pypy/jit/backend/ppc/ppcgen/field.py	Fri Aug 12 09:12:13 2011 -0400
@@ -17,7 +17,7 @@
 
 
 class Field(object):
-    def __init__(self, name, left, right, signedness=False, valclass=int):
+    def __init__(self, name, left, right, signedness=False, valclass=int, overlap=False):
         self.name = name
         self.left = left
         self.right = right
@@ -26,6 +26,7 @@
         self.mask = 2**width - 1
         self.signed = signedness == 'signed'
         self.valclass = valclass
+        self.overlap = overlap == 'overlap'
     def __repr__(self):
         return '<Field %r>'%(self.name,)
     def encode(self, value):
diff -r 38f60e97182c pypy/jit/backend/ppc/ppcgen/form.py
--- a/pypy/jit/backend/ppc/ppcgen/form.py	Fri Aug 12 13:29:52 2011 +0200
+++ b/pypy/jit/backend/ppc/ppcgen/form.py	Fri Aug 12 09:12:13 2011 -0400
@@ -165,13 +165,16 @@
     def __init__(self, *fnames):
         self.fields = []
         bits = {}
+        overlap = False
         for fname in fnames:
             if isinstance(fname, str):
                 field = self.fieldmap[fname]
             else:
                 field = fname
+            if field.overlap:
+                overlap = True
             for b in range(field.left, field.right+1):
-                if b in bits:
+                if not overlap and b in bits:
                     raise FormException, "'%s' and '%s' clash at bit '%s'"%(
                         bits[b], fname, b)
                 else:
diff -r 38f60e97182c pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py	Fri Aug 12 13:29:52 2011 +0200
+++ b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py	Fri Aug 12 09:12:13 2011 -0400
@@ -44,7 +44,7 @@
 
 MI = Form("rA", "rS", "SH", "MB", "ME", "Rc")
 MB = Form("rA", "rS", "rB", "MB", "ME", "Rc")
-MDI = Form("rA", "rS", "SH", "mbe", "XO5", "sh", "Rc")
+MDI = Form("rA", "rS", "sh", "mbe", "XO5", "Rc")
 MDS = Form("rA", "rS", "rB", "mbe", "XO5", "Rc")
 
 class BasicPPCAssembler(Assembler):
diff -r 38f60e97182c pypy/jit/backend/ppc/ppcgen/ppc_field.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_field.py	Fri Aug 12 13:29:52 2011 +0200
+++ b/pypy/jit/backend/ppc/ppcgen/ppc_field.py	Fri Aug 12 09:12:13 2011 -0400
@@ -37,7 +37,7 @@
     "rD":     ( 6, 10, 'unsigned', regname._R),
     "rS":     ( 6, 10, 'unsigned', regname._R),
     "SH":     (16, 20),
-    "sh":     (30, 30),
+    "sh":     (16, 30, 'unsigned', int, 'overlap'),
     "SIMM":   (16, 31, 'signed'),
     "SR":     (12, 15),
     "spr":    (11, 20),
@@ -91,13 +91,22 @@
         value = super(mbe, self).decode(inst)
         return (value & 1) << 5 | (value >> 1 & 31)
 
+class sh(Field):
+    def encode(self, value):
+        value = (value & 31) << 10 | (value & 32) >> 5
+        return super(spr, self).encode(value)
+    def decode(self, inst):
+        value = super(mbe, self).decode(inst)
+        return (value & 32) << 5 | (value >> 10 & 31)
+
 # other special fields?
 
 ppc_fields = {
     "LI":  IField("LI", *fields["LI"]),
     "BD":  IField("BD", *fields["BD"]),
     "ds":  IField("ds", *fields["ds"]),
-    "mbe": mbe("mbe", *fields["mbe"]),
+    "mbe": mbe("mbe",   *fields["mbe"]),
+    "sh":  sh("sh",     *fields["sh"]),
     "spr": spr("spr",   *fields["spr"]),
 }