On Tue, Mar 24, 2015 at 8:46 PM, Henry Gomersall <h...@cantab.net> wrote: > On 23/03/15 15:26, Derek Lockhart wrote: >> >> More generally, PyMTL supports multi-level simulation, so that >> functional-level, cycle-level, and register-transfer level logic can be >> described, composed, and simulated together. This, along with the way we >> construct our models (we use Python classes like Verilog modules), makes us >> a bit different than MyHDL. However, I think the mechanism we use to >> translate RTL logic into Verilog is quite similar: we have our own >> "translator" to manually walk the AST of behavioral logic, infer types, and >> generate Verilog source. >> > > PyMTL looks interesting, though I don't quite understand what you mean by > multi-level simulation. > > On the topic at hand, I wonder if there is scope for defining a common > intermediate representation (I mean, that both PyMTL and MyHDL can target). > Certainly, that would allow substantially more capability for novel schemes > for writing to V*, as well as sharing improvements in target generation. If > so, perhaps this discussion should be taken off list. > > My question in the context of PyPy is then, is building on the flow object > space sensible here? This is quite a natural fit for MyHDL, as the logic is > fully described (including all the signals) inside a single function. > > Cheers, > > Henry
I'm skeptical. Maybe you can abuse parts of it, but you'll soon realize that some things are not fitting in your model. Additionally, you would need to write verilog/vhdl backend which is a non-trivial amount of work _______________________________________________ pypy-dev mailing list pypy-dev@python.org https://mail.python.org/mailman/listinfo/pypy-dev
