Daniel Diniz <[email protected]> added the comment:
IIUC, this is what gcc 4.2.4 generates on a Celeron M for the code
Alexandre posted:
movl -272(%ebp), %eax
movl 8(%ebp), %edx
subl -228(%ebp), %eax
movl %eax, 60(%edx)
movl -272(%ebp), %ecx
movzbl (%ecx), %eax
-
addl $1, %ecx
movl %ecx, -272(%ebp)
movl opcode_targets.9311(,%eax,4), %ecx
movl %eax, %ebx
-
jmp *%ecx
And this is what ICC 11.0 generates for (what I think is) the same bit:
movl 360(%esp), %ecx
movl %esi, %edi
subl 304(%esp), %edi
movl %edi, 60(%ecx)
movzbl (%esi), %ecx
-
movl opcode_targets.2239.0.34(,%ecx,4), %eax
incl %esi
-
jmp ..B12.137 # Prob 100%
# ..B12.137: jmp *%eax
Does this mean that icc handles register starvation better here?
FWIW, on this CPU, compiling with icc gives a 20% speed boost in pybench
regardless of this patch.
----------
nosy: +ajaksu2
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