On Sat, Dec 7, 2019 at 9:58 AM Greg Ewing <greg.ew...@canterbury.ac.nz> wrote: > > On 7/12/19 2:54 am, Rhodri James wrote: > > > You've talked some about not making the 640k mistake > > I think it's a bit unfair to call it a "mistake". They had a 1MB > address space limit to work with, and that was a reasonable place > to put the division between RAM and display/IO space. If anything > is to be criticised, it's Intel's decision to only add 4 more > address bits when going from an 8-bit to a 16-bit architecture. >
And to construct a bizarre segmented system that means that 16 + 16 = 20, thus making it very hard to improve on it later. If it hadn't been for the overlapping segment idea, it would have been easy to go to 24 address lines later, and eventually 32. But since the 16:16 segmented system was built the way it was, every CPU afterwards had to remain compatible with it. Do you know when support for the A20 gate was finally dropped? 2013. Yes. THIS DECADE. If they'd decided to go for 32-bit addressing (even with 20 address lines), it would have been far easier to improve on it later. I'm sure there were good reasons for what they did (and hey, it did mean TSRs could be fairly granular in their memory requirements), but it's still a lesson to be learned from in not unnecessarily restrict something that follows Moore's Law. ChrisA _______________________________________________ Python-Dev mailing list -- python-dev@python.org To unsubscribe send an email to python-dev-le...@python.org https://mail.python.org/mailman3/lists/python-dev.python.org/ Message archived at https://mail.python.org/archives/list/python-dev@python.org/message/SW5HDQ27KBNYFMWAIMPVCGLVLNGQVNOK/ Code of Conduct: http://python.org/psf/codeofconduct/
