Thank you very much for your suggestions! I'll try in the next days to elaborate a bit on the last two ones.
By the way, the "once" assignment is not that evil if you use it for hardware modeling. Most hardware models look like: wire1 = function() instance component(input=wire1,output=wire2) result = function(wire2) When employing Python it's pretty straightforward to translate the instance to an object. instance = Component(input=wire1,output=wire2) Then you don't use "instance" *almost* anymore: it's an object which gets registered with the simulator kernel and gets called by reference and event-driven only by the simulator kernel. We might reuse the name for calling some administrative methods related to the instance (e.g. for reporting) but that's a pretty safe thing to do. Of course all this can be done during initialization, but there are some good reasons (see Verilog vs VHDL) why it's handy do be able to do it *anywhere*. The annoying problem was that every time the program flow goes over the assignment, the object gets recreated. Indeed Python itself is not a hardware modeling language, but I built some infrastructure to fill what I was missing and for quickly building up a functional prototype and testing some ideas Python is really excellent. Best Regards, Lorenzo -- http://mail.python.org/mailman/listinfo/python-list
