On Wed, 13 May 2026 at 11:55, Corvin Köhne <[email protected]> wrote: > > From: YannickV <[email protected]> > > A dummy DDR controller for ZYNQ has been added. While all registers are > present, > not all are functional. Read and write access is validated, and the user mode > can be set. This provides a basic DDR controller initialization, preventing > system hangs due to endless polling or similar issues. > > Signed-off-by: YannickV <[email protected]> > ---
Please address the code review comments from v5: https://patchew.org/QEMU/[email protected]/[email protected]/ thanks -- PMM
