On Wed, Sep 27, 2017 at 04:56:33PM -0300, Eduardo Habkost wrote: > Change all devices that set is_express=1 to implement > INTERFACE_PCIE_DEVICE. > > Cc: Keith Busch <[email protected]> > Cc: Kevin Wolf <[email protected]> > Cc: Max Reitz <[email protected]> > Cc: Dmitry Fleytman <[email protected]> > Cc: Jason Wang <[email protected]> > Cc: "Michael S. Tsirkin" <[email protected]> > Cc: Marcel Apfelbaum <[email protected]> > Cc: Paul Burton <[email protected]> > Cc: Paolo Bonzini <[email protected]> > Cc: Hannes Reinecke <[email protected]> > Cc: [email protected] > Reviewed-by: Alistair Francis <[email protected]> > Signed-off-by: Eduardo Habkost <[email protected]>
Reviewed-by: David Gibson <[email protected]> > --- > Changes v1 -> v2: > * base-xhci is marked as hybrid, now (in another patch) > * Included pcie-pci-bridge > --- > hw/block/nvme.c | 4 ++++ > hw/net/e1000e.c | 4 ++++ > hw/pci-bridge/pcie_pci_bridge.c | 1 + > hw/pci-bridge/pcie_root_port.c | 4 ++++ > hw/pci-bridge/xio3130_downstream.c | 4 ++++ > hw/pci-bridge/xio3130_upstream.c | 4 ++++ > hw/pci-host/xilinx-pcie.c | 4 ++++ > hw/scsi/megasas.c | 6 ++++++ > 8 files changed, 31 insertions(+) > > diff --git a/hw/block/nvme.c b/hw/block/nvme.c > index 9aa32692a3..441e21ed1f 100644 > --- a/hw/block/nvme.c > +++ b/hw/block/nvme.c > @@ -1110,6 +1110,10 @@ static const TypeInfo nvme_info = { > .instance_size = sizeof(NvmeCtrl), > .class_init = nvme_class_init, > .instance_init = nvme_instance_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { } > + }, > }; > > static void nvme_register_types(void) > diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c > index 6c42b4478c..81f7934a59 100644 > --- a/hw/net/e1000e.c > +++ b/hw/net/e1000e.c > @@ -708,6 +708,10 @@ static const TypeInfo e1000e_info = { > .instance_size = sizeof(E1000EState), > .class_init = e1000e_class_init, > .instance_init = e1000e_instance_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { } > + }, > }; > > static void e1000e_register_types(void) > diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c > index 9aa5cc3e45..88db143633 100644 > --- a/hw/pci-bridge/pcie_pci_bridge.c > +++ b/hw/pci-bridge/pcie_pci_bridge.c > @@ -180,6 +180,7 @@ static const TypeInfo pcie_pci_bridge_info = { > .class_init = pcie_pci_bridge_class_init, > .interfaces = (InterfaceInfo[]) { > { TYPE_HOTPLUG_HANDLER }, > + { INTERFACE_PCIE_DEVICE }, > { }, > } > }; > diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c > index 4d588cb22e..9b6e4ce512 100644 > --- a/hw/pci-bridge/pcie_root_port.c > +++ b/hw/pci-bridge/pcie_root_port.c > @@ -161,6 +161,10 @@ static const TypeInfo rp_info = { > .class_init = rp_class_init, > .abstract = true, > .class_size = sizeof(PCIERootPortClass), > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { } > + }, > }; > > static void rp_register_types(void) > diff --git a/hw/pci-bridge/xio3130_downstream.c > b/hw/pci-bridge/xio3130_downstream.c > index e706f36cb7..7d2f7629c1 100644 > --- a/hw/pci-bridge/xio3130_downstream.c > +++ b/hw/pci-bridge/xio3130_downstream.c > @@ -195,6 +195,10 @@ static const TypeInfo xio3130_downstream_info = { > .name = "xio3130-downstream", > .parent = TYPE_PCIE_SLOT, > .class_init = xio3130_downstream_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { } > + }, > }; > > static void xio3130_downstream_register_types(void) > diff --git a/hw/pci-bridge/xio3130_upstream.c > b/hw/pci-bridge/xio3130_upstream.c > index a052224bbf..227997ce46 100644 > --- a/hw/pci-bridge/xio3130_upstream.c > +++ b/hw/pci-bridge/xio3130_upstream.c > @@ -166,6 +166,10 @@ static const TypeInfo xio3130_upstream_info = { > .name = "x3130-upstream", > .parent = TYPE_PCIE_PORT, > .class_init = xio3130_upstream_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { } > + }, > }; > > static void xio3130_upstream_register_types(void) > diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c > index 4613dda1d2..7659253090 100644 > --- a/hw/pci-host/xilinx-pcie.c > +++ b/hw/pci-host/xilinx-pcie.c > @@ -317,6 +317,10 @@ static const TypeInfo xilinx_pcie_root_info = { > .parent = TYPE_PCI_BRIDGE, > .instance_size = sizeof(XilinxPCIERoot), > .class_init = xilinx_pcie_root_class_init, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { } > + }, > }; > > static void xilinx_pcie_register(void) > diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c > index 0db68aacee..535ee267c3 100644 > --- a/hw/scsi/megasas.c > +++ b/hw/scsi/megasas.c > @@ -2451,6 +2451,7 @@ typedef struct MegasasInfo { > int osts; > const VMStateDescription *vmsd; > Property *props; > + InterfaceInfo *interfaces; > } MegasasInfo; > > static struct MegasasInfo megasas_devices[] = { > @@ -2480,6 +2481,10 @@ static struct MegasasInfo megasas_devices[] = { > .is_express = true, > .vmsd = &vmstate_megasas_gen2, > .props = megasas_properties_gen2, > + .interfaces = (InterfaceInfo[]) { > + { INTERFACE_PCIE_DEVICE }, > + { } > + }, > } > }; > > @@ -2531,6 +2536,7 @@ static void megasas_register_types(void) > type_info.parent = TYPE_MEGASAS_BASE; > type_info.class_data = (void *)info; > type_info.class_init = megasas_class_init; > + type_info.interfaces = info->interfaces; > > type_register(&type_info); > } -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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