From: Naveen Nagar <naveen...@samsung.com>
Add support for the PMRMSCL and PMRMSCU MMIO registers. This allows
adding RDS/WDS support for PMR as well.
Signed-off-by: Naveen Nagar <naveen...@samsung.com>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
---
hw/block/nvme.h | 1 +
include/block/nvme.h | 1 +
hw/block/nvme.c | 89 ++++++++++++++++++++++++++++++++++++++++++--
3 files changed, 87 insertions(+), 4 deletions(-)
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index 2a25bc84f3f9..5988d9b36e12 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -152,6 +152,7 @@ typedef struct NvmeCtrl {
uint16_t temperature;
HostMemoryBackend *pmrdev;
+ bool pmr_cmse;
uint8_t aer_mask;
NvmeRequest **aer_reqs;
diff --git a/include/block/nvme.h b/include/block/nvme.h
index f3cbe17d0971..183dc5c0ecf6 100644
--- a/include/block/nvme.h
+++ b/include/block/nvme.h
@@ -62,6 +62,7 @@ enum NvmeCapMask {
#define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK)
#define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK)
#define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK)
+#define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK)
#define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK)
\
<< CAP_MQES_SHIFT)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 937a6ed0a70d..cbc2b32f7c87 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -273,6 +273,26 @@ static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr
addr)
return &n->cmbuf[addr - n->ctrl_mem.addr];
}
+static bool nvme_addr_is_pmr(NvmeCtrl *n, hwaddr addr)
+{
+ hwaddr hi, low;
+
+ if (!n->pmr_cmse) {
+ return false;
+ }
+
+ low = NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SHIFT;
+ hi = low + int128_get64(n->pmrdev->mr.size);
+
+ return addr >= low && addr < hi;
+}
+
+static inline void *nvme_addr_to_pmr(NvmeCtrl *n, hwaddr addr)
+{
+ hwaddr cba = NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SHIFT;
+ return memory_region_get_ram_ptr(&n->pmrdev->mr) + (addr - cba);
+}
+
static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
hwaddr hi = addr + size - 1;
@@ -285,6 +305,11 @@ static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void
*buf, int size)
return 0;
}
+ if (nvme_addr_is_pmr(n, addr) && nvme_addr_is_pmr(n, hi)) {
+ memcpy(buf, nvme_addr_to_pmr(n, addr), size);
+ return 0;
+ }
+
return pci_dma_read(&n->parent_obj, addr, buf, size);
}
@@ -406,9 +431,27 @@ static uint16_t nvme_map_addr_cmb(NvmeCtrl *n,
QEMUIOVector *iov, hwaddr addr,
return NVME_SUCCESS;
}
+static uint16_t nvme_map_addr_pmr(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr,
+ size_t len)
+{
+ if (!len) {
+ return NVME_SUCCESS;
+ }
+
+ if (!nvme_addr_is_pmr(n, addr) || !nvme_addr_is_pmr(n, addr + len - 1)) {
+ return NVME_DATA_TRAS_ERROR;
+ }
+
+ qemu_iovec_add(iov, nvme_addr_to_pmr(n, addr), len);
+
+ return NVME_SUCCESS;
+}
+
static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
hwaddr addr, size_t len)
{
+ bool cmb = false, pmr = false;
+
if (!len) {
return NVME_SUCCESS;
}
@@ -416,6 +459,12 @@ static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList
*qsg, QEMUIOVector *iov,
trace_pci_nvme_map_addr(addr, len);
if (nvme_addr_is_cmb(n, addr)) {
+ cmb = true;
+ } else if (nvme_addr_is_pmr(n, addr)) {
+ pmr = true;
+ }
+
+ if (cmb || pmr) {
if (qsg && qsg->sg) {
return NVME_INVALID_USE_OF_CMB | NVME_DNR;
}
@@ -426,7 +475,11 @@ static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList
*qsg, QEMUIOVector *iov,
qemu_iovec_init(iov, 1);
}
- return nvme_map_addr_cmb(n, iov, addr, len);
+ if (cmb) {
+ return nvme_map_addr_cmb(n, iov, addr, len);
+ } else {
+ return nvme_map_addr_pmr(n, iov, addr, len);
+ }
}
if (iov && iov->iov) {
@@ -459,7 +512,7 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1,
uint64_t prp2,
trace_pci_nvme_map_prp(trans_len, len, prp1, prp2, num_prps);
- if (nvme_addr_is_cmb(n, prp1)) {
+ if (nvme_addr_is_cmb(n, prp1) || (nvme_addr_is_pmr(n, prp1))) {
qemu_iovec_init(iov, num_prps);
} else {
pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
@@ -3818,6 +3871,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset,
uint64_t data,
} else {
memory_region_set_enabled(&n->pmrdev->mr, false);
NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 1);
+ n->pmr_cmse = false;
}
return;
case 0xE08: /* PMRSTS */
@@ -3832,8 +3886,32 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset,
uint64_t data,
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
"invalid write to PMRSWTP register, ignored");
return;
- case 0xE14: /* TODO PMRMSC */
- break;
+ case 0xE14: /* PMRMSCL */
+ if (!NVME_CAP_PMRS(n->bar.cap)) {
+ return;
+ }
+
+ n->bar.pmrmsc = (n->bar.pmrmsc & ~0xffffffff) | (data & 0xffffffff);
+ n->pmr_cmse = false;
+
+ if (NVME_PMRMSC_CMSE(n->bar.pmrmsc)) {
+ hwaddr cba = NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SHIFT;
+ if (cba + int128_get64(n->pmrdev->mr.size) < cba) {
+ NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 1);
+ return;
+ }
+
+ n->pmr_cmse = true;
+ }
+
+ return;
+ case 0xE18: /* PMRMSCU */
+ if (!NVME_CAP_PMRS(n->bar.cap)) {
+ return;
+ }
+
+ n->bar.pmrmsc = (n->bar.pmrmsc & 0xffffffff) | (data << 32);
+ return;
default:
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
"invalid MMIO write,"
@@ -4187,8 +4265,11 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice
*pci_dev)
static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
{
+ NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 1);
+ NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 1);
NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
+ NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 1);
pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
PCI_BASE_ADDRESS_SPACE_MEMORY |
--
2.30.0
