Branch: refs/heads/master Home: https://github.com/qemu/qemu Commit: dcf578ed8cec89543158b103940e854ebd21a8cf https://github.com/qemu/qemu/commit/dcf578ed8cec89543158b103940e854ebd21a8cf Author: Andrey Yurovsky <yurov...@gmail.com> Date: 2016-09-22 (Thu, 22 Sep 2016)
Changed paths: M target-arm/cpu.c Log Message: ----------- arm: add Cortex A7 CPU parameters Add the "cortex-a7" CPU with features and registers matching the Cortex-A7 MPCore Technical Reference Manual and the Cortex-A7 Floating-Point Unit Technical Reference Manual. The A7 is very similar to the A15. Signed-off-by: Andrey Yurovsky <yurov...@gmail.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473185229-4597-1-git-send-email-yurov...@gmail.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 00442402eaf818c8e0a9c7e79b68c957ea5f1f53 https://github.com/qemu/qemu/commit/00442402eaf818c8e0a9c7e79b68c957ea5f1f53 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/Makefile.objs A hw/arm/aspeed_soc.c R hw/arm/ast2400.c M hw/arm/palmetto-bmc.c A include/hw/arm/aspeed_soc.h R include/hw/arm/ast2400.h Log Message: ----------- ast2400: rename the Aspeed SoC files to aspeed_soc Let's prepare for new Aspeed SoCs and rename the ast2400 file to a more generic one. There are no changes in the code apart from the header file include. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-2-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: ff90606f9ae5efd78f2ae98f31207c735e8580a5 https://github.com/qemu/qemu/commit/ff90606f9ae5efd78f2ae98f31207c735e8580a5 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed_soc.c M hw/arm/palmetto-bmc.c M include/hw/arm/aspeed_soc.h Log Message: ----------- ast2400: replace ast2400 with aspeed_soc This is a name replacement to prepare ground for other SoCs. Let's also remove the AST2400_SMC_BASE definition from the address space mappings, as it is not used. This controller was removed from the Aspeed SoC AST2500, so this provides us a better common base for the address space mapping on both SoCs. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-3-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: b033271f11a17debc1cc3e56f6b9fa319ebe2c45 https://github.com/qemu/qemu/commit/b033271f11a17debc1cc3e56f6b9fa319ebe2c45 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed_soc.c M hw/arm/palmetto-bmc.c M include/hw/arm/aspeed_soc.h Log Message: ----------- aspeed-soc: provide a framework to add new SoCs Let's define an object class for each Aspeed SoC we support. A AspeedSoCInfo struct gathers the SoC specifications which can later be used by an instance of the class or by a board using the SoC. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Message-id: 1473438177-26079-4-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: aaf4e67f0efce49ca5cf2648706bf0b834d2535f https://github.com/qemu/qemu/commit/aaf4e67f0efce49ca5cf2648706bf0b834d2535f Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/Makefile.objs A hw/arm/aspeed.c R hw/arm/palmetto-bmc.c Log Message: ----------- palmetto-bmc: rename the Aspeed board file to aspeed.c We plan to add more Aspeed boards to this file. There are no changes in the code. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-5-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 74fb1f38071f557154558141ed8d3a57914b0996 https://github.com/qemu/qemu/commit/74fb1f38071f557154558141ed8d3a57914b0996 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed.c Log Message: ----------- palmetto-bmc: replace palmetto_bmc with aspeed This is mostly a name replacement to prepare ground for other SoCs specificities. It also adds a TypeInfo struct for the palmetto-bmc board with a custom initialization for the same reason. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-6-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: c3ba99f723af21f27d0f6c839443b218c75b0dc0 https://github.com/qemu/qemu/commit/c3ba99f723af21f27d0f6c839443b218c75b0dc0 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed.c Log Message: ----------- palmetto-bmc: add board specific configuration aspeed_board_init() now uses a board identifier to customize some values specific to the board. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-7-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 8da33ef757d6d49b41432a22e4ab357652ec0e14 https://github.com/qemu/qemu/commit/8da33ef757d6d49b41432a22e4ab357652ec0e14 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed.c M include/hw/misc/aspeed_scu.h Log Message: ----------- hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC This gives some explanation behind the magic number 0x120CE416. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-8-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 365aff1eaa370dc3bab2fb42b707496c46acb621 https://github.com/qemu/qemu/commit/365aff1eaa370dc3bab2fb42b707496c46acb621 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed_soc.c M hw/misc/aspeed_scu.c M hw/misc/aspeed_sdmc.c M include/hw/misc/aspeed_scu.h Log Message: ----------- aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers Based on previous work done by Andrew Jeffery <and...@aj.id.au>. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-9-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 9a7c17501187061e60102164bd84509a4d854d1d https://github.com/qemu/qemu/commit/9a7c17501187061e60102164bd84509a4d854d1d Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed.c Log Message: ----------- arm: add support for an ast2500 evaluation board The ast2500 eval board has a hardware strapping register value of 0xF100C2E6 which we use for a definition of AST2500_EVB_HW_STRAP1 below. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-10-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 67077e301454069fd849de755e9d04da70474304 https://github.com/qemu/qemu/commit/67077e301454069fd849de755e9d04da70474304 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed.c Log Message: ----------- palmetto-bmc: remove extra no_sdcard assignement Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1473438177-26079-11-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 3755f9e3164360ca34dcc77d842ce1d41321db4e https://github.com/qemu/qemu/commit/3755f9e3164360ca34dcc77d842ce1d41321db4e Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/misc/aspeed_sdmc.c M include/hw/misc/aspeed_sdmc.h Log Message: ----------- aspeed: calculate the RAM size bits at realize time There is no need to do this at each reset as the RAM size will not change. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Message-id: 1473438177-26079-12-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: b2fd45458d294e0a8a7c559881788d8642958bb7 https://github.com/qemu/qemu/commit/b2fd45458d294e0a8a7c559881788d8642958bb7 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/misc/aspeed_sdmc.c Log Message: ----------- aspeed: use error_report instead of LOG_GUEST_ERROR Also change the default value used in case of an error. The minimum size is a bit severe, so let's just use an average RAM size. Signed-off-by: Cédric Le Goater <c...@kaod.org> Message-id: 1473438177-26079-13-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: c6c7cfb01a00be0553f6694bbe71d45fc5e068c8 https://github.com/qemu/qemu/commit/c6c7cfb01a00be0553f6694bbe71d45fc5e068c8 Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed.c M hw/arm/aspeed_soc.c M hw/misc/aspeed_sdmc.c M include/hw/misc/aspeed_sdmc.h Log Message: ----------- aspeed: add a ram_size property to the memory controller Configure the size of the RAM of the SOC using a property to propagate the value down to the memory controller from the board level. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Message-id: 1473438177-26079-14-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: de46f5f46c1bb169045432a8208a9e10a662b55d https://github.com/qemu/qemu/commit/de46f5f46c1bb169045432a8208a9e10a662b55d Author: Cédric Le Goater <c...@kaod.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/aspeed.c Log Message: ----------- aspeed: allocate RAM after the memory controller has checked the size If the RAM size is invalid, the memory controller will use a default value. Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Andrew Jeffery <and...@aj.id.au> Message-id: 1473438177-26079-15-git-send-email-...@kaod.org Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 780d23e54e4a62c1bc37641b72e0188b6d13e861 https://github.com/qemu/qemu/commit/780d23e54e4a62c1bc37641b72e0188b6d13e861 Author: Dmitry Osipenko <dig...@gmail.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/core/ptimer.c Log Message: ----------- hw/ptimer: Actually stop the timer in case of error Running with counter / period = 0 is treated as a error case, printing error message claiming that timer has been disabled. However, timer is only marked as disabled, keeping to tick till expired and triggering after being claimed as disabled. Stop the QEMU timer to avoid confusion. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Message-id: 1e9bae4fae3c36430d7c28b0f486a0c71aff7eb3.1473252818.git.dig...@gmail.com Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: e7ea81c37d6f8b4202f63abbac35267bba1c8260 https://github.com/qemu/qemu/commit/e7ea81c37d6f8b4202f63abbac35267bba1c8260 Author: Dmitry Osipenko <dig...@gmail.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/musicpal.c M hw/core/ptimer.c M hw/dma/xilinx_axidma.c M hw/m68k/mcf5206.c M hw/m68k/mcf5208.c M hw/net/fsl_etsec/etsec.c M hw/net/lan9118.c M hw/timer/allwinner-a10-pit.c M hw/timer/arm_timer.c M hw/timer/digic-timer.c M hw/timer/etraxfs_timer.c M hw/timer/exynos4210_mct.c M hw/timer/exynos4210_pwm.c M hw/timer/exynos4210_rtc.c M hw/timer/grlib_gptimer.c M hw/timer/imx_epit.c M hw/timer/imx_gpt.c M hw/timer/lm32_timer.c M hw/timer/milkymist-sysctl.c M hw/timer/puv3_ost.c M hw/timer/sh_timer.c M hw/timer/slavio_timer.c M hw/timer/xilinx_timer.c M include/hw/ptimer.h Log Message: ----------- hw/ptimer: Introduce timer policy feature Some of the timer devices may behave differently from what ptimer provides. Introduce ptimer policy feature that allows ptimer users to change default and wrong timer behaviour, for example to continuously trigger periodic timer when load value is equal to "0". Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Message-id: 994cd608ec392da6e58f0643800dda595edb9d97.1473252818.git.dig...@gmail.com Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 2a8b58703e2144c136f6d26f609c6a338a03a3ca https://github.com/qemu/qemu/commit/2a8b58703e2144c136f6d26f609c6a338a03a3ca Author: Dmitry Osipenko <dig...@gmail.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/core/ptimer.c Log Message: ----------- hw/ptimer: Suppress error messages under qtest Under qtest ptimer emits lots of warning messages. The messages are caused by the actual checking of the ptimer error conditions. Suppress those messages, so they do not distract. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Message-id: 44877fff4ff03205590698d3dc189ad6d091472f.1473252818.git.dig...@gmail.com Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 5b262bb697189f4c979353933e883b6ae0dd0233 https://github.com/qemu/qemu/commit/5b262bb697189f4c979353933e883b6ae0dd0233 Author: Dmitry Osipenko <dig...@gmail.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M stubs/vmstate.c M tests/Makefile.include A tests/ptimer-test-stubs.c A tests/ptimer-test.c A tests/ptimer-test.h Log Message: ----------- tests: Add ptimer tests Ptimer is a generic countdown timer helper that is used by many timer device models as well as by the QEMU core. Add QTests for the ptimer. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Message-id: 1de89fe6e1ccaf6c8071ee3469e1a844df948359.1473252818.git.dig...@gmail.com Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: bcb39a65f141ca0d5bc703435dc6c54d402112f1 https://github.com/qemu/qemu/commit/bcb39a65f141ca0d5bc703435dc6c54d402112f1 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/net/cadence_gem.c Log Message: ----------- cadence_gem: QOMify Cadence GEM The sysbus_init_irq() call will eventually depend on a property so it needs to be in the realize function. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 486595809cf416d18a750aafbcfa1c81d7160c59.1469727764.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 2bf57f73e3a324ecdfac338e050eca381aa2216c https://github.com/qemu/qemu/commit/2bf57f73e3a324ecdfac338e050eca381aa2216c Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/net/cadence_gem.c M include/hw/net/cadence_gem.h Log Message: ----------- cadence_gem: Add the num-priority-queues property The Cadence GEM hardware supports N number priority queues, this patch is a step towards that by adding the property to set the queues. At the moment behaviour doesn't change as we only use queue 0. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 6543ec0d0c4bfd2678d0ed683efb197e91b17733.1469727764.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: e8e4994313b7f9fa41c9867c2b507cf24ef78789 https://github.com/qemu/qemu/commit/e8e4994313b7f9fa41c9867c2b507cf24ef78789 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/net/cadence_gem.c M include/hw/net/cadence_gem.h Log Message: ----------- cadence_gem: Add support for screening The Cadence GEM hardware allows incoming data to be 'screened' based on some register values. Add support for these screens. We also need to increase the max regs to avoid compilation failures. These new registers are implemented in the next patch. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 73e69a8ad9fa2763e9f68f71eaf2469dd5744fcc.1469727764.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 6710172501bedaf5181b6cac5a3d81e6deb2e136 https://github.com/qemu/qemu/commit/6710172501bedaf5181b6cac5a3d81e6deb2e136 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/net/cadence_gem.c Log Message: ----------- cadence_gem: Add queue support Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 28921252217b1d14f16889bafa88675f5b7a66cb.1469727764.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 77524d1157cf7c18b980c9d6f95879f2ce7e56e2 https://github.com/qemu/qemu/commit/77524d1157cf7c18b980c9d6f95879f2ce7e56e2 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/net/cadence_gem.c Log Message: ----------- cadence_gem: Correct indentation Fix up the indentation inside the for loop that was introduced in the previous patch. This commit is almost empty if viewed using 'git show -w', except for a few changes that were required to avoid the 80 charecter line limit. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: b40d1b12d24be9f0ac5d72f86249103e0c1c720a.1469727764.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 1372fc0b87b80634313ad332279f9c7ca0583862 https://github.com/qemu/qemu/commit/1372fc0b87b80634313ad332279f9c7ca0583862 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/arm/xlnx-zynqmp.c Log Message: ----------- xlnx-zynqmp: Set the number of priority queues Set the ZynqMP number of priority queues to 2. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: e047c338ee981a61afd7f765a317b3de25a4f629.1469727764.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 8cf6e9daca19e08216cf09e523d1dcdf3cfdaec7 https://github.com/qemu/qemu/commit/8cf6e9daca19e08216cf09e523d1dcdf3cfdaec7 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M include/hw/elf_ops.h M include/hw/loader.h Log Message: ----------- loader: Allow ELF loader to auto-detect the ELF arch If the caller didn't specify an architecture for the ELF machine the load_elf() function will auto detect it based on the ELF file. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: f2d70b47fcad31445f947f8817a0e146d80a046b.1474331683.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: d6ac342a48d50bdceaa43abe2e57854230101d90 https://github.com/qemu/qemu/commit/d6ac342a48d50bdceaa43abe2e57854230101d90 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/core/loader.c Log Message: ----------- loader: Use the specified MemoryRegion Prevously the specified MemoryRegion was ignored during the rom register reset. This patch uses the rom MemoryRegion is avaliable. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: d63fef5524deeb88e0068ca9d3fd4c8344f54dd4.1474331683.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 3e76099aacb4dae0d37ebf95305369e03d1491e6 https://github.com/qemu/qemu/commit/3e76099aacb4dae0d37ebf95305369e03d1491e6 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/core/loader.c M include/hw/elf_ops.h M include/hw/loader.h Log Message: ----------- loader: Allow a custom AddressSpace when loading ROMs When loading ROMs allow the caller to specify an AddressSpace to use for the load. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Message-id: 85f86b94ea94879e7ce8b12e85ac8de26658f7eb.1474331683.git.alistair.fran...@xilinx.com Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 70bb1d16f4e8576eb9370ae6be244312cd96df78 https://github.com/qemu/qemu/commit/70bb1d16f4e8576eb9370ae6be244312cd96df78 Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/core/loader.c M include/hw/elf_ops.h M include/hw/loader.h Log Message: ----------- loader: Add AddressSpace loading support to ELFs Add a new function load_elf_as() that allows the caller to specify an AddressSpace to use when loading the ELF. The original load_elf() function doesn't have any change in functionality. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 8b5cefecdf56fba4ccdff2db880f0b6b264cf16f.1474331683.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 5e774eb3bd264c76484906f4bd0fb38e00b8090e https://github.com/qemu/qemu/commit/5e774eb3bd264c76484906f4bd0fb38e00b8090e Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/core/loader.c M include/hw/loader.h Log Message: ----------- loader: Add AddressSpace loading support to uImages Add a new function load_uimage_as() that allows the caller to specify an AddressSpace to use when loading the uImage. The original load_uimage() function doesn't have any change in functionality. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 1254092e6b80d3cd3cfabafe165d56a96c54c0b5.1474331683.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 93ffc7c766429350d788ae0a978ea54171d652bd https://github.com/qemu/qemu/commit/93ffc7c766429350d788ae0a978ea54171d652bd Author: Alistair Francis <alistair.fran...@xilinx.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/core/loader.c M include/hw/loader.h Log Message: ----------- loader: Add AddressSpace loading support to targphys Add a new function load_image_targphys_as() that allows the caller to specify an AddressSpace to use when loading a targphys. The original load_image_targphys() function doesn't have any change in functionality. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Message-id: 87de45de7acf02cbe6bae9d6c4d6fb8f3aba4f61.1474331683.git.alistair.fran...@xilinx.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: a43639b12daff2230a98faffcffc79346c8ebf8c https://github.com/qemu/qemu/commit/a43639b12daff2230a98faffcffc79346c8ebf8c Author: Nathan Rossi <nat...@nathanrossi.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M include/hw/dma/xlnx-zynq-devcfg.h Log Message: ----------- dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX Whilst according to the Zynq TRM this device covers a register region of 0x000 - 0x120. The register region is also shared with XADCIF prefix registers at 0x100 and above. Due to how the devcfg and the xadc devices are implemented in QEMU these are separate models with individual mmio regions. As such the region registered by the devcfg overlaps with the xadc when initialized in a machine model (e.g. xilinx-zynq-a9). This patch fixes up the incorrect region size, where XLNX_ZYNQ_DEVCFG_R_MAX is missing its '/ 4' causing it to be 0x460 in size. As well as setting the region size to the 0x0 - 0x100 region so that an xadc device instance can be registered in the correct region to pair with the devcfg device instance. Mapping with XLNX_ZYNQ_DEVCFG_R_MAX = 0x118: dev: xlnx.ps7-dev-cfg, id "" mmio 00000000f8007000/0000000000000460 dev: xlnx,zynq-xadc, id "" mmio 00000000f8007100/0000000000000020 Mapping with XLNX_ZYNQ_DEVCFG_R_MAX = 0x100 / 4: dev: xlnx.ps7-dev-cfg, id "" mmio 00000000f8007000/0000000000000100 dev: xlnx,zynq-xadc, id "" mmio 00000000f8007100/0000000000000020 Signed-off-by: Nathan Rossi <nat...@nathanrossi.com> Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com> Message-id: 20160921180911.32289-1-nat...@nathanrossi.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: e7f76c521f4fd3c5bdbbb2cf97393523c05f6952 https://github.com/qemu/qemu/commit/e7f76c521f4fd3c5bdbbb2cf97393523c05f6952 Author: Dr. David Alan Gilbert <dgilb...@redhat.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/display/ssd0323.c Log Message: ----------- vmstateify ssd0323 display Bumps version number because we now use the VMSTATE_SSI_SLAVE that only uses a byte rather than a 32bit (for saving a bool 'cs'). Signed-off-by: Dr. David Alan Gilbert <dgilb...@redhat.com> Message-id: 1472035246-12483-2-git-send-email-dgilb...@redhat.com Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 2ccfd336dcdbc6f4f479380ed80003fac17a946e https://github.com/qemu/qemu/commit/2ccfd336dcdbc6f4f479380ed80003fac17a946e Author: Dr. David Alan Gilbert <dgilb...@redhat.com> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/sd/ssi-sd.c Log Message: ----------- vmstateify ssi-sd Changed a few types to fixed sized types in the ssi_sd_state Now saving/loading a byte for the cmdarg/response bytes that were previously saved as uint32 Bumped version number to deal with those changes. Signed-off-by: Dr. David Alan Gilbert <dgilb...@redhat.com> Message-id: 1472035246-12483-4-git-send-email-dgilb...@redhat.com Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: d486ccaa9ecdc37015ca0ecb330e3127ea948f8a https://github.com/qemu/qemu/commit/d486ccaa9ecdc37015ca0ecb330e3127ea948f8a Author: Peter Maydell <peter.mayd...@linaro.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M disas/arm.c Log Message: ----------- disas/arm.c: Remove unused macro definitions The macros ISSPACE, strneq, NUM_ELEMS and NUM_ARM_REGNAMES are defined in disas/arm.c but never used. Remove the unnecessary definitions. Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: d675765a0244af1d65c292f2508009f1bd13e1b6 https://github.com/qemu/qemu/commit/d675765a0244af1d65c292f2508009f1bd13e1b6 Author: Peter Maydell <peter.mayd...@linaro.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M hw/misc/imx25_ccm.c M hw/misc/imx31_ccm.c M hw/misc/imx6_ccm.c M hw/misc/imx6_src.c M hw/ssi/imx_spi.c M hw/timer/imx_epit.c M hw/timer/imx_gpt.c Log Message: ----------- imx: Use 'const char', not 'char const' 'char const' means the same thing as 'const char', but we use the former in only a handful of places and we use the latter over six thousand times. Switch the imx reg_name() functions to bring them in line with everything else. Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: e678c56f169bb576b607cda2a39c0b626ebfb221 https://github.com/qemu/qemu/commit/e678c56f169bb576b607cda2a39c0b626ebfb221 Author: Peter Maydell <peter.mayd...@linaro.org> Date: 2016-09-22 (Thu, 22 Sep 2016) Changed paths: M disas/arm.c M hw/arm/Makefile.objs A hw/arm/aspeed.c A hw/arm/aspeed_soc.c R hw/arm/ast2400.c M hw/arm/musicpal.c R hw/arm/palmetto-bmc.c M hw/arm/xlnx-zynqmp.c M hw/core/loader.c M hw/core/ptimer.c M hw/display/ssd0323.c M hw/dma/xilinx_axidma.c M hw/m68k/mcf5206.c M hw/m68k/mcf5208.c M hw/misc/aspeed_scu.c M hw/misc/aspeed_sdmc.c M hw/misc/imx25_ccm.c M hw/misc/imx31_ccm.c M hw/misc/imx6_ccm.c M hw/misc/imx6_src.c M hw/net/cadence_gem.c M hw/net/fsl_etsec/etsec.c M hw/net/lan9118.c M hw/sd/ssi-sd.c M hw/ssi/imx_spi.c M hw/timer/allwinner-a10-pit.c M hw/timer/arm_timer.c M hw/timer/digic-timer.c M hw/timer/etraxfs_timer.c M hw/timer/exynos4210_mct.c M hw/timer/exynos4210_pwm.c M hw/timer/exynos4210_rtc.c M hw/timer/grlib_gptimer.c M hw/timer/imx_epit.c M hw/timer/imx_gpt.c M hw/timer/lm32_timer.c M hw/timer/milkymist-sysctl.c M hw/timer/puv3_ost.c M hw/timer/sh_timer.c M hw/timer/slavio_timer.c M hw/timer/xilinx_timer.c A include/hw/arm/aspeed_soc.h R include/hw/arm/ast2400.h M include/hw/dma/xlnx-zynq-devcfg.h M include/hw/elf_ops.h M include/hw/loader.h M include/hw/misc/aspeed_scu.h M include/hw/misc/aspeed_sdmc.h M include/hw/net/cadence_gem.h M include/hw/ptimer.h M stubs/vmstate.c M target-arm/cpu.c M tests/Makefile.include A tests/ptimer-test-stubs.c A tests/ptimer-test.c A tests/ptimer-test.h Log Message: ----------- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160922' into staging target-arm queue: * add Cortex-A7 CPU * new ast2500 SoC model and evaluation board * palmetto-bmc: remove stray double assignment * aspeed: clean up RAM size handling * ptimer: framework for defining policy bits to change behaviour choices for different timer devices * ptimer: add some test cases * cadence_gem: add queue support * loader: support loading images to specified address spaces * loader: support auto-detect of ELF architecture from file * dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX * vmstateify ssd0323 * vmstateify ssi-sd * disas/arm.c: remove unused macros * imx: use 'const char', not 'char const' # gpg: Signature made Thu 22 Sep 2016 18:20:22 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>" # gpg: aka "Peter Maydell <pmayd...@gmail.com>" # gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160922: (36 commits) imx: Use 'const char', not 'char const' disas/arm.c: Remove unused macro definitions vmstateify ssi-sd vmstateify ssd0323 display dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX loader: Add AddressSpace loading support to targphys loader: Add AddressSpace loading support to uImages loader: Add AddressSpace loading support to ELFs loader: Allow a custom AddressSpace when loading ROMs loader: Use the specified MemoryRegion loader: Allow ELF loader to auto-detect the ELF arch xlnx-zynqmp: Set the number of priority queues cadence_gem: Correct indentation cadence_gem: Add queue support cadence_gem: Add support for screening cadence_gem: Add the num-priority-queues property cadence_gem: QOMify Cadence GEM tests: Add ptimer tests hw/ptimer: Suppress error messages under qtest hw/ptimer: Introduce timer policy feature ... Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Compare: https://github.com/qemu/qemu/compare/430da7a81d35...e678c56f169b