Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: fb70029b5099e955e3356a16bcb1c63ea99d7528
https://github.com/qemu/qemu/commit/fb70029b5099e955e3356a16bcb1c63ea99d7528
Author: Guenter Roeck <li...@roeck-us.net>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/gpio/imx_gpio.c
Log Message:
-----------
i.MX: Fix GPIO ISR register write
Writing the ISR register is supposed to clear interrupt status bits,
not to set them.
This patch makes '-M sabrelite' work without devicetree changes (Linux
kernel versions 3.18 to 4.7 with imx_v6_v7_defconfig and up to v4.8 with
multi_v7_defconfig; mainline has different problems).
Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Message-id: 1477361005-18646-1-git-send-email-li...@roeck-us.net
Acked-by: Jean-Christophe Dubois <j...@tribudubois.net>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 2aae15c679c1f81aeff3bd489c62778a560b7cf5
https://github.com/qemu/qemu/commit/2aae15c679c1f81aeff3bd489c62778a560b7cf5
Author: Guenter Roeck <li...@roeck-us.net>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/arm/cubieboard.c
Log Message:
-----------
arm: cubieboard: Add support for initrd
Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Message-id: 1477361131-18752-1-git-send-email-li...@roeck-us.net
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e9aff9864a52dda50bf78973aa1f648b0c166613
https://github.com/qemu/qemu/commit/e9aff9864a52dda50bf78973aa1f648b0c166613
Author: Guenter Roeck <li...@roeck-us.net>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/arm/pxa2xx.c
Log Message:
-----------
hw/arm/pxa2xx: Set value default values for CCCR and CKEN on PXA255
The code used default values for PXA270 to configure CCCR. For PXA255,
the resulting register value is invalid (unsupported) and resulted
in a division by zero in the Linux kernel. Use default values from
datasheet instead.
Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Message-id: 1477361273-18888-1-git-send-email-li...@roeck-us.net
[PMM: fixed tabs-vs-spaces nit]
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 5c8c2aafcf02986a998cf71aa47692fff176ad69
https://github.com/qemu/qemu/commit/5c8c2aafcf02986a998cf71aa47692fff176ad69
Author: Jean-Christophe Dubois <j...@tribudubois.net>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/arm/versatilepb.c
Log Message:
-----------
versatilepb: do not run if user asks for more than 256MB RAM
The versatilepb physical address space layout only has
a 256MB region for RAM before the devices. Without a guard
on the amount of RAM requested by the user we would happily
create a RAM area that overlapped with the devices, resulting
in very confusing behaviour (typically a guest crash).
Report the problem to the user if they try to request more
RAM than the board can handle (as we do already for some
other board models).
Signed-off-by: Jean-Christophe Dubois <j...@tribudubois.net>
Message-id: 20161025093711.17407-1-...@tribudubois.net
[PMM: tidied up commit message, comments. Use error_report()
rather than fprintf(stderr, ...).]
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d1df5cf3634af7003951d23164f349e360ecb601
https://github.com/qemu/qemu/commit/d1df5cf3634af7003951d23164f349e360ecb601
Author: Prasad J Pandit <p...@fedoraproject.org>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char: cadence: correct reset value for baud rate registers
The Cadence UART device emulator stores 'baud rate generator'
and 'baud rate divider' values, used in computing speed, in two
registers. The device specification defines their range and
their reset value. Use their correct value when resetting the
device in cadence_uart_reset.
Signed-off-by: Prasad J Pandit <p...@fedoraproject.org>
Message-id: 1477378140-2670-1-git-send-email-ppan...@redhat.com
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 929e754d5a621cd53f30e69b766ccf381b58d124
https://github.com/qemu/qemu/commit/929e754d5a621cd53f30e69b766ccf381b58d124
Author: Wei Huang <w...@redhat.com>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/cpu64.c
M target-arm/kvm64.c
Log Message:
-----------
arm: Add an option to turn on/off vPMU support
This patch adds a pmu=[on/off] option to enable/disable vPMU support
in guest vCPU. It allows virt tools, such as libvirt, to determine the
exsitence of vPMU and configure it. Note this option is only available
for cortex-a57/cortex-53/ host CPUs, but unavailable on ARMv7 and other
processors. Also even though "pmu=" option is available for TCG mode,
setting it doesn't turn PMU on.
Signed-off-by: Wei Huang <w...@redhat.com>
Reviewed-by: Andrew Jones <drjo...@redhat.com>
Message-id: 1477463301-17175-2-git-send-email-...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 1141d1eb572015c4664788297ca355b278194e9c
https://github.com/qemu/qemu/commit/1141d1eb572015c4664788297ca355b278194e9c
Author: Wei Huang <w...@redhat.com>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
arm: virt: add PMU property to mach-virt machine type
CPU vPMU is now turned ON by default, but this feature wasn't introduced
until virt-2.7 machine type. To solve this problem, this patch adds a
PMU option in machine state, which is used to control CPU's vPMU status.
This PMU option is not exposed to command line and is turned off in
virt-2.6 machine type.
Reviewed-by: Andrew Jones <drjo...@redhat.com>
Signed-off-by: Wei Huang <w...@redhat.com>
Message-id: 1477463301-17175-3-git-send-email-...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 14da5821010b3fd68e25f2193805c43e402bd33a
https://github.com/qemu/qemu/commit/14da5821010b3fd68e25f2193805c43e402bd33a
Author: Guenter Roeck <li...@roeck-us.net>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/arm/spitz.c
Log Message:
-----------
hw/arm/spitz: Fix reset handling
Using the CPU reset handler for resets triggered by writing into
gpio pins other than GPIO01 is not appropriate and does not work,
since the reset triggered by writing into GPIO01 is configurable.
Use a separate reset handler for spitz to reset the entire system
and not just the CPU.
Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Message-id: 1477597646-24111-1-git-send-email-li...@roeck-us.net
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d26a10e232eb18bf9e32dc2366231715bfd1d5b4
https://github.com/qemu/qemu/commit/d26a10e232eb18bf9e32dc2366231715bfd1d5b4
Author: Guenter Roeck <li...@roeck-us.net>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/arm/tosa.c
Log Message:
-----------
hw/arm/tosa: Fix reset handling
Using the CPU reset handler for resets triggered by writing into
gpio pins other than GPIO01 is not appropriate and does not work,
since the reset triggered by writing into GPIO01 is configurable.
Use a separate reset handler for tosa to reset the entire system
and not just the CPU.
Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Message-id: 1477597646-24111-2-git-send-email-li...@roeck-us.net
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 4178c782f85530d261058abdccc734aa9b7c89ca
https://github.com/qemu/qemu/commit/4178c782f85530d261058abdccc734aa9b7c89ca
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2016-10-31 (Mon, 31 Oct 2016)
Changed paths:
M hw/arm/cubieboard.c
M hw/arm/pxa2xx.c
M hw/arm/spitz.c
M hw/arm/tosa.c
M hw/arm/versatilepb.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/char/cadence_uart.c
M hw/gpio/imx_gpio.c
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/cpu64.c
M target-arm/kvm64.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161028'
into staging
target-arm queue:
* Fix reset GPIO handling for spitz, tosa boards
* virt: add 'pmu' property for configuring whether to expose the
vPMU to the guest
* char: cadence: correct reset value for baud rate registers
* versatilepb: do not run if user asks for more than 256MB RAM
* pxa2xx: Set value default values for CCCR and CKEN on PXA255
* arm: cubieboard: Add support for initrd
* i.MX: Fix GPIO ISR register write
# gpg: Signature made Fri 28 Oct 2016 15:56:56 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>"
# gpg: aka "Peter Maydell <pmayd...@gmail.com>"
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20161028:
hw/arm/tosa: Fix reset handling
hw/arm/spitz: Fix reset handling
arm: virt: add PMU property to mach-virt machine type
arm: Add an option to turn on/off vPMU support
char: cadence: correct reset value for baud rate registers
versatilepb: do not run if user asks for more than 256MB RAM
hw/arm/pxa2xx: Set value default values for CCCR and CKEN on PXA255
arm: cubieboard: Add support for initrd
i.MX: Fix GPIO ISR register write
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/5273a45e7521...4178c782f855
