Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 5ede82b8ccb652382c106d53f656ed67997d76e8
      
https://github.com/qemu/qemu/commit/5ede82b8ccb652382c106d53f656ed67997d76e8
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add armv7m_nvic_set_pending_derived()

In order to support derived exceptions (exceptions generated in
the course of trying to take an exception), we need to be able
to handle prioritizing whether to take the original exception
or the derived exception.

We do this by introducing a new function
armv7m_nvic_set_pending_derived() which the exception-taking code in
helper.c will call when a derived exception occurs.  Derived
exceptions are dealt with mostly like normal pending exceptions, so
we share the implementation with the armv7m_nvic_set_pending()
function.

Note that the way we structure this is significantly different
from the v8M Arm ARM pseudocode: that does all the prioritization
logic in the DerivedLateArrival() function, whereas we choose to
let the existing "identify highest priority exception" logic
do the prioritization for us. The effect is the same, though.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1517324542-6607-2-git-send-email-peter.mayd...@linaro.org


  Commit: 6c9485188170e11ad31ce477c8ce200b8e8ce59d
      
https://github.com/qemu/qemu/commit/6c9485188170e11ad31ce477c8ce200b8e8ce59d
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Split "get pending exception info" from "acknowledge it"

Currently armv7m_nvic_acknowledge_irq() does three things:
 * make the current highest priority pending interrupt active
 * return a bool indicating whether that interrupt is targeting
   Secure or NonSecure state
 * implicitly tell the caller which is the highest priority
   pending interrupt by setting env->v7m.exception

We need to split these jobs, because v7m_exception_taken()
needs to know whether the pending interrupt targets Secure so
it can choose to stack callee-saves registers or not, but it
must not make the interrupt active until after it has done
that stacking, in case the stacking causes a derived exception.
Similarly, it needs to know the number of the pending interrupt
so it can read the correct vector table entry before the
interrupt is made active, because vector table reads might
also cause a derived exception.

Create a new armv7m_nvic_get_pending_irq_info() function which simply
returns information about the highest priority pending interrupt, and
use it to rearrange the v7m_exception_taken() code so we don't
acknowledge the exception until we've done all the things which could
possibly cause a derived exception.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 1517324542-6607-3-git-send-email-peter.mayd...@linaro.org


  Commit: 0094ca70e165cfb69882fa2e100d935d45f1c983
      
https://github.com/qemu/qemu/commit/0094ca70e165cfb69882fa2e100d935d45f1c983
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add ignore_stackfaults argument to v7m_exception_taken()

In the v8M architecture, if the process of taking an exception
results in a further exception this is called a derived exception
(for example, an MPU exception when writing the exception frame to
memory). If the derived exception happens while pushing the initial
stack frame, we must ignore any subsequent possible exception
pushing the callee-saves registers.

In preparation for making the stack writes check for exceptions,
add a return value from v7m_push_stack() and a new parameter to
v7m_exception_taken(), so that the former can tell the latter that
it needs to ignore failures to write to the stack. We also plumb
the argument through to v7m_push_callee_stack(), which is where
the code to ignore the failures will be.

(Note that the v8M ARM pseudocode structures this slightly differently:
derived exceptions cause the attempt to process the original
exception to be abandoned; then at the top level it calls
DerivedLateArrival to prioritize the derived exception and call
TakeException from there. We choose to let the NVIC do the prioritization
and continue forward with a call to TakeException which will then
take either the original or the derived exception. The effect is
the same, but this structure works better for QEMU because we don't
have a convenient top level place to do the abandon-and-retry logic.)

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1517324542-6607-4-git-send-email-peter.mayd...@linaro.org


  Commit: fd592d890ec40e3686760de84044230a8ebb1eb3
      
https://github.com/qemu/qemu/commit/fd592d890ec40e3686760de84044230a8ebb1eb3
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Make v7M exception entry stack push check MPU

The memory writes done to push registers on the stack
on exception entry in M profile CPUs are supposed to
go via MPU permissions checks, which may cause us to
take a derived exception instead of the original one of
the MPU lookup fails. We were implementing these as
always-succeeds direct writes to physical memory.
Rewrite v7m_push_stack() to do the necessary checks.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1517324542-6607-5-git-send-email-peter.mayd...@linaro.org


  Commit: 65b4234ff73a4d4865438ce30bdfaaa499464efa
      
https://github.com/qemu/qemu/commit/65b4234ff73a4d4865438ce30bdfaaa499464efa
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Make v7m_push_callee_stack() honour MPU

Make v7m_push_callee_stack() honour the MPU by using the
new v7m_stack_write() function. We return a flag to indicate
whether the pushes failed, which we can then use in
v7m_exception_taken() to cause us to handle the derived
exception correctly.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 1517324542-6607-6-git-send-email-peter.mayd...@linaro.org


  Commit: 600c33f24752a00e81e9372261e35c2befea612b
      
https://github.com/qemu/qemu/commit/600c33f24752a00e81e9372261e35c2befea612b
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Make exception vector loads honour the SAU

Make the load of the exception vector from the vector table honour
the SAU and any bus error on the load (possibly provoking a derived
exception), rather than simply aborting if the load fails.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1517324542-6607-7-git-send-email-peter.mayd...@linaro.org


  Commit: 95695effe8caa552b8f243bceb3a08de4003c882
      
https://github.com/qemu/qemu/commit/95695effe8caa552b8f243bceb3a08de4003c882
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Handle exceptions during exception stack pop

Handle possible MPU faults, SAU faults or bus errors when
popping register state off the stack during exception return.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 1517324542-6607-8-git-send-email-peter.mayd...@linaro.org


  Commit: 90b827d131812d7f0a8abb13dba1942a2bcee821
      
https://github.com/qemu/qemu/commit/90b827d131812d7f0a8abb13dba1942a2bcee821
  Author: Ard Biesheuvel <ard.biesheu...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/crypto_helper.c
    M target/arm/helper.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: implement SHA-512 instructions

This implements emulation of the new SHA-512 instructions that have
been added as an optional extensions to the ARMv8 Crypto Extensions
in ARM v8.2.

Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Message-id: 20180207111729.15737-2-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: cd270ade74ea86467f393a9fb9c54c4f1148c28f
      
https://github.com/qemu/qemu/commit/cd270ade74ea86467f393a9fb9c54c4f1148c28f
  Author: Ard Biesheuvel <ard.biesheu...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: implement SHA-3 instructions

This implements emulation of the new SHA-3 instructions that have
been added as an optional extensions to the ARMv8 Crypto Extensions
in ARM v8.2.

Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Message-id: 20180207111729.15737-3-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 80d6f4c6bbb718f343a832df8dee15329cc7686c
      
https://github.com/qemu/qemu/commit/80d6f4c6bbb718f343a832df8dee15329cc7686c
  Author: Ard Biesheuvel <ard.biesheu...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/crypto_helper.c
    M target/arm/helper.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: implement SM3 instructions

This implements emulation of the new SM3 instructions that have
been added as an optional extension to the ARMv8 Crypto Extensions
in ARM v8.2.

Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Message-id: 20180207111729.15737-4-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: b6577bcd251ca0d57ae1de149e3c706b38f21587
      
https://github.com/qemu/qemu/commit/b6577bcd251ca0d57ae1de149e3c706b38f21587
  Author: Ard Biesheuvel <ard.biesheu...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/crypto_helper.c
    M target/arm/helper.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: implement SM4 instructions

This implements emulation of the new SM4 instructions that have
been added as an optional extension to the ARMv8 Crypto Extensions
in ARM v8.2.

Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Message-id: 20180207111729.15737-5-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 955f56d44a73d74016b2e71765d984ac7a6db1dc
      
https://github.com/qemu/qemu/commit/955f56d44a73d74016b2e71765d984ac7a6db1dc
  Author: Ard Biesheuvel <ard.biesheu...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M linux-user/elfload.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support

Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to
AArch64 user mode emulation.

Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Message-id: 20180207111729.15737-6-ard.biesheu...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: fd1e5c81796454b6459f44bef8759a970eb9e92a
      
https://github.com/qemu/qemu/commit/fd1e5c81796454b6459f44bef8759a970eb9e92a
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/sd/sdhci-internal.h
    M hw/sd/sdhci.c
    M include/hw/sd/sdhci.h

  Log Message:
  -----------
  sdhci: Add i.MX specific subtype of SDHCI

IP block found on several generations of i.MX family does not use
vanilla SDHCI implementation and it comes with a number of quirks.

Introduce i.MX SDHCI subtype of SDHCI block to add code necessary to
support unmodified Linux guest driver.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
[PMM: define and use ESDHC_UNDOCUMENTED_REG27]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: df2a5cf4c83de02376fe90e925219c6b9d1821d7
      
https://github.com/qemu/qemu/commit/df2a5cf4c83de02376fe90e925219c6b9d1821d7
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/arm/fsl-imx6.c

  Log Message:
  -----------
  hw: i.MX: Convert i.MX6 to use TYPE_IMX_USDHC

Convert i.MX6 to use TYPE_IMX_USDHC since that's what real HW comes
with.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e9e0ef15d2357eca058af71c35eba51093b0c0fb
      
https://github.com/qemu/qemu/commit/e9e0ef15d2357eca058af71c35eba51093b0c0fb
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/imx7_ccm.c
    A include/hw/misc/imx7_ccm.h

  Log Message:
  -----------
  i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks

Add minimal code needed to allow upstream Linux guest to boot.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 067e68e7041ec6eff73dd053876e22eaf1d4cb00
      
https://github.com/qemu/qemu/commit/067e68e7041ec6eff73dd053876e22eaf1d4cb00
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/imx2_wdt.c
    A include/hw/misc/imx2_wdt.h

  Log Message:
  -----------
  i.MX: Add code to emulate i.MX2 watchdog IP block

Add enough code to emulate i.MX2 watchdog IP block so it would be
possible to reboot the machine running Linux Guest.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0a7bc1c0457a803a89d6506e97d5b035992c7dff
      
https://github.com/qemu/qemu/commit/0a7bc1c0457a803a89d6506e97d5b035992c7dff
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/imx7_snvs.c
    A include/hw/misc/imx7_snvs.h

  Log Message:
  -----------
  i.MX: Add code to emulate i.MX7 SNVS IP-block

Add code to emulate SNVS IP-block. Currently only the bits needed to
be able to emulate machine shutdown are implemented.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0999e87fa5b45f579670a48f168c77f6235e996f
      
https://github.com/qemu/qemu/commit/0999e87fa5b45f579670a48f168c77f6235e996f
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/imx_gpcv2.c
    A include/hw/intc/imx_gpcv2.h

  Log Message:
  -----------
  i.MX: Add code to emulate GPCv2 IP block

Add minimal code needed to allow upstream Linux guest to boot.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a62bf59fd97c15e95e271adb318135fbe0277730
      
https://github.com/qemu/qemu/commit/a62bf59fd97c15e95e271adb318135fbe0277730
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/timer/imx_gpt.c
    M include/hw/timer/imx_gpt.h

  Log Message:
  -----------
  i.MX: Add i.MX7 GPT variant

Add minimal code needed to allow upstream Linux guest to boot.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 30b2f8709d16b1ed2255552ac90935ebab542385
      
https://github.com/qemu/qemu/commit/30b2f8709d16b1ed2255552ac90935ebab542385
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/imx7_gpr.c
    M hw/misc/trace-events
    A include/hw/misc/imx7_gpr.h

  Log Message:
  -----------
  i.MX: Add implementation of i.MX7 GPR IP block

Add minimal code needed to allow upstream Linux guest to boot.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a24273bba858d61f75ab0e98871f7691988fd0ce
      
https://github.com/qemu/qemu/commit/a24273bba858d61f75ab0e98871f7691988fd0ce
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/usb/Makefile.objs
    A hw/usb/chipidea.c
    A include/hw/usb/chipidea.h

  Log Message:
  -----------
  usb: Add basic code to emulate Chipidea USB IP

Add code to emulate Chipidea USB IP (used in i.MX SoCs). Tested to
work against:

-usb -drive if=none,id=stick,file=usb.img,format=raw -device \
 usb-storage,bus=usb-bus.0,drive=stick

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 4cbca7d9b4de5ecf6a8447b2eba89d591717f6c4
      
https://github.com/qemu/qemu/commit/4cbca7d9b4de5ecf6a8447b2eba89d591717f6c4
  Author: Andrey Smirnov <andrew.smir...@gmail.com>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/arm/boot.c
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm: Move virt's PSCI DT fixup code to arm/boot.c

Move virt's PSCI DT fixup code to arm/boot.c and set this fixup to
happen automatically for every board that doesn't mark "psci-conduit"
as disabled. This way emulated boards other than "virt" that rely on
PSIC for SMP could benefit from that code.

Cc: Peter Maydell <peter.mayd...@linaro.org>
Cc: Jason Wang <jasow...@redhat.com>
Cc: Philippe Mathieu-Daudé <f4...@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelb...@zoho.com>
Cc: Michael S. Tsirkin <m...@redhat.com>
Cc: qemu-de...@nongnu.org
Cc: qemu-...@nongnu.org
Cc: yurov...@gmail.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c39c2b9043ec59516c80f2c6f3e8193e99d04d4b
      
https://github.com/qemu/qemu/commit/c39c2b9043ec59516c80f2c6f3e8193e99d04d4b
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/machine.c
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Expand vector registers for SVE

Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg.
The previous patches have made the change in representation
relatively painless.

Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180123035349.24538-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3c7d30866fd1f56e5945726221410e0d8d535033
      
https://github.com/qemu/qemu/commit/3c7d30866fd1f56e5945726221410e0d8d535033
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add predicate registers for SVE

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180123035349.24538-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: ef401601d5561f9805102695d5e65d72594f7020
      
https://github.com/qemu/qemu/commit/ef401601d5561f9805102695d5e65d72594f7020
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/machine.c

  Log Message:
  -----------
  target/arm: Add SVE to migration state

Save the high parts of the Zregs and all of the Pregs.
The ZCR_ELx registers are migrated via the CP mechanism.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180123035349.24538-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 5be5e8eda78474f6e89a54af12ee6f44234115ed
      
https://github.com/qemu/qemu/commit/5be5e8eda78474f6e89a54af12ee6f44234115ed
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add ZCR_ELx

Define ZCR_EL[1-3].

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180123035349.24538-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 1db5e96c54d8b3d1df0a6fed6771390be6b010da
      
https://github.com/qemu/qemu/commit/1db5e96c54d8b3d1df0a6fed6771390be6b010da
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Add SVE state to TB->FLAGS

Add both SVE exception state and vector length.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180123035349.24538-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: bd55947884b5421697d186016b0e57b1d6643fe0
      
https://github.com/qemu/qemu/commit/bd55947884b5421697d186016b0e57b1d6643fe0
  Author: Christoffer Dall <christoffer.d...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM

KVM doesn't support emulating a GICv3 in userspace, only GICv2.  We
currently attempt this anyway, and as a result a KVM guest doesn't
receive interrupts and the user is left wondering why.  Report an error
to the user if this particular combination is requested.

Signed-off-by: Christoffer Dall <christoffer.d...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20180201205307.30343-1-christoffer.d...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 384c6c03fb687bea239a5990a538c4bc50fdcecb
      
https://github.com/qemu/qemu/commit/384c6c03fb687bea239a5990a538c4bc50fdcecb
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm/translate.c: Fix missing 'break' for TT insns

The code where we added the TT instruction was accidentally
missing a 'break', which meant that after generating the code
to execute the TT we would fall through to 'goto illegal_op'
and generate code to take an UNDEF insn.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20180206103941.13985-1-peter.mayd...@linaro.org


  Commit: bbba7757bacc9f890a3f028d328b4b429dbe78ec
      
https://github.com/qemu/qemu/commit/bbba7757bacc9f890a3f028d328b4b429dbe78ec
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/core/generic-loader.c

  Log Message:
  -----------
  hw/core/generic-loader: Allow PC to be set on command line

The documentation for the generic loader claims that you can
set the PC for a CPU with an option of the form
  -device loader,cpu-num=0,addr=0x10000004

However if you try this QEMU complains:
  cpu_num must be specified when setting a program counter

This is because we were testing against 0 rather than CPU_NONE.

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20180205150426.20542-1-peter.mayd...@linaro.org


  Commit: f31cd9e4e2172a4807f390194978c61e717791d2
      
https://github.com/qemu/qemu/commit/f31cd9e4e2172a4807f390194978c61e717791d2
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-02-09 (Fri, 09 Feb 2018)

  Changed paths:
    M hw/arm/boot.c
    M hw/arm/fsl-imx6.c
    M hw/arm/virt.c
    M hw/core/generic-loader.c
    M hw/intc/Makefile.objs
    M hw/intc/armv7m_nvic.c
    A hw/intc/imx_gpcv2.c
    M hw/intc/trace-events
    M hw/misc/Makefile.objs
    A hw/misc/imx2_wdt.c
    A hw/misc/imx7_ccm.c
    A hw/misc/imx7_gpr.c
    A hw/misc/imx7_snvs.c
    M hw/misc/trace-events
    M hw/sd/sdhci-internal.h
    M hw/sd/sdhci.c
    M hw/timer/imx_gpt.c
    M hw/usb/Makefile.objs
    A hw/usb/chipidea.c
    A include/hw/intc/imx_gpcv2.h
    A include/hw/misc/imx2_wdt.h
    A include/hw/misc/imx7_ccm.h
    A include/hw/misc/imx7_gpr.h
    A include/hw/misc/imx7_snvs.h
    M include/hw/sd/sdhci.h
    M include/hw/timer/imx_gpt.h
    A include/hw/usb/chipidea.h
    M linux-user/elfload.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/crypto_helper.c
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/kvm_arm.h
    M target/arm/machine.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180209' 
into staging

target-arm queue:
 * Support M profile derived exceptions on exception entry and exit
 * Implement AArch64 v8.2 crypto insns (SHA-512, SHA-3, SM3, SM4)
 * Implement working i.MX6 SD controller
 * Various devices preparatory to i.MX7 support
 * Preparatory patches for SVE emulation
 * v8M: Fix bug in implementation of 'TT' insn
 * Give useful error if user tries to use userspace GICv3 with KVM

# gpg: Signature made Fri 09 Feb 2018 11:01:23 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>"
# gpg:                 aka "Peter Maydell <pmayd...@gmail.com>"
# gpg:                 aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180209: (30 commits)
  hw/core/generic-loader: Allow PC to be set on command line
  target/arm/translate.c: Fix missing 'break' for TT insns
  target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM
  target/arm: Add SVE state to TB->FLAGS
  target/arm: Add ZCR_ELx
  target/arm: Add SVE to migration state
  target/arm: Add predicate registers for SVE
  target/arm: Expand vector registers for SVE
  hw/arm: Move virt's PSCI DT fixup code to arm/boot.c
  usb: Add basic code to emulate Chipidea USB IP
  i.MX: Add implementation of i.MX7 GPR IP block
  i.MX: Add i.MX7 GPT variant
  i.MX: Add code to emulate GPCv2 IP block
  i.MX: Add code to emulate i.MX7 SNVS IP-block
  i.MX: Add code to emulate i.MX2 watchdog IP block
  i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks
  hw: i.MX: Convert i.MX6 to use TYPE_IMX_USDHC
  sdhci: Add i.MX specific subtype of SDHCI
  target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support
  target/arm: implement SM4 instructions
  ...

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


Compare: https://github.com/qemu/qemu/compare/fdcbebe4519e...f31cd9e4e217

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