Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: eab158625703457b8aa6ce6c1b88a0e2c4899cc5
https://github.com/qemu/qemu/commit/eab158625703457b8aa6ce6c1b88a0e2c4899cc5
Author: Michael Clark <m...@sifive.com>
Date: 2018-03-28 (Wed, 28 Mar 2018)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
RISC-V: Convert cpu definition to future model
- Model borrowed from target/sh4/cpu.c
- Rewrote riscv_cpu_list to use object_class_get_list
- Dropped 'struct RISCVCPUInfo' and used TypeInfo array
- Replaced riscv_cpu_register_types with DEFINE_TYPES
- Marked base class as abstract
- Fixes -cpu list
Cc: Igor Mammedov <imamm...@redhat.com>
Cc: Sagar Karandikar <sag...@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <pal...@sifive.com>
Signed-off-by: Michael Clark <m...@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Igor Mammedov <imamm...@redhat.com>
Commit: 33b4f859f1e1ea6722d10c3e9c0e3d85afb44ff4
https://github.com/qemu/qemu/commit/33b4f859f1e1ea6722d10c3e9c0e3d85afb44ff4
Author: Michael Clark <m...@sifive.com>
Date: 2018-03-28 (Wed, 28 Mar 2018)
Changed paths:
M disas/riscv.c
Log Message:
-----------
RISC-V: Fix incorrect disassembly for addiw
This fixes a bug in the disassembler constraints used
to lift instructions into pseudo-instructions, whereby
addiw instructions are always lifted to sext.w instead
of just lifting addiw with a zero immediate.
An associated fix has been made to the metadata used to
machine generate the disseasembler:
https://github.com/michaeljclark/riscv-meta/
commit/4a6b2f3898430768acfe201405224d2ea31e1477
Cc: Sagar Karandikar <sag...@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <pal...@sifive.com>
Cc: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Michael Clark <m...@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 47d3b60858d90ac8a0cc3a72af7f95c96781125a
https://github.com/qemu/qemu/commit/47d3b60858d90ac8a0cc3a72af7f95c96781125a
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-03-28 (Wed, 28 Mar 2018)
Changed paths:
M disas/riscv.c
M target/riscv/cpu.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/riscv/tags/riscv-qemu-2.12-important-fixes' into staging
RISC-V: Important fixes for QEMU 2.12
This series includes changes that are considered important.
i.e. correct user-visible bugs that are exercised by common
operations such as -cpu list (CPU model changes) or -d in_asm
(fix for disassembly of addiw)
# gpg: Signature made Wed 28 Mar 2018 21:34:57 BST
# gpg: using DSA key 6BF1D7B357EF3E4F
# gpg: Good signature from "Michael Clark <michaeljcl...@mac.com>"
# gpg: aka "Michael Clark <m...@sifive.com>"
# gpg: aka "Michael Clark <mich...@metaparadigm.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7C99 930E B17C D8BA 073D 5EFA 6BF1 D7B3 57EF 3E4F
* remotes/riscv/tags/riscv-qemu-2.12-important-fixes:
RISC-V: Fix incorrect disassembly for addiw
RISC-V: Convert cpu definition to future model
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/043289bef4d9...47d3b60858d9
