Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: a5a5f5e2e437db6c19164b734f838a7bf9e0c5ec
https://github.com/qemu/qemu/commit/a5a5f5e2e437db6c19164b734f838a7bf9e0c5ec
Author: Alex Bennée <alex.ben...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
fpu/softfloat: int_to_float ensure r fully initialised
Reported by Coverity (CID1390635). We ensure this for uint_to_float
later on so we might as well mirror that.
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 333583757c5e910b040bef793974773635ce1918
https://github.com/qemu/qemu/commit/333583757c5e910b040bef793974773635ce1918
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
In float-to-integer conversion, if the floating point input
converts exactly to the largest or smallest integer that
fits in to the result type, this is not an overflow.
In this situation we were producing the correct result value,
but were incorrectly setting the Invalid flag.
For example for Arm A64, "FCVTAS w0, d0" on an input of
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
Fix the boundary case to take the right half of the if()
statements.
This fixes a regression from 2.11 introduced by the softfloat
refactoring.
Cc: qemu-sta...@nongnu.org
Fixes: ab52f973a50
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180510140141.12120-1-peter.mayd...@linaro.org
Commit: bcc531f0364796104df4443d17f99b5fb494eca2
https://github.com/qemu/qemu/commit/bcc531f0364796104df4443d17f99b5fb494eca2
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Fix fp_status_f16 tininess before rounding
In commit d81ce0ef2c4f105 we added an extra float_status field
fp_status_fp16 for Arm, but forgot to initialize it correctly
by setting it to float_tininess_before_rounding. This currently
will only cause problems for the new V8_FP16 feature, since the
float-to-float conversion code doesn't use it yet. The effect
would be that we failed to set the Underflow IEEE exception flag
in all the cases where we should.
Add the missing initialization.
Fixes: d81ce0ef2c4f105
Cc: qemu-sta...@nongnu.org
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20180512004311.9299-16-richard.hender...@linaro.org
Commit: 68130236e30a1ec64363f4915349feee181bfbc1
https://github.com/qemu/qemu/commit/68130236e30a1ec64363f4915349feee181bfbc1
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FMOV (general) for fp16
Adding the fp16 moves to/from general registers.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20180512003217.9105-2-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 8c738d430796edeae5e13d6daf0895c02c62bd54
https://github.com/qemu/qemu/commit/8c738d430796edeae5e13d6daf0895c02c62bd54
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
No sense in emitting code after the exception.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20180512003217.9105-3-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 564a0632504fad840491aa9a59453f4e64a316c4
https://github.com/qemu/qemu/commit/564a0632504fad840491aa9a59453f4e64a316c4
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/helper.c
M target/arm/helper.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FCVT (scalar, integer) for fp16
Cc: qemu-sta...@nongnu.org
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20180512003217.9105-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 2752728016bef06e7c9cfb961019272859beeca4
https://github.com/qemu/qemu/commit/2752728016bef06e7c9cfb961019272859beeca4
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FCVT (scalar, fixed-point) for fp16
Cc: qemu-sta...@nongnu.org
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20180512003217.9105-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 3d99d931266eaeaf7e83703a53f32232cd6faad7
https://github.com/qemu/qemu/commit/3d99d931266eaeaf7e83703a53f32232cd6faad7
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Introduce and use read_fp_hreg
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20180512003217.9105-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: b8f5171cf01420a9f0ee895c5591e9b9914f391a
https://github.com/qemu/qemu/commit/b8f5171cf01420a9f0ee895c5591e9b9914f391a
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FP data-processing (2 source) for fp16
We missed all of the scalar fp16 binary operations.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20180512003217.9105-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 95f9864fde6078e2d2c036a07cc4fe44f199be96
https://github.com/qemu/qemu/commit/95f9864fde6078e2d2c036a07cc4fe44f199be96
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FP data-processing (3 source) for fp16
We missed all of the scalar fp16 fma operations.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20180512003217.9105-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 7a1929256ea1a03df12625e75ed571c60dca5bfb
https://github.com/qemu/qemu/commit/7a1929256ea1a03df12625e75ed571c60dca5bfb
Author: Alex Bennée <alex.ben...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/helper-a64.c
M target/arm/helper-a64.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FCMP for fp16
These where missed out from the rest of the half-precision work.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180512003217.9105-9-richard.hender...@linaro.org
[rth: Diagnose lack of FP16 before fp_access_check]
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: ace97feef3613194900d4eb9ffc6819b840fbaeb
https://github.com/qemu/qemu/commit/ace97feef3613194900d4eb9ffc6819b840fbaeb
Author: Alex Bennée <alex.ben...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FCSEL for fp16
These were missed out from the rest of the half-precision work.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180512003217.9105-10-richard.hender...@linaro.org
[rth: Fix erroneous check vs type]
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 6ba28ddb9be37bdb67e3e38007a53ccbdcd010df
https://github.com/qemu/qemu/commit/6ba28ddb9be37bdb67e3e38007a53ccbdcd010df
Author: Alex Bennée <alex.ben...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FMOV (immediate) for fp16
All the hard work is already done by vfp_expand_imm, we just need to
make sure we pick up the correct size.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180512003217.9105-11-richard.hender...@linaro.org
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 905edee9101c54cda5b72286b7f7607cf1c3c4d1
https://github.com/qemu/qemu/commit/905edee9101c54cda5b72286b7f7607cf1c3c4d1
Author: Alex Bennée <alex.ben...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Fix sqrt_f16 exception raising
We are meant to explicitly pass fpst, not cpu_env.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20180512003217.9105-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: f6fb1f9b319feac09119848d206b07640ddd39e7
https://github.com/qemu/qemu/commit/f6fb1f9b319feac09119848d206b07640ddd39e7
Author: Philippe Mathieu-Daudé <f4...@amsat.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M hw/sd/sd.c
Log Message:
-----------
sdcard: Correct CRC16 offset in sd_function_switch()
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
The block length is predefined to 512 bits
and "4.10.2 SD Status":
The SD Status contains status bits that are related to the SD Memory Card
proprietary features and may be used for future application-specific usage.
The size of the SD Status is one data block of 512 bit. The content of this
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
Thus the 16-bit CRC goes at offset 64.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-id: 20180509060104.4458-3-f4...@amsat.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: ae7651804748c6b479d5ae09aeac4edb9c44f76e
https://github.com/qemu/qemu/commit/ae7651804748c6b479d5ae09aeac4edb9c44f76e
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M accel/tcg/cpu-exec.c
M include/qemu/log.h
M util/log.c
Log Message:
-----------
tcg: Optionally log FPU state in TCG -d cpu logging
Usually the logging of the CPU state produced by -d cpu is sufficient
to diagnose problems, but sometimes you want to see the state of
the floating point registers as well. We don't want to enable that
by default as it adds a lot of extra data to the log; instead,
allow it to be optionally enabled via -d fpu.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20180510130024.31678-1-peter.mayd...@linaro.org
Commit: 0275e6b66c0947f83ad0d8dd687eadbcbf0c5ec5
https://github.com/qemu/qemu/commit/0275e6b66c0947f83ad0d8dd687eadbcbf0c5ec5
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2018-05-15 (Tue, 15 May 2018)
Changed paths:
M accel/tcg/cpu-exec.c
M fpu/softfloat.c
M hw/sd/sd.c
M include/qemu/log.h
M target/arm/cpu.c
M target/arm/helper-a64.c
M target/arm/helper-a64.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/translate-a64.c
M util/log.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180515'
into staging
target-arm queue:
* Fix coverity nit in int_to_float code
* Don't set Invalid for float-to-int(MAXINT)
* Fix fp_status_f16 tininess before rounding
* Add various missing insns from the v8.2-FP16 extension
* Fix sqrt_f16 exception raising
* sdcard: Correct CRC16 offset in sd_function_switch()
* tcg: Optionally log FPU state in TCG -d cpu logging
# gpg: Signature made Tue 15 May 2018 15:06:09 BST
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>"
# gpg: aka "Peter Maydell <pmayd...@gmail.com>"
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180515:
tcg: Optionally log FPU state in TCG -d cpu logging
sdcard: Correct CRC16 offset in sd_function_switch()
target/arm: Fix sqrt_f16 exception raising
target/arm: Implement FMOV (immediate) for fp16
target/arm: Implement FCSEL for fp16
target/arm: Implement FCMP for fp16
target/arm: Implement FP data-processing (3 source) for fp16
target/arm: Implement FP data-processing (2 source) for fp16
target/arm: Introduce and use read_fp_hreg
target/arm: Implement FCVT (scalar, fixed-point) for fp16
target/arm: Implement FCVT (scalar, integer) for fp16
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
target/arm: Implement FMOV (general) for fp16
target/arm: Fix fp_status_f16 tininess before rounding
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
fpu/softfloat: int_to_float ensure r fully initialised
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/ad1b4ec39caa...0275e6b66c09
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