Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6603d50648901e8b9e6d66ec1142accf0b1df1e6
      
https://github.com/qemu/qemu/commit/6603d50648901e8b9e6d66ec1142accf0b1df1e6
  Author: Petr Tesarik <ptesa...@suse.com>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Fix conversion from uint64 to float128

The significand is passed to normalizeRoundAndPackFloat128() as high
first, low second. The current code passes the integer first, so the
result is incorrectly shifted left by 64 bits.

This bug affects the emulation of s390x instruction CXLGBR (convert
from logical 64-bit binary-integer operand to extended BFP result).

Cc: qemu-sta...@nongnu.org
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Petr Tesarik <ptesa...@suse.com>
Message-Id: <20180511071052.1443-1-ptesa...@suse.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: bca52234d1c04e0665f67708bcdef6d805d60adb
      
https://github.com/qemu/qemu/commit/bca52234d1c04e0665f67708bcdef6d805d60adb
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h

  Log Message:
  -----------
  fpu/softfloat: Merge NO_SIGNALING_NANS definitions

Move the ifdef inside the relevant functions instead of
duplicating the function declarations.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: d619bb98fdcda24f9ee3b7a53a4d555228dbca52
      
https://github.com/qemu/qemu/commit/d619bb98fdcda24f9ee3b7a53a4d555228dbca52
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M include/fpu/softfloat.h

  Log Message:
  -----------
  fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan

The new function assumes that the input is an SNaN and
does not double-check.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 0664335a6eb65d684918dd3f1a7f0a3d5b92cbe1
      
https://github.com/qemu/qemu/commit/0664335a6eb65d684918dd3f1a7f0a3d5b92cbe1
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Move softfloat-specialize.h below FloatParts definition

We want to be able to specialize on the canonical representation.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 94933df0e5c34d1a50fc950553f9c9649cae5320
      
https://github.com/qemu/qemu/commit/94933df0e5c34d1a50fc950553f9c9649cae5320
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Canonicalize NaN fraction

Shift the NaN fraction to a canonical position, much like we
do for the fraction of normal numbers.  This will facilitate
manipulation of NaNs within the shared code paths.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 298b468e4389587ab2e8599dd33eff3fbc698011
      
https://github.com/qemu/qemu/commit/298b468e4389587ab2e8599dd33eff3fbc698011
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Introduce parts_is_snan_frac

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: f7e598e264b94d0982e647ac303108781d5eb4fa
      
https://github.com/qemu/qemu/commit/f7e598e264b94d0982e647ac303108781d5eb4fa
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Replace float_class_dnan with parts_default_nan

With a canonical representation of NaNs, we can return the
default nan directly rather than delay the expansion until
the final format is known.

Note one case where we uselessly assigned to a.sign, which was
overwritten/ignored later when expanding float_class_dnan.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 0bcfbcbea548656ff930394f296589728c2a0c5d
      
https://github.com/qemu/qemu/commit/0bcfbcbea548656ff930394f296589728c2a0c5d
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Replace float_class_msnan with parts_silence_nan

With a canonical representation of NaNs, we can silence an SNaN
immediately rather than delay until the final format is known.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 486624fcd3eaca6165ab8401d73bbae6c0fb81c1
      
https://github.com/qemu/qemu/commit/486624fcd3eaca6165ab8401d73bbae6c0fb81c1
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: convert conversion helpers to fpst/ahp_flag

Instead of passing env and leaving it up to the helper to get the
right fpstatus we pass it explicitly. There was already a get_fpstatus
helper for neon for the 32 bit code. We also add an get_ahp_flag() for
passing the state of the alternative FP16 format flag. This leaves
scope for later tracking the AHP state in translation flags.

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 0acb9e7cb341cd767e39ec0875c8706eb2f1c359
      
https://github.com/qemu/qemu/commit/0acb9e7cb341cd767e39ec0875c8706eb2f1c359
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: squash FZ16 behaviour for conversions

The ARM ARM specifies FZ16 is suppressed for conversions. Rather than
pushing this logic into the softfloat code we can simply save the FZ
state and temporarily disable it for the softfloat call.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: ca3a3d5a3141d44aa717dc11e4d33a834a85e1f6
      
https://github.com/qemu/qemu/commit/ca3a3d5a3141d44aa717dc11e4d33a834a85e1f6
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Partial support for ARM Alternative half-precision

For float16 ARM supports an alternative half-precision format which
sacrifices the ability to represent NaN/Inf in return for a higher
dynamic range.  The new FloatFmt flag, arm_althp, is then used to
modify the behaviour of canonicalize and round_canonical with respect
to representation and exception raising.

Usage of this new flag waits until we re-factor float-to-float conversions.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 6fed16b265a4fcc810895bbca4d67e1ae7a89f07
      
https://github.com/qemu/qemu/commit/6fed16b265a4fcc810895bbca4d67e1ae7a89f07
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c
    M include/fpu/softfloat.h

  Log Message:
  -----------
  fpu/softfloat: re-factor float to float conversions

This allows us to delete a lot of additional boilerplate
code which is no longer needed.

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: d7ecc062c4e264f716ed239df931f52adb340508
      
https://github.com/qemu/qemu/commit/d7ecc062c4e264f716ed239df931f52adb340508
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Use floatX_silence_nan when we have already checked for SNaN

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: a9d173dc603af74102c24c1c92d479ba580bbf07
      
https://github.com/qemu/qemu/commit/a9d173dc603af74102c24c1c92d479ba580bbf07
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: e1cf9adf5b5defdc077e9029b9e776201e6a42a7
      
https://github.com/qemu/qemu/commit/e1cf9adf5b5defdc077e9029b9e776201e6a42a7
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/hppa/op_helper.c

  Log Message:
  -----------
  target/hppa: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code.

Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 1c0c951f717e66b4be45611c0d6661a2dff4241c
      
https://github.com/qemu/qemu/commit/1c0c951f717e66b4be45611c0d6661a2dff4241c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/m68k/softfloat.c

  Log Message:
  -----------
  target/m68k: Use floatX_silence_nan when we have already checked for SNaN

Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Laurent Vivier <laur...@vivier.eu>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 4accd4a89f776b0d2a34d1edf74c785549c7f3b9
      
https://github.com/qemu/qemu/commit/4accd4a89f776b0d2a34d1edf74c785549c7f3b9
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/mips/msa_helper.c
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code.

Cc: Aurelien Jarno <aurel...@aurel32.net>
Cc: Yongbok Kim <yongbok....@mips.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: cab3211261b3dad5de3b15fadcca483af5e2b113
      
https://github.com/qemu/qemu/commit/cab3211261b3dad5de3b15fadcca483af5e2b113
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/riscv/fpu_helper.c

  Log Message:
  -----------
  target/riscv: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code.

Cc: Palmer Dabbelt <pal...@sifive.com>
Cc: Sagar Karandikar <sag...@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
Reviewed-by: Michael Clark <m...@sifive.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: d0cfecb50df777d9d97118325d663682598a5a83
      
https://github.com/qemu/qemu/commit/d0cfecb50df777d9d97118325d663682598a5a83
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M target/s390x/fpu_helper.c

  Log Message:
  -----------
  target/s390x: Remove floatX_maybe_silence_nan from conversions

This is now handled properly by the generic softfloat code.

Cc: Alexander Graf <ag...@suse.de>
Reviewed-by: David Hildenbrand <da...@redhat.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 4885312f47c0b3607e36d0568db3d717a79e51a3
      
https://github.com/qemu/qemu/commit/4885312f47c0b3607e36d0568db3d717a79e51a3
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h

  Log Message:
  -----------
  fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN

We have already checked the arguments for SNaN;
we don't need to do it again.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 5240a30dcc6ca85dc9352f351e2cc326402288ed
      
https://github.com/qemu/qemu/commit/5240a30dcc6ca85dc9352f351e2cc326402288ed
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M include/fpu/softfloat.h

  Log Message:
  -----------
  fpu/softfloat: Remove floatX_maybe_silence_nan

These functions are now unused.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 03385dfdaaa2dc31bbd07d13244a6b037bfab4cc
      
https://github.com/qemu/qemu/commit/03385dfdaaa2dc31bbd07d13244a6b037bfab4cc
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M include/fpu/softfloat-types.h
    M target/hppa/cpu.c
    M target/ppc/fpu_helper.c
    M target/sh4/cpu.c
    M target/unicore32/cpu.c

  Log Message:
  -----------
  fpu/softfloat: Specialize on snan_bit_is_one

Only MIPS requires snan_bit_is_one to be variable.  While we are
specializing softfloat behaviour, allow other targets to eliminate
this runtime check.

Cc: Aurelien Jarno <aurel...@aurel32.net>
Cc: Yongbok Kim <yongbok....@mips.com>
Cc: David Gibson <da...@gibson.dropbear.id.au>
Cc: Alexander Graf <ag...@suse.de>
Cc: Guan Xuetao <g...@mprc.pku.edu.cn>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 247d1f2190c5530fd18fe92a145d0a1985fca4e4
      
https://github.com/qemu/qemu/commit/247d1f2190c5530fd18fe92a145d0a1985fca4e4
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Make is_nan et al available to softfloat-specialize.h

We will need these helpers within softfloat-specialize.h, so move
the definitions above the include.  After specialization, they will
not always be used so mark them to avoid the Werror.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 4f251cfd52c7945ebd6ab0d86518b1a9aa51b10c
      
https://github.com/qemu/qemu/commit/4f251cfd52c7945ebd6ab0d86518b1a9aa51b10c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Pass FloatClass to pickNaN

For each operand, pass a single enumeration instead of a pair of booleans.
The commit also merges multiple different ifdef-selected implementations
of pickNaN into a single function whose body is ifdef-selected.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 3bd2dec1a1e8fadb49e3ff2e2633f79e01a25c41
      
https://github.com/qemu/qemu/commit/3bd2dec1a1e8fadb49e3ff2e2633f79e01a25c41
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Pass FloatClass to pickNaNMulAdd

For each operand, pass a single enumeration instead of a pair of booleans.
The commit also merges multiple different ifdef-selected implementations
of pickNaNMulAdd into a single function whose body is ifdef-selected.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 0218a16e540ad416683e19dfbd52f75092507b27
      
https://github.com/qemu/qemu/commit/0218a16e540ad416683e19dfbd52f75092507b27
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan

Isolate the target-specific choice to 2 functions instead of 6.

The code in float16_default_nan was only correct for ARM, MIPS, and X86.
Though float16 support is rare among our targets.

The code in float128_default_nan was arguably wrong for Sparc.  While
QEMU supports the Sparc 128-bit insns, no real cpu enables it.

The code in floatx80_default_nan tried to be over-general.  There are
only two targets that support this format: x86 and m68k.  Thus there
is no point in inventing a value for snan_bit_is_one.

Move routines that no longer have ifdefs out of softfloat-specialize.h.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 8fb3d90203f328d1bebcf7f20934027bfc4e7f3f
      
https://github.com/qemu/qemu/commit/8fb3d90203f328d1bebcf7f20934027bfc4e7f3f
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h

  Log Message:
  -----------
  fpu/softfloat: Clean up parts_default_nan

Reduce the number of ifdefs.  Correct the result for OpenRISC
and TriCore (although TriCore fixed in target-specific code).

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 377ed92679a2a5f838bc0a095112ea5020720fff
      
https://github.com/qemu/qemu/commit/377ed92679a2a5f838bc0a095112ea5020720fff
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nan

Isolate the target-specific choice to 3 functions instead of 6.

The code in floatx80_default_nan tried to be over-general.  There are
only two targets that support this format: x86 and m68k.  Thus there
is no point in inventing a mechanism for snan_bit_is_one.

Move routines that no longer have ifdefs out of softfloat-specialize.h.

Tested-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 681299482681bd56c9628c9a994ab16c6860c358
      
https://github.com/qemu/qemu/commit/681299482681bd56c9628c9a994ab16c6860c358
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2018-05-18 (Fri, 18 May 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    M fpu/softfloat.c
    M include/fpu/softfloat-types.h
    M include/fpu/softfloat.h
    M target/arm/helper-a64.c
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/hppa/cpu.c
    M target/hppa/op_helper.c
    M target/m68k/softfloat.c
    M target/mips/msa_helper.c
    M target/mips/op_helper.c
    M target/ppc/fpu_helper.c
    M target/riscv/fpu_helper.c
    M target/s390x/fpu_helper.c
    M target/sh4/cpu.c
    M target/unicore32/cpu.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20180517' into staging

Roundup of softfloat patches

# gpg: Signature made Thu 17 May 2018 23:44:04 BST
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.hender...@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-fpu-20180517: (28 commits)
  fpu/softfloat: Define floatN_silence_nan in terms of parts_silence_nan
  fpu/softfloat: Clean up parts_default_nan
  fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan
  fpu/softfloat: Pass FloatClass to pickNaNMulAdd
  fpu/softfloat: Pass FloatClass to pickNaN
  fpu/softfloat: Make is_nan et al available to softfloat-specialize.h
  fpu/softfloat: Specialize on snan_bit_is_one
  fpu/softfloat: Remove floatX_maybe_silence_nan
  fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN
  target/s390x: Remove floatX_maybe_silence_nan from conversions
  target/riscv: Remove floatX_maybe_silence_nan from conversions
  target/mips: Remove floatX_maybe_silence_nan from conversions
  target/m68k: Use floatX_silence_nan when we have already checked for SNaN
  target/hppa: Remove floatX_maybe_silence_nan from conversions
  target/arm: Remove floatX_maybe_silence_nan from conversions
  target/arm: Use floatX_silence_nan when we have already checked for SNaN
  fpu/softfloat: re-factor float to float conversions
  fpu/softfloat: Partial support for ARM Alternative half-precision
  target/arm: squash FZ16 behaviour for conversions
  target/arm: convert conversion helpers to fpst/ahp_flag
  ...

Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a4207e3b00e8...681299482681
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