Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: c5b4ee5bb799685e1c5a4a30ab40013a984daded https://github.com/qemu/qemu/commit/c5b4ee5bb799685e1c5a4a30ab40013a984daded Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021)
Changed paths: M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Introduce temporary in gen_add_uw() Following the recent changes in translate.c, gen_add_uw() causes failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these regressions by introducing a temporary. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Message-id: 20210911140016.834071-2-philipp.toms...@vrull.eu Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*") Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: e47fb6c1e96a4e50603c13b8408e0745a09cd867 https://github.com/qemu/qemu/commit/e47fb6c1e96a4e50603c13b8408e0745a09cd867 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: fix clzw implementation to operate on arg1 The refactored gen_clzw() uses ret as its argument, instead of arg1. Fix it. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Message-id: 20210911140016.834071-3-philipp.toms...@vrull.eu Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary") Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 45d1749c1c32f7f44e02f267407cd6bca88fb84a https://github.com/qemu/qemu/commit/45d1749c1c32f7f44e02f267407cd6bca88fb84a Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: clwz must ignore high bits (use shift-left & changed logic) Assume clzw being executed on a register that is not sign-extended, such as for the following sequence that uses (1ULL << 63) | 392 as the operand to clzw: bseti a2, zero, 63 addi a2, a2, 392 clzw a3, a2 The correct result of clzw would be 23, but the current implementation returns -32 (as it performs a 64bit clz, which results in 0 leading zero bits, and then subtracts 32). Fix this by changing the implementation to: 1. shift the original register up by 32 2. performs a target-length (64bit) clz 3. return 32 if no bits are set Marking this instruction as 'w-form' (i.e., setting ctx->w) would not correctly model the behaviour, as the instruction should not perform a zero-extensions on the input (after all, it is not a .uw instruction) and the result is always in the range 0..32 (so neither a sign-extension nor a zero-extension on the result will ever be needed). Consequently, we do not set ctx->w and mark the instruction as EXT_NONE. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: LIU Zhiwei<zhiwei_...@c-sky.com> Message-id: 20210911140016.834071-4-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 878dd0e9ac18af657dcbdb598bb2eb1278606d3a https://github.com/qemu/qemu/commit/878dd0e9ac18af657dcbdb598bb2eb1278606d3a Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/cpu.c M target/riscv/cpu.h Log Message: ----------- target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for these in target/riscv/cpu.[ch]. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Bin Meng <bmeng...@gmail.com> Message-id: 20210911140016.834071-5-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: bb4dc158e084c3293b553c37f3ace99997aeff6f https://github.com/qemu/qemu/commit/bb4dc158e084c3293b553c37f3ace99997aeff6f Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Reassign instructions to the Zba-extension The following instructions are part of Zba: - add.uw (RV64 only) - sh[123]add (RV32 and RV64) - sh[123]add.uw (RV64-only) - slli.uw (RV64-only) Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Acked-by: Bin Meng <bmeng...@gmail.com> Message-id: 20210911140016.834071-6-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: dd98a74034a4ae6a80162f2db42e67260875eb5e https://github.com/qemu/qemu/commit/dd98a74034a4ae6a80162f2db42e67260875eb5e Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Remove the W-form instructions from Zbs Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form instructions for Zbs (single-bit instructions). Remove them. Note that these instructions had already been removed for the 0.93 version of the draft-B extention and have not been present in the binutils patches circulating in January 2021. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Acked-by: Bin Meng <bmeng...@gmail.com> Message-id: 20210911140016.834071-7-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 628d8c88c14e6ee8eef0c6d3b7178dbfc7770f03 https://github.com/qemu/qemu/commit/628d8c88c14e6ee8eef0c6d3b7178dbfc7770f03 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Acked-by: Bin Meng <bmeng...@gmail.com> Message-id: 20210911140016.834071-8-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: f36a4a89aad493990084a9b540ed511cb66701ce https://github.com/qemu/qemu/commit/f36a4a89aad493990084a9b540ed511cb66701ce Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Reassign instructions to the Zbs-extension The following instructions are part of Zbs: - b{set,clr,ext,inv} - b{set,clr,ext,inv}i Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Acked-by: Bin Meng <bmeng...@gmail.com> Message-id: 20210911140016.834071-9-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: fd4b81a304a5d50e719019d22eacca2d8ef4de69 https://github.com/qemu/qemu/commit/fd4b81a304a5d50e719019d22eacca2d8ef4de69 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/bitmanip_helper.c M target/riscv/helper.h M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Add instructions of the Zbc-extension The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210911140016.834071-10-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 16c38f36f5cb42bbfe7b9cd4bb29206a3ecab760 https://github.com/qemu/qemu/commit/16c38f36f5cb42bbfe7b9cd4bb29206a3ecab760 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Reassign instructions to the Zbb-extension This reassigns the instructions that are part of Zbb into it, with the notable exceptions of the instructions (rev8, zext.w and orc.b) that changed due to gorci, grevi and pack not being part of Zb[abcs]. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Acked-by: Bin Meng <bmeng...@gmail.com> Message-id: 20210911140016.834071-11-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: d7a4fcb03433edefd19b7db3c4d20ed750b5833b https://github.com/qemu/qemu/commit/d7a4fcb03433edefd19b7db3c4d20ed750b5833b Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/bitmanip_helper.c M target/riscv/helper.h M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a orc.b instruction (equivalent to the orc.b pseudo-instruction built on gorci from pre-0.93 draft-B) is available, mainly targeting string-processing workloads. This commit adds the new orc.b instruction and removed gorc/gorci. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210911140016.834071-12-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 7e68e6c79b9de5c923e478ea6794a5143610b765 https://github.com/qemu/qemu/commit/7e68e6c79b9de5c923e478ea6794a5143610b765 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/translate.c Log Message: ----------- target/riscv: Add a REQUIRE_32BIT macro With the changes to Zb[abcs], there's some encodings that are different in RV64 and RV32 (e.g., for rev8 and zext.h). For these, we'll need a helper macro allowing us to select on RV32, as well. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Bin Meng <bmeng...@gmail.com> Message-id: 20210911140016.834071-13-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: a1095bdcb050f0a17afb3fcb8a36543fb58f4ea9 https://github.com/qemu/qemu/commit/a1095bdcb050f0a17afb3fcb8a36543fb58f4ea9 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/bitmanip_helper.c M target/riscv/helper.h M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Add rev8 instruction, removing grev/grevi The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a rev8 instruction (equivalent to the rev8 pseudo-instruction built on grevi from pre-0.93 draft-B) is available. This commit adds the new rev8 instruction and removes grev/grevi. Note that there is no W-form of this instruction (both a sign-extending and zero-extending 32-bit version can easily be synthesized by following rev8 with either a srai or srli instruction on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are different. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210911140016.834071-14-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 06dfa8a5c5e79c2be7672b0a56e08c7f6d350148 https://github.com/qemu/qemu/commit/06dfa8a5c5e79c2be7672b0a56e08c7f6d350148 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc Log Message: ----------- target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which is handled through REQUIRE_32BIT. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210911140016.834071-15-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 9916ea3c97f6cbd46d912ecc80dfe94baed5d288 https://github.com/qemu/qemu/commit/9916ea3c97f6cbd46d912ecc80dfe94baed5d288 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/cpu.c M target/riscv/cpu.h M target/riscv/insn32.decode Log Message: ----------- target/riscv: Remove RVB (replaced by Zb[abcs]) With everything classified as Zb[abcs] and pre-0.93 draft-B instructions that are not part of Zb[abcs] removed, we can remove the remaining support code for RVB. Note that RVB has been retired for good and misa.B will neither mean 'some' or 'all of' Zb*: https://lists.riscv.org/g/tech-bitmanip/message/532 Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Bin Meng <bmeng...@gmail.com> Message-id: 20210911140016.834071-16-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 02c1b569a15b4b06a3c69b6cb1713830a29cb01f https://github.com/qemu/qemu/commit/02c1b569a15b4b06a3c69b6cb1713830a29cb01f Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M disas/riscv.c Log Message: ----------- disas/riscv: Add Zb[abcs] instructions With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> Acked-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210911140016.834071-17-philipp.toms...@vrull.eu Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: a88f0402391e9075df774affe5482d1286b9237e https://github.com/qemu/qemu/commit/a88f0402391e9075df774affe5482d1286b9237e Author: Frank Chang <frank.ch...@sifive.com> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M target/riscv/cpu.h M target/riscv/translate.c Log Message: ----------- target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect. Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty). However, it's possible that HS-level sstatus.FS is Clean and VS-level vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=1. We can't early return for this case because we still need to set sstatus.FS to Dirty according to spec. Signed-off-by: Frank Chang <frank.ch...@sifive.com> Reviewed-by: Vincent Chen <vincent.c...@sifive.com> Tested-by: Vincent Chen <vincent.c...@sifive.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210921020234.123448-1-frank.ch...@sifive.com Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 34229c46a721b2acf3cc1c1af3324f7468852330 https://github.com/qemu/qemu/commit/34229c46a721b2acf3cc1c1af3324f7468852330 Author: Bin Meng <bmeng...@gmail.com> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/char/ibex_uart.c Log Message: ----------- hw/char: ibex_uart: Register device in 'input' category The category of ibex_uart device is not set. Put it into the 'input' category. Signed-off-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210926105003.2716-1-bmeng...@gmail.com Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 5515ff162e8c20bfe907e21b2a3b9bed12a8ef67 https://github.com/qemu/qemu/commit/5515ff162e8c20bfe907e21b2a3b9bed12a8ef67 Author: Bin Meng <bmeng...@gmail.com> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/char/shakti_uart.c Log Message: ----------- hw/char: shakti_uart: Register device in 'input' category The category of shakti_uart device is not set. Put it into the 'input' category. Signed-off-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210926105003.2716-2-bmeng...@gmail.com Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 6a03349007f84e514e2e3def25c3f85400fdb47a https://github.com/qemu/qemu/commit/6a03349007f84e514e2e3def25c3f85400fdb47a Author: Bin Meng <bmeng...@gmail.com> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/char/sifive_uart.c Log Message: ----------- hw/char: sifive_uart: Register device in 'input' category The category of sifive_uart device is not set. Put it into the 'input' category. Signed-off-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210926105003.2716-3-bmeng...@gmail.com Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 284a66a8f6ffc8a720071b3f3cbc10cff0637337 https://github.com/qemu/qemu/commit/284a66a8f6ffc8a720071b3f3cbc10cff0637337 Author: Philippe Mathieu-Daudé <f4...@amsat.org> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/char/mchp_pfsoc_mmuart.c M include/hw/char/mchp_pfsoc_mmuart.h Log Message: ----------- hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the size occupied by all the registers. However all registers are 32-bit wide, and the MemoryRegionOps handlers are restricted to 32-bit: static const MemoryRegionOps mchp_pfsoc_mmuart_ops = { .read = mchp_pfsoc_mmuart_read, .write = mchp_pfsoc_mmuart_write, .impl = { .min_access_size = 4, .max_access_size = 4, }, Avoid being triskaidekaphobic, simplify by using the number of registers. Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Bin Meng <bin.m...@windriver.com> Tested-by: Bin Meng <bin.m...@windriver.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210925133407.1259392-2-f4...@amsat.org Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 24ce762df7d10175db1f91962d4fb1355b2645d2 https://github.com/qemu/qemu/commit/24ce762df7d10175db1f91962d4fb1355b2645d2 Author: Philippe Mathieu-Daudé <f4...@amsat.org> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/char/mchp_pfsoc_mmuart.c M include/hw/char/mchp_pfsoc_mmuart.h Log Message: ----------- hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container Our device have 2 different I/O regions: - a 16550 UART mapped for 32-bit accesses - 13 extra registers Instead of mapping each region on the main bus, introduce a container, map the 2 devices regions on the container, and map the container on the main bus. Before: (qemu) info mtree ... 0000000020100000-000000002010001f (prio 0, i/o): serial 0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020102000-000000002010201f (prio 0, i/o): serial 0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020104000-000000002010401f (prio 0, i/o): serial 0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart 0000000020106000-000000002010601f (prio 0, i/o): serial 0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart After: (qemu) info mtree ... 0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020100000-000000002010001f (prio 0, i/o): serial 0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs 0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020102000-000000002010201f (prio 0, i/o): serial 0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs 0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020104000-000000002010401f (prio 0, i/o): serial 0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs 0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart 0000000020106000-000000002010601f (prio 0, i/o): serial 0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Bin Meng <bin.m...@windriver.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Tested-by: Bin Meng <bin.m...@windriver.com> Message-id: 20210925133407.1259392-3-f4...@amsat.org Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 31ca70b5ff7c6ac600211f60e3ab024642fe5abb https://github.com/qemu/qemu/commit/31ca70b5ff7c6ac600211f60e3ab024642fe5abb Author: Philippe Mathieu-Daudé <f4...@amsat.org> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/char/mchp_pfsoc_mmuart.c M include/hw/char/mchp_pfsoc_mmuart.h Log Message: ----------- hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() - Add DeviceReset() method - Add vmstate structure for migration - Register device in 'input' category - Keep mchp_pfsoc_mmuart_create() behavior Note, serial_mm_init() calls qdev_set_legacy_instance_id(). This call is only needed for backwards-compatibility of incoming migration data with old versions of QEMU which implemented migration of devices with hand-rolled code. Since this device didn't previously handle migration at all, then it doesn't need to set the legacy instance ID. Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Bin Meng <bin.m...@windriver.com> Tested-by: Bin Meng <bin.m...@windriver.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210925133407.1259392-4-f4...@amsat.org Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: b7af62ae2ca4a5f36a36d98e37d59e96fb3f8ef5 https://github.com/qemu/qemu/commit/b7af62ae2ca4a5f36a36d98e37d59e96fb3f8ef5 Author: Bin Meng <bmeng...@gmail.com> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/dma/sifive_pdma.c Log Message: ----------- hw/dma: sifive_pdma: Fix Control.claim bit detection At present the codes detect whether the DMA channel is claimed by: claimed = !!s->chan[ch].control & CONTROL_CLAIM; As ! has higher precedence over & (bitwise and), this is essentially claimed = (!!s->chan[ch].control) & CONTROL_CLAIM; which is wrong, as any non-zero bit set in the control register will produce a result of a claimed channel. Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Control.claim is set") Signed-off-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Message-id: 20210927072124.1564129-1-bmeng...@gmail.com Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 47b5fbf5a3f9c88936a0532ecb918f5e58ad348c https://github.com/qemu/qemu/commit/47b5fbf5a3f9c88936a0532ecb918f5e58ad348c Author: Bin Meng <bmeng...@gmail.com> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/dma/sifive_pdma.c Log Message: ----------- hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed If Control.run bit is set while not preserving the Control.claim bit, the DMA transfer shall not be started. The following result is PDMA tested in U-Boot on Unleashed board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 => mw.l 0x3000000 0x1 <= Claim channel 0 => mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes) => mw.q 0x3000008 0x2 <= NextBytes = 2 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 55000000 00000002 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x2 <= Set channel 0 run bit only => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000000 55000000 00000002 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. Signed-off-by: Bin Meng <bmeng...@gmail.com> Acked-by: Alistair Francis <alistair.fran...@wdc.com> Message-id: 20210927072124.1564129-2-bmeng...@gmail.com Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Commit: 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07 https://github.com/qemu/qemu/commit/9ae6ecd848dcd1b32003526ab65a0d4c644dfb07 Author: Alistair Francis <alistair.fran...@wdc.com> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M hw/riscv/shakti_c.c Log Message: ----------- hw/riscv: shakti_c: Mark as not user creatable Mark the shakti_c machine as not user creatable. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639 Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Bin Meng <bmeng...@gmail.com> Tested-by: Philippe Mathieu-Daudé <f4...@amsat.org> Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.fran...@wdc.com> Commit: 3c019339830affe7974b738e0c2b71bd28778ef0 https://github.com/qemu/qemu/commit/3c019339830affe7974b738e0c2b71bd28778ef0 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2021-10-07 (Thu, 07 Oct 2021) Changed paths: M disas/riscv.c M hw/char/ibex_uart.c M hw/char/mchp_pfsoc_mmuart.c M hw/char/shakti_uart.c M hw/char/sifive_uart.c M hw/dma/sifive_pdma.c M hw/riscv/shakti_c.c M include/hw/char/mchp_pfsoc_mmuart.h M target/riscv/bitmanip_helper.c M target/riscv/cpu.c M target/riscv/cpu.h M target/riscv/helper.h M target/riscv/insn32.decode M target/riscv/insn_trans/trans_rvb.c.inc M target/riscv/translate.c Log Message: ----------- Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-20211007' into staging Third RISC-V PR for QEMU 6.2 - Add Zb[abcs] instruction support - Remove RVB support - Bug fix of setting mstatus_hs.[SD|FS] bits - Mark some UART devices as 'input' - QOMify PolarFire MMUART - Fixes for sifive PDMA - Mark shakti_c as not user creatable # gpg: Signature made Wed 06 Oct 2021 11:42:53 PM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alist...@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211007: (26 commits) hw/riscv: shakti_c: Mark as not user creatable hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed hw/dma: sifive_pdma: Fix Control.claim bit detection hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition hw/char: sifive_uart: Register device in 'input' category hw/char: shakti_uart: Register device in 'input' category hw/char: ibex_uart: Register device in 'input' category target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() disas/riscv: Add Zb[abcs] instructions target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Add a REQUIRE_32BIT macro target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Reassign instructions to the Zbb-extension target/riscv: Add instructions of the Zbc-extension target/riscv: Reassign instructions to the Zbs-extension target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) ... Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Compare: https://github.com/qemu/qemu/compare/ca61fa4b803e...3c019339830a