Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 5242ef887dd06659e3d516cb4000c8ed3277fb08
https://github.com/qemu/qemu/commit/5242ef887dd06659e3d516cb4000c8ed3277fb08
Author: Palmer Dabbelt <pal...@rivosinc.com>
Date: 2022-04-01 (Fri, 01 Apr 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Avoid leaking "no translation" TLB entries
The ISA doesn't allow bare mappings to be cached, as the caches are
translations and bare mppings are not translated. We cache these
translations in QEMU in order to utilize the TLB code, but that leaks
out to the guest.
Suggested-by: phan...@zju.edu.cn # no name in the From field
Fixes: 1e0d985fa9 ("target/riscv: Only flush TLB if SATP.ASID changes")
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-Id: <20220330165913.8836-1-pal...@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 8ff8ac63298611c8373b294ec936475b1a33f63f
https://github.com/qemu/qemu/commit/8ff8ac63298611c8373b294ec936475b1a33f63f
Author: Yueh-Ting (eop) Chen <eop.c...@sifive.com>
Date: 2022-04-01 (Fri, 01 Apr 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Add missing early exit condition for whole register
load/store
According to v-spec (section 7.9):
The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
regardless of current settings in vtype and vl. The usual property that no
elements are written if vstart ≥ vl does not apply to these instructions.
Instead, no elements are written if vstart ≥ evl.
Signed-off-by: eop Chen <eop.c...@sifive.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-Id: <164762720573.18409.393193122799748352...@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 697d18b1bd2667efa418cc7d7248d5450da547e7
https://github.com/qemu/qemu/commit/697d18b1bd2667efa418cc7d7248d5450da547e7
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2022-04-01 (Fri, 01 Apr 2022)
Changed paths:
M target/riscv/csr.c
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20220401' of github.com:alistair23/qemu into
staging
Sixth RISC-V PR for QEMU 7.0
This is a last minute RISC-V PR for 7.0.
It includes a fix to avoid leaking no translation TLB entries. This
incorrectly cached uncachable baremetal entries. This would break Linux
boot while single stepping. As the fix is pretty straight forward (flush
the cache more often) it's being pulled in for 7.0.
At the same time I have included a RISC-V vector extension fixup patch.
# gpg: Signature made Fri 01 Apr 2022 00:33:58 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alist...@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220401' of github.com:alistair23/qemu:
target/riscv: rvv: Add missing early exit condition for whole register
load/store
target/riscv: Avoid leaking "no translation" TLB entries
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/9b617b1bb405...697d18b1bd26
