Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 5dd0be53e89acfc367944489a364b0ec835dee9a
https://github.com/qemu/qemu/commit/5dd0be53e89acfc367944489a364b0ec835dee9a
Author: Joel Stanley <j...@jms.id.au>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M pc-bios/skiboot.lid
M roms/skiboot
Log Message:
-----------
ppc/pnv: Update skiboot to v7.0
This is skiboot 7.0 (commit 76b349cf7b40). Built using gcc 11.2.0 and
binutils 2.38.
Changes since the previous version:
Christophe Lombard (15):
npu2: move opal api
pau: introduce support
rainier: detect pau devices
pau: assign bars
pau: create phb
pau: enabling opencapi
pau: translation layer configuration
pau: enable interrupt on error
pau: complete phb ops
pau: hmi scom dump
pau: phy init
pau: link training
pau: update current opal call functions
pau: mmio invalidates
pau: Add support for OpenCAPI Persistent Memory devices.
Cédric Le Goater (4):
xive/p10: Fix xive_special_cache_check when DEBUG=1
xive/p10: Fix mismatch errors when DEBUG=1
interrupts: Do not advertise XICS support on P10
skiboot v6.6.6 release notes
Frederic Barrat (6):
phb4/5: Escalate page-level TCE kills
npu3: Remove GPU support on Swift
phb5: Remove obsolete capp-related properties
xive/p10:: Declare xive2 DT node as an interrupt-controller
skiboot v6.0.24 release notes
opal-api: Drop diagnostics data type symbol for PHB5
Michael Ellerman (3):
external/mambo: Print more info when the kernel is too big
doc: Make it clear all existing platforms use Power9N
docs: Add Swift, Mowgli & Rainier
Nicholas Piggin (12):
external/mambo: Updates for POWER10 configuration for DD2.0
external/mambo: Updates POWER9 SIM_CTRL1 to remove hardware atomic RC
external/mambo: Add POWER10 small-core mode
HBRT: fix clobbered r16 when host services handlers are called
interrupts: add_opal_interrupts avoid NULL dereference on P10 mambo
cpu: cpu_idle_job SMT priority fix
cpu: add debug check in cpu_relax
asm/head: Fix P10 HILE for little endian build
phb4: annotate tbl_pest with endian types
Remove support for POWER8 DD1
phb3: make endian-clean
flash: AST BMC endian fixes
Nick Child (1):
secvar: Free md context on hash error
Ryan Grimm (1):
AWAN simulator support for P10
Vasant Hegde (5):
ci: Bump qemu version
hello_world: Add p10 mambo tests
skiboot v6.7.3 release notes
skiboot v6.8.1 release notes
skiboot v7.0 release notes
Signed-off-by: Joel Stanley <j...@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 4c7daca302a4f4d0f66f1112e094307863c4f6c8
https://github.com/qemu/qemu/commit/4c7daca302a4f4d0f66f1112e094307863c4f6c8
Author: Alexey Kardashevskiy <a...@ozlabs.ru>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/spapr_rtas_ddw.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr/ddw: Add 2M pagesize
Recently the LoPAPR spec got a new 2MB pagesize to support in Dynamic DMA
Windows API (DDW), this adds the new flag.
Linux supports it since
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=38727311871
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru>
Message-Id: <20220321071945.918669-1-...@ozlabs.ru>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 58858759c198dc56498095e387a31178d0d852b9
https://github.com/qemu/qemu/commit/58858759c198dc56498095e387a31178d0d852b9
Author: Cédric Le Goater <c...@kaod.org>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/pnv_psi.c
M include/hw/ppc/pnv_psi.h
Log Message:
-----------
ppc/pnv: Fix PSI IRQ definition
On HW, the PSI and FSP interrupt levels are muxed under the same
interrupt number. For coding reasons, an extra IRQ number was
introduced to index register values in an array. It increased the
count of IRQs which do not fit in the PSI IRQ range anymore.
The PSI and FSP interrupts should be modeled with an extra level of
GPIO lines but since QEMU does not support them, simply drop the extra
number to stay within the IRQ range.
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
Message-Id: <20220323072846.1780212-2-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: c05aa1406b376a71ba8071f4b959750721086371
https://github.com/qemu/qemu/commit/c05aa1406b376a71ba8071f4b959750721086371
Author: Cédric Le Goater <c...@kaod.org>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
M hw/ppc/pnv_psi.c
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: Remove PnvLpcController::psi link
Create an anonymous output GPIO line to connect the LPC device with
the PSIHB device and raise the appropriate PSI IRQ line depending on
the processor model.
A temporary __pnv_psi_irq_set() routine is introduced to handle the
transition. It will be removed when all devices raising PSI interrupts
are converted to use GPIOs.
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
Message-Id: <20220323072846.1780212-3-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: b0ae5c69e1609852623186a2508faf3f7990d72e
https://github.com/qemu/qemu/commit/b0ae5c69e1609852623186a2508faf3f7990d72e
Author: Cédric Le Goater <c...@kaod.org>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_occ.c
M include/hw/ppc/pnv_occ.h
Log Message:
-----------
ppc/pnv: Remove PnvOCC::psi link
Use an anonymous output GPIO line to connect the OCC device with the
PSIHB device and raise the appropriate PSI IRQ line depending on the
processor model.
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
Message-Id: <20220323072846.1780212-4-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: dcf4ca45140c04d24f7e193e80f1780910d4ea09
https://github.com/qemu/qemu/commit/dcf4ca45140c04d24f7e193e80f1780910d4ea09
Author: Cédric Le Goater <c...@kaod.org>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/pnv_psi.c
M include/hw/ppc/pnv_psi.h
Log Message:
-----------
ppc/pnv: Remove PnvPsiClas::irq_set
All devices raising PSI interrupts are now converted to use GPIO lines
and the pnv_psi_irq_set() routines have become useless. Drop them.
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
Message-Id: <20220323072846.1780212-5-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 354ff1557ad8a448330a870cf0166c4a7bb5eb36
https://github.com/qemu/qemu/commit/354ff1557ad8a448330a870cf0166c4a7bb5eb36
Author: Cédric Le Goater <c...@kaod.org>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/pnv_psi.c
Log Message:
-----------
ppc/pnv: Remove useless checks in set_irq handlers
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
Message-Id: <20220323072846.1780212-6-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 0939ac2cd9c0ad02dbfa65fb528c0c69431d01b5
https://github.com/qemu/qemu/commit/0939ac2cd9c0ad02dbfa65fb528c0c69431d01b5
Author: Fabiano Rosas <faro...@linux.ibm.com>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr: Move hypercall_register_softmmu
I'm moving this because next patch will add more code under the ifdef
and it will be cleaner if we keep them together.
Also switch the ifdef branches to make it more convenient to add code
under CONFIG_TCG in the next patch.
Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Message-Id: <20220325221113.255834-2-faro...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 365acf15d36345bd3b3df1f1f5dba76156c95dc7
https://github.com/qemu/qemu/commit/365acf15d36345bd3b3df1f1f5dba76156c95dc7
Author: Fabiano Rosas <faro...@linux.ibm.com>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr: Move nested KVM hypercalls under a TCG only config.
These are the spapr virtual hypervisor implementation of the nested
KVM API. They only make sense when running with TCG.
Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Message-Id: <20220325221113.255834-3-faro...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: f290a23868ee80c0cb8d27659e0c3b2a91437fbc
https://github.com/qemu/qemu/commit/f290a23868ee80c0cb8d27659e0c3b2a91437fbc
Author: Fabiano Rosas <faro...@linux.ibm.com>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M target/ppc/kvm.c
M target/ppc/trace-events
Log Message:
-----------
target/ppc: Improve KVM hypercall trace
Before:
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
kvm_handle_papr_hcall handle PAPR hypercall
After:
kvm_handle_papr_hcall 0x3a8
kvm_handle_papr_hcall 0x3ac
kvm_handle_papr_hcall 0x108
kvm_handle_papr_hcall 0x104
kvm_handle_papr_hcall 0x104
kvm_handle_papr_hcall 0x108
Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Message-Id: <20220325223316.276494-1-faro...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 613cf0fcbabee5ec34cab85a933eb3d46845a7cb
https://github.com/qemu/qemu/commit/613cf0fcbabee5ec34cab85a933eb3d46845a7cb
Author: Matheus Ferst <matheus.fe...@eldorado.org.br>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M include/qemu/int128.h
M tests/unit/test-int128.c
Log Message:
-----------
qemu/int128: add int128_urshift
Implement an unsigned right shift for Int128 values and add the same
tests cases of int128_rshift in the unit test.
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20220330175932.6995-3-matheus.fe...@eldorado.org.br>
[danielhb: fixed long lines in test_urshift()]
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: f279852b89bd42289c421714221c860e71fb4639
https://github.com/qemu/qemu/commit/f279852b89bd42289c421714221c860e71fb4639
Author: Matheus Ferst <matheus.fe...@eldorado.org.br>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: add uint128_to_float128
Based on parts_uint_to_float, implements uint128_to_float128 to convert
an unsigned 128-bit value received through an Int128 argument.
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20220330175932.6995-4-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 95c1b71e25a9bafb64e4dd69f8834716332a7542
https://github.com/qemu/qemu/commit/95c1b71e25a9bafb64e4dd69f8834716332a7542
Author: Matheus Ferst <matheus.fe...@eldorado.org.br>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: add int128_to_float128
Based on parts_sint_to_float, implements int128_to_float128 to convert a
signed 128-bit value received through an Int128 argument.
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
Message-Id: <20220330175932.6995-5-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 4de49ddfacd8154eba5f2de897c732175d80af5f
https://github.com/qemu/qemu/commit/4de49ddfacd8154eba5f2de897c732175d80af5f
Author: Matheus Ferst <matheus.fe...@eldorado.org.br>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: add float128_to_uint128
Implements float128_to_uint128 based on parts_float_to_uint logic.
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20220330175932.6995-6-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: bea592300b387fa62fda59878886eb84fe373374
https://github.com/qemu/qemu/commit/bea592300b387fa62fda59878886eb84fe373374
Author: Matheus Ferst <matheus.fe...@eldorado.org.br>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
M include/qemu/int128.h
Log Message:
-----------
softfloat: add float128_to_int128
Implements float128_to_int128 based on parts_float_to_int logic.
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20220330175932.6995-7-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 67332e07187bee210e9c7d03b2b4c6f6ab79c2a4
https://github.com/qemu/qemu/commit/67332e07187bee210e9c7d03b2b4c6f6ab79c2a4
Author: Matheus Ferst <matheus.fe...@eldorado.org.br>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: implement xscv[su]qqp
Implement the following PowerISA v3.1 instructions:
xscvsqqp: VSX Scalar Convert with round Signed Quadword to
Quad-Precision
xscvuqqp: VSX Scalar Convert with round Unsigned Quadword to
Quad-Precision format
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20220330175932.6995-8-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: b3d4520585eb445affc4f46b979a3970d99e87d8
https://github.com/qemu/qemu/commit/b3d4520585eb445affc4f46b979a3970d99e87d8
Author: Matheus Ferst <matheus.fe...@eldorado.org.br>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: implement xscvqp[su]qz
Implement the following PowerISA v3.1 instructions:
xscvqpsqz: VSX Scalar Convert with round to zero Quad-Precision to
Signed Quadword
xscvqpuqz: VSX Scalar Convert with round to zero Quad-Precision to
Unsigned Quadword
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20220330175932.6995-9-matheus.fe...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: b8ff425b1d384ffb9662a4e9a0380e2861d1479a
https://github.com/qemu/qemu/commit/b8ff425b1d384ffb9662a4e9a0380e2861d1479a
Author: Bernhard Beschow <shen...@gmail.com>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
hw/ppc/ppc405_boards: Initialize g_autofree pointer
Resolves the only compiler warning when building a full QEMU under Arch Linux:
Compiling C object libqemu-ppc-softmmu.fa.p/hw_ppc_ppc405_boards.c.o
In file included from /usr/include/glib-2.0/glib.h:114,
from qemu/include/glib-compat.h:32,
from qemu/include/qemu/osdep.h:132,
from ../src/hw/ppc/ppc405_boards.c:25:
../src/hw/ppc/ppc405_boards.c: In function ‘ref405ep_init’:
/usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: warning: ‘filename’ may
be used uninitialized in this function [-Wmaybe-uninitialized]
28 | g_free (*pp);
| ^~~~~~~~~~~~
../src/hw/ppc/ppc405_boards.c:265:26: note: ‘filename’ was declared here
265 | g_autofree char *filename;
| ^~~~~~~~
Signed-off-by: Bernhard Beschow <shen...@gmail.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-Id: <20220405123534.3395-1-shen...@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 23bd5fc3ed1a681eb4f1e1308bb2869fb7ca050f
https://github.com/qemu/qemu/commit/23bd5fc3ed1a681eb4f1e1308bb2869fb7ca050f
Author: Alexey Kardashevskiy <a...@ozlabs.ru>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/vof.c
Log Message:
-----------
ppc/vof: Fix uninitialized string tracing
There are error paths which do not initialize propname but the trace_exit
label prints it anyway. This initializes the problem string.
Spotted by Coverity CID 1487241.
Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru>
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Message-Id: <20220406045013.3610172-1-...@ozlabs.ru>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 2e8656710a3ac6e79d54b18df9f74b30753448cd
https://github.com/qemu/qemu/commit/2e8656710a3ac6e79d54b18df9f74b30753448cd
Author: Frederic Barrat <fbar...@linux.ibm.com>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/pci/pcie.c
M hw/pci/pcie_aer.c
Log Message:
-----------
pcie: Don't try triggering a LSI when not defined
This patch skips [de]asserting a LSI interrupt if the device doesn't
have any LSI defined. Doing so would trigger an assert in
pci_irq_handler().
The PCIE root port implementation in qemu requests a LSI (INTA), but a
subclass may want to change that behavior since it's a valid
configuration. For example on the POWER8/POWER9/POWER10 systems, the
root bridge doesn't request any LSI.
Signed-off-by: Frederic Barrat <fbar...@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Reviewed-by: Michael S. Tsirkin <m...@redhat.com>
Message-Id: <20220408131303.147840-2-fbar...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: b34ce592fd3133509793e38adf73c27841aba756
https://github.com/qemu/qemu/commit/b34ce592fd3133509793e38adf73c27841aba756
Author: Frederic Barrat <fbar...@linux.ibm.com>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
ppc/pnv: Remove LSI on the PCIE host bridge
The phb3/phb4/phb5 root ports inherit from the default PCIE root port
implementation, which requests a LSI interrupt (#INTA). On real
hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch
corrects it so that it matches the hardware.
As a consequence, the device tree previously generated was bogus, as
the root bridge LSI was not properly mapped. On some
implementation (powernv9), it was leading to inconsistent interrupt
controller (xive) data. With this patch, it is now clean.
Signed-off-by: Frederic Barrat <fbar...@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Message-Id: <20220408131303.147840-3-fbar...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 4e610064dbcb2425de03cfd541a6393280c463c9
https://github.com/qemu/qemu/commit/4e610064dbcb2425de03cfd541a6393280c463c9
Author: Frederic Barrat <fbar...@linux.ibm.com>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Add two missing register callbacks on POWER10
This patch adds tcg accessors for 2 SPRs which were missing on P10:
- the TBU40 register is used to write the upper 40 bits of the
timebase register. It is used by kvm to update the timebase when
entering/exiting the guest on P9 and above. The missing definition was
causing erratic decrementer interrupts in a pseries/kvm guest running
in a powernv10/tcg host, typically resulting in hangs.
- the missing DPDES SPR was found through code inspection. It exists
unchanged on P10.
Both existed on previous versions of the processor and a bit of git
archaeology hints that they were added while the P10 model was already
being worked on so they may have simply fallen through the cracks.
Signed-off-by: Frederic Barrat <fbar...@linux.ibm.com>
Reviewed-by: Fabiano Rosas <faro...@linux.ibm.com>
Message-Id: <20220411125900.352028-1-fbar...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: 2d94af4b16c40758eee3a8591307ae173090d4ad
https://github.com/qemu/qemu/commit/2d94af4b16c40758eee3a8591307ae173090d4ad
Author: Guo Zhi <qtxuning1...@sjtu.edu.cn>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M hw/ppc/ppc440_bamboo.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/ppc.h
Log Message:
-----------
hw/ppc: change indentation to spaces from TABs
There are still some files in the QEMU PPC code base that use TABs for
indentation instead of using spaces. The TABs should be replaced so
that we have a consistent coding style.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/374
Signed-off-by: Guo Zhi <qtxuning1...@sjtu.edu.cn>
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Message-Id: <20220412021240.2080218-1-qtxuning1...@sjtu.edu.cn>
[danielhb: trimmed commit msg to 72 chars per line]
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Commit: b1efff6bf031a93b5b8bf3912ddc720cc1653a61
https://github.com/qemu/qemu/commit/b1efff6bf031a93b5b8bf3912ddc720cc1653a61
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2022-04-20 (Wed, 20 Apr 2022)
Changed paths:
M fpu/softfloat.c
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
M hw/pci/pcie.c
M hw/pci/pcie_aer.c
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
M hw/ppc/pnv_occ.c
M hw/ppc/pnv_psi.c
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_rtas.c
M hw/ppc/spapr_rtas_ddw.c
M hw/ppc/vof.c
M include/fpu/softfloat.h
M include/hw/ppc/pnv_lpc.h
M include/hw/ppc/pnv_occ.h
M include/hw/ppc/pnv_psi.h
M include/hw/ppc/ppc.h
M include/hw/ppc/spapr.h
M include/qemu/int128.h
M pc-bios/skiboot.lid
M roms/skiboot
M target/ppc/cpu_init.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/kvm.c
M target/ppc/trace-events
M target/ppc/translate/vsx-impl.c.inc
M tests/unit/test-int128.c
Log Message:
-----------
Merge tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu into
staging
ppc patch queue for 2022-04-20
First batch of ppc patches for QEMU 7.1:
- skiboot firmware version bump
- pseries: add 2M DDW pagesize
- pseries: make virtual hypervisor code TCG only
- powernv: introduce GPIO lines for PSIHB device
- powernv: remove PCIE root bridge LSI
- target/ppc: alternative softfloat 128 bit integer support
- assorted fixes
# -----BEGIN PGP SIGNATURE-----
#
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# ZE10AP4wPeJQ3fxXb5ylVtL4qkJaLWy6VrJBQSKSb5YEA0fhegEA9ZufpnENQePU
# gZF0eFAQK/DbSnDyvRQVpGcJM0K1UgI=
# =nVRw
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 20 Apr 2022 02:48:14 PM PDT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Can't check signature: No public key
* tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu: (23 commits)
hw/ppc: change indentation to spaces from TABs
target/ppc: Add two missing register callbacks on POWER10
ppc/pnv: Remove LSI on the PCIE host bridge
pcie: Don't try triggering a LSI when not defined
ppc/vof: Fix uninitialized string tracing
hw/ppc/ppc405_boards: Initialize g_autofree pointer
target/ppc: implement xscvqp[su]qz
target/ppc: implement xscv[su]qqp
softfloat: add float128_to_int128
softfloat: add float128_to_uint128
softfloat: add int128_to_float128
softfloat: add uint128_to_float128
qemu/int128: add int128_urshift
target/ppc: Improve KVM hypercall trace
spapr: Move nested KVM hypercalls under a TCG only config.
spapr: Move hypercall_register_softmmu
ppc/pnv: Remove useless checks in set_irq handlers
ppc/pnv: Remove PnvPsiClas::irq_set
ppc/pnv: Remove PnvOCC::psi link
ppc/pnv: Remove PnvLpcController::psi link
...
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/9c125d17e940...b1efff6bf031
