Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 838f717b22fb942f488f2bf5d1cd943736c8eae5
https://github.com/qemu/qemu/commit/838f717b22fb942f488f2bf5d1cd943736c8eae5
Author: Bin Meng <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M hw/riscv/boot.c
Log Message:
-----------
hw/riscv: Update comment for qtest check in riscv_find_firmware()
Since commit 4211fc553234 ("roms/opensbi: Remove ELF images"), the
comment for qtest check in riscv_find_firmware() is out of date.
Update it to reflect the latest status.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-Id:
<bn7pr08mb435525c92550bac5467be672bf...@bn7pr08mb4355.namprd08.prod.outlook.com>
Signed-off-by: Alistair Francis <[email protected]>
Commit: ff3809ef34d39a2b42f0ced5f5f90c36bd550cc9
https://github.com/qemu/qemu/commit/ff3809ef34d39a2b42f0ced5f5f90c36bd550cc9
Author: Wilfred Mallawa <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M hw/ssi/ibex_spi_host.c
Log Message:
-----------
hw/ssi: ibex_spi: fixup coverity issue
This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.
[1] https://www.mail-archive.com/[email protected]/msg887713.html
Fixes: Coverity CID 1488107
Signed-off-by: Wilfred Mallawa <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6c1876958bbb53396655777401ab34207d0e1afa
https://github.com/qemu/qemu/commit/6c1876958bbb53396655777401ab34207d0e1afa
Author: Wilfred Mallawa <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M hw/ssi/ibex_spi_host.c
M include/hw/ssi/ibex_spi_host.h
Log Message:
-----------
hw/ssi: ibex_spi: fixup/add rw1c functionality
This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.
Signed-off-by: Wilfred Mallawa <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 785a7383dd4832cc772a2c5483bd6fa40ee51302
https://github.com/qemu/qemu/commit/785a7383dd4832cc772a2c5483bd6fa40ee51302
Author: Sunil V L <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M hw/arm/boot.c
M hw/loongarch/virt.c
M hw/nvram/fw_cfg.c
M include/hw/nvram/fw_cfg.h
Log Message:
-----------
hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same
function will be required by riscv too. So, it's time to refactor and
move this function to a common path.
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 90e26984eede1f4303572a39ee328f4c23b276a0
https://github.com/qemu/qemu/commit/90e26984eede1f4303572a39ee328f4c23b276a0
Author: Sunil V L <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
To enable both -kernel and -pflash options, the fw_cfg needs to be
created prior to loading the kernel.
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: a5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0
https://github.com/qemu/qemu/commit/a5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0
Author: Sunil V L <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: virt: Enable booting S-mode firmware from pflash
To boot S-mode firmware payload like EDK2 from persistent
flash storage, qemu needs to pass the flash address as the
next_addr in fw_dynamic_info to the opensbi.
When both -kernel and -pflash options are provided in command line,
the kernel (and initrd if -initrd) will be copied to fw_cfg table.
The S-mode FW will load the kernel/initrd from fw_cfg table.
If only pflash is given but not -kernel, then it is the job of
of the S-mode firmware to locate and load the kernel.
In either case, update the kernel_entry with the flash address
so that the opensbi can jump to the entry point of the S-mode
firmware.
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 07f4964d1785e9c230282074a5aef1eb7368d378
https://github.com/qemu/qemu/commit/07f4964d1785e9c230282074a5aef1eb7368d378
Author: Yang Liu <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: rvv: Add disas support for vector instructions
Tested with https://github.com/ksco/rvv-decoder-tests
Expected checkpatch errors for consistency and brevity reasons:
ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: braces {} are necessary for all arms of this statement
Signed-off-by: Yang Liu <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 55144a1fd0d1f37b49ea051291decbbe427b7714
https://github.com/qemu/qemu/commit/55144a1fd0d1f37b49ea051291decbbe427b7714
Author: Jim Shu <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: fix hard-coded max priority level
The maximum priority level is hard-coded when writing to interrupt
priority register. However, when writing to priority threshold register,
the maximum priority level is from num_priorities Property which is
configured by platform.
Also change interrupt priority register to use num_priorities Property
in maximum priority level.
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Jim Shu <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 1aae4a12dab4bf1adc249c2ac6178d15e4b5a77d
https://github.com/qemu/qemu/commit/1aae4a12dab4bf1adc249c2ac6178d15e4b5a77d
Author: Jim Shu <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: change interrupt priority register to WARL field
PLIC spec [1] requires interrupt source priority registers are WARL
field and the number of supported priority is power-of-2 to simplify SW
discovery.
Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC
spec, whose number of supported priority is not power-of-2. Just change
each bit of interrupt priority register to WARL field when the number of
supported priority is power-of-2.
[1]
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
Signed-off-by: Jim Shu <[email protected]>
Reviewed-by: Clément Chigot <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 47566421f029b0a489b63f8195b3ff944e017056
https://github.com/qemu/qemu/commit/47566421f029b0a489b63f8195b3ff944e017056
Author: Alistair Francis <[email protected]>
Date: 2022-10-14 (Fri, 14 Oct 2022)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: pmp: Fixup TLB size calculation
Since commit 4047368938f6 "accel/tcg: Introduce tlb_set_page_full" we
have been seeing this assert
../accel/tcg/cputlb.c:1294: tlb_set_page_with_attrs: Assertion
`is_power_of_2(size)' failed.
When running Tock on the OpenTitan machine.
The issue is that pmp_get_tlb_size() would return a TLB size that wasn't
a power of 2. The size was also smaller then TARGET_PAGE_SIZE.
This patch ensures that any TLB size less then TARGET_PAGE_SIZE is
rounded down to 1 to ensure it's a valid size.
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: LIU Zhiwei<[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Message-Id: <[email protected]>
Commit: 5c2439a92ce4a1c5a53070bd803d6f7647e702ca
https://github.com/qemu/qemu/commit/5c2439a92ce4a1c5a53070bd803d6f7647e702ca
Author: Stefan Hajnoczi <[email protected]>
Date: 2022-10-16 (Sun, 16 Oct 2022)
Changed paths:
M disas/riscv.c
M hw/arm/boot.c
M hw/intc/sifive_plic.c
M hw/loongarch/virt.c
M hw/nvram/fw_cfg.c
M hw/riscv/boot.c
M hw/riscv/virt.c
M hw/ssi/ibex_spi_host.c
M include/hw/nvram/fw_cfg.h
M include/hw/riscv/boot.h
M include/hw/ssi/ibex_spi_host.h
M target/riscv/pmp.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20221014' of
https://github.com/alistair23/qemu into staging
Third RISC-V PR for QEMU 7.2
* Update qtest comment
* Fix coverity issue with Ibex SPI
* Move load_image_to_fw_cfg() to common location
* Enable booting S-mode firmware from pflash on virt machine
* Add disas support for vector instructions
* Priority level fixes for PLIC
* Fixup TLB size calculation when using PMP
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# gpg: Signature made Fri 14 Oct 2022 03:51:59 EDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <[email protected]>" [unknown]
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# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20221014' of https://github.com/alistair23/qemu:
target/riscv: pmp: Fixup TLB size calculation
hw/intc: sifive_plic: change interrupt priority register to WARL field
hw/intc: sifive_plic: fix hard-coded max priority level
disas/riscv.c: rvv: Add disas support for vector instructions
hw/riscv: virt: Enable booting S-mode firmware from pflash
hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
hw/ssi: ibex_spi: fixup/add rw1c functionality
hw/ssi: ibex_spi: fixup coverity issue
hw/riscv: Update comment for qtest check in riscv_find_firmware()
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/2ba341b3694c...5c2439a92ce4
