Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 62c5bc348e39f8b715fb2eac414749ee7e630043
https://github.com/qemu/qemu/commit/62c5bc348e39f8b715fb2eac414749ee7e630043
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()
Next patch will move all calls to riscv_load_initrd() to
riscv_load_kernel(). Machines that want to load initrd will be able to
do via an extra flag to riscv_load_kernel().
This change will expose a sign-extend behavior that is happening in
load_elf_ram_sym() when running 32 bit guests [1]. This is currently
obscured by the fact that riscv_load_initrd() is using the return of
riscv_load_kernel(), defined as target_ulong, and this return type will
crop the higher 32 bits that would be padded with 1s by the sign
extension when running in 32 bit targets. The changes to be done will
force riscv_load_initrd() to use an uint64_t instead, exposing it to the
padding when dealing with 32 bit CPUs.
There is a discussion about whether load_elf_ram_sym() should or should
not sign extend the value returned by 'lowaddr'. What we can do is to
prevent the behavior change that the next patch will end up doing.
riscv_load_initrd() wasn't dealing with 64 bit kernel entries when
running 32 bit CPUs, and we want to keep it that way.
One way of doing it is to use target_ulong in 'kernel_entry' in
riscv_load_kernel() and rely on the fact that this var will not be sign
extended for 32 bit targets. Another way is to explictly clear the
higher 32 bits when running 32 bit CPUs for all possibilities of
kernel_entry.
We opted for the later. This will allow us to be clear about the design
choices made in the function, while also allowing us to add a small
comment about what load_elf_ram_sym() is doing. With this change, the
consolation patch can do its job without worrying about unintended
behavioral changes.
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-Id: <20230206140022.2748401-2-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Commit: 487d73fc470d233f2d5da9cec7cd229ae8b88b49
https://github.com/qemu/qemu/commit/487d73fc470d233f2d5da9cec7cd229ae8b88b49
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline
Let's fold everything inside riscv_load_kernel() to avoid code
repetition. To not change the behavior of boards that aren't calling
riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and
allow these boards to opt out from initrd loading.
Cc: Palmer Dabbelt <pal...@dabbelt.com>
Reviewed-by: Bin Meng <bm...@tinylab.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-Id: <20230206140022.2748401-3-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Commit: 8b64475bd529ffe42f89b6c2f819e5133c9f8317
https://github.com/qemu/qemu/commit/8b64475bd529ffe42f89b6c2f819e5133c9f8317
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2023-02-16 (Thu, 16 Feb 2023)
Changed paths:
M hw/riscv/boot.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv/boot.c: make riscv_load_initrd() static
The only remaining caller is riscv_load_kernel_and_initrd() which
belongs to the same file.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Bin Meng <bm...@tinylab.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-Id: <20230206140022.2748401-4-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Commit: 0e660142ca085284c31b8418104b22b18d33bc22
https://github.com/qemu/qemu/commit/0e660142ca085284c31b8418104b22b18d33bc22
Author: Frank Chang <frank.ch...@sifive.com>
Date: 2023-02-23 (Thu, 23 Feb 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Remove privileged spec version restriction for RVV
The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level.
This commit removes the restriction from both RVV CSRs and extension CPU
ISA string.
Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Bin Meng <bm...@tinylab.org>
Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-Id: <20230208063209.27279-1-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Commit: a3ae8d46c04364148a6ea814140dff3b9b29ba1b
https://github.com/qemu/qemu/commit/a3ae8d46c04364148a6ea814140dff3b9b29ba1b
Author: Alistair Francis <alistair.fran...@wdc.com>
Date: 2023-02-23 (Thu, 23 Feb 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add some RISC-V reviewers
This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Acked-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Acked-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
Message-Id: <20230209003308.738237-1-alistair.fran...@opensource.wdc.com>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Commit: 90b1fafce0602d46243a40d8eea3006ef57e24d8
https://github.com/qemu/qemu/commit/90b1fafce0602d46243a40d8eea3006ef57e24d8
Author: Himanshu Chauhan <hchau...@ventanamicro.com>
Date: 2023-02-23 (Thu, 23 Feb 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Smepmp: Skip applying default rules when address matches
When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied. This should only be the case when there
is no matching address is found.
This patch skips applying default rules when matching address range
is found. It returns the index of the match PMP entry.
Fixes: 824cac681c3 (target/riscv: Fix PMP propagation for tlb)
Signed-off-by: Himanshu Chauhan <hchau...@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-Id: <20230209055206.229392-1-hchau...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Commit: 718942aed69d42f0d982824b2469331ff77edcb2
https://github.com/qemu/qemu/commit/718942aed69d42f0d982824b2469331ff77edcb2
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2023-02-23 (Thu, 23 Feb 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
We have a RISCVCPU *cpu pointer available at the start of the function.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Message-ID: <20230210123836.506286-1-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Commit: 8c89d50c10afdd98da82642ca5e9d7af4f1c18bd
https://github.com/qemu/qemu/commit/8c89d50c10afdd98da82642ca5e9d7af4f1c18bd
Author: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Date: 2023-02-23 (Thu, 23 Feb 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix vslide1up.vf and vslide1down.vf
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
scalar input should be uint64_t to hold the 64 bits float register.And the
same for vslide1down_##BITWIDTH.
This bug is caught when run these instructions on qemu-riscv32.
Signed-off-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
Message-ID: <20230213094550.29621-1-zhiwei_...@linux.alibaba.com>
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
Commit: b11728dc3ae67ddedf34b7a4f318170e7092803c
https://github.com/qemu/qemu/commit/b11728dc3ae67ddedf34b7a4f318170e7092803c
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2023-02-26 (Sun, 26 Feb 2023)
Changed paths:
M MAINTAINERS
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
M target/riscv/cpu.c
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/pmp.c
M target/riscv/vector_helper.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu
into staging
Fourth RISC-V PR for QEMU 8.0, Attempt 2
* A triplet of cleanups to the kernel/initrd loader that avoids
duplication between the various boards.
* Weiwei Li, Daniel Henrique Barboza, and Liu Zhiwei have been added as
reviewers. Thanks for the help!
* A fix for PMP matching to avoid incorrectly appling the default
permissions on PMP permission violations.
* A cleanup to avoid an unnecessary avoid env_archcpu() in
cpu_get_tb_cpu_state().
* Fixes for the vector slide instructions to avoid truncating 64-bit
values (such as doubles) on 32-bit targets.
# -----BEGIN PGP SIGNATURE-----
#
# iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmP5Br8THHBhbG1lckBk
# YWJiZWx0LmNvbQAKCRAuExnzX7sYiT4RD/9hdSlQlR1g/2h4fbCJ3U0GvyNH0T7N
# mt3AX8hFvmfR1O63qqVVebJSHM1dTm6WsA19vKE5tdtbjV5V8UZuBTSqYeRBSrLd
# LK9IHhwv3k9OQ/EG8CgRo7HEMxAurpC26zTf3chnfwa1Wyl5XxCXNx5hPbhu18G9
# oxw0sBi51T0Tb+N6lOVVSfmiEZWLXRq+lDCZdV0j864brsSjo4x8VEGrLaFTOJLf
# X4MW6vBI4Pcb7EGnHjj5WvRKsf8gdahdx8bSTjORIm8oGri9Iyw6Vrg2khuhjnuH
# 99sD1O06cvrylp+sCOVei8H3S6/xCepQXUXnCBCd1/cetgV+olo+ZR78Z8ZjXPED
# jhZ23lsDcge+4W141lsCiwLgzI0YO3Ac+84zQLIvcx16c8zow3G9FO9sTlBSsgnW
# 0XJrsUF7AZB6quUSMytG7WK+OBizzCRwj7ItC+Mty68wLrei5lDVj8b0t8hAQEdr
# dOb7jku+Dz8OspGZx1aDKKifGDO+Ppv4PjAM2G44OmkM824SvvFg8+FEr9NgbKbp
# VgTZDCeVC6IEpzthKsK8WeompLo7Sc33KITqwMbGiyGs+gsnmgKP2bcTLF8YTlFk
# dqFBWjo3tjH5oukgTLCSYY4xPaHR9q418vGAfRox15GtUVliQ9iL5oH47PVXg4U7
# YsNZ74nD1pUueg==
# =Umli
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 24 Feb 2023 18:49:35 GMT
# gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg: issuer "pal...@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <pal...@dabbelt.com>" [unknown]
# gpg: aka "Palmer Dabbelt <palmerdabb...@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
# Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889
* tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu:
target/riscv: Fix vslide1up.vf and vslide1down.vf
target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
target/riscv: Smepmp: Skip applying default rules when address matches
MAINTAINERS: Add some RISC-V reviewers
target/riscv: Remove privileged spec version restriction for RVV
hw/riscv/boot.c: make riscv_load_initrd() static
hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/1270a3f57c92...b11728dc3ae6
