Branch: refs/heads/staging Home: https://github.com/qemu/qemu Commit: 343ed32dacd866e393a8fa4825c53bcd610330f5 https://github.com/qemu/qemu/commit/343ed32dacd866e393a8fa4825c53bcd610330f5 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths: M include/hw/core/cpu.h Log Message: ----------- include/hw/core: Add mmu_index to CPUClass To be used after all targets have populated the hook. Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 32a8ea12fab6b8f2959090819aa589c24b33715e https://github.com/qemu/qemu/commit/32a8ea12fab6b8f2959090819aa589c24b33715e Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/alpha/cpu.h M target/alpha/translate.c Log Message: ----------- target/alpha: Split out alpha_env_mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 9d6847904b83df2cb0d1a1b8e72d141331094054 https://github.com/qemu/qemu/commit/9d6847904b83df2cb0d1a1b8e72d141331094054 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/alpha/cpu.c Log Message: ----------- target/alpha: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: b7770d72f51505e7fbc4683b4c72085e40dcec51 https://github.com/qemu/qemu/commit/b7770d72f51505e7fbc4683b4c72085e40dcec51 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/arm/helper.c M target/arm/internals.h M target/arm/tcg/helper-a64.c M target/arm/tcg/mte_helper.c M target/arm/tcg/sve_helper.c M target/arm/tcg/tlb_helper.c Log Message: ----------- target/arm: Split out arm_env_mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 628421c74a64bcc7b4eda1218a66b77e89e02d4f https://github.com/qemu/qemu/commit/628421c74a64bcc7b4eda1218a66b77e89e02d4f Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/arm/cpu.c Log Message: ----------- target/arm: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: b9e877f20f22b308ef2c2fd5e3e7c3b6295db994 https://github.com/qemu/qemu/commit/b9e877f20f22b308ef2c2fd5e3e7c3b6295db994 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/avr/cpu.c M target/avr/cpu.h Log Message: ----------- target/avr: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 97fc0c210bf522d319f2c55c03c7f977f3f9b46c https://github.com/qemu/qemu/commit/97fc0c210bf522d319f2c55c03c7f977f3f9b46c Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/cris/translate.c M target/cris/translate_v10.c.inc Log Message: ----------- target/cris: Cache mem_index in DisasContext Compute this value once for each translation. Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 3f605a15a7ec14885ba34d15758ccaeceeee9f49 https://github.com/qemu/qemu/commit/3f605a15a7ec14885ba34d15758ccaeceeee9f49 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/cris/cpu.c Log Message: ----------- target/cris: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 8f39cb77643828e08fe3320a0080dd0e27dd8e3b https://github.com/qemu/qemu/commit/8f39cb77643828e08fe3320a0080dd0e27dd8e3b Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/hppa/cpu.c M target/hppa/cpu.h Log Message: ----------- target/hppa: Populate CPUClass.mmu_index Reviewed-by: Helge Deller <del...@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: ace0c5fe595047d720c685478b22a5e4c572ac42 https://github.com/qemu/qemu/commit/ace0c5fe595047d720c685478b22a5e4c572ac42 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/i386/cpu.c M target/i386/cpu.h Log Message: ----------- target/i386: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: a72a1b105d22eaf9a095143a317e738a3ef12019 https://github.com/qemu/qemu/commit/a72a1b105d22eaf9a095143a317e738a3ef12019 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/loongarch/cpu.c M target/loongarch/cpu.h Log Message: ----------- target/loongarch: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 3f262d256802b72a2b819de260c5e57effbc53f7 https://github.com/qemu/qemu/commit/3f262d256802b72a2b819de260c5e57effbc53f7 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/loongarch/cpu.c M target/loongarch/cpu.h M target/loongarch/cpu_helper.c M target/loongarch/tcg/insn_trans/trans_privileged.c.inc M target/loongarch/tcg/translate.c Log Message: ----------- target/loongarch: Rename MMU_IDX_* The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. Rename to match generic code. Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: a5a2d7f64f0d71278fb338a25fb9a05f926b6845 https://github.com/qemu/qemu/commit/a5a2d7f64f0d71278fb338a25fb9a05f926b6845 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/m68k/cpu.c Log Message: ----------- target/m68k: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 167d6cd0e855eb64d51707fea194833695bac2c4 https://github.com/qemu/qemu/commit/167d6cd0e855eb64d51707fea194833695bac2c4 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/microblaze/cpu.c M target/microblaze/cpu.h Log Message: ----------- target/microblaze: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 4e999bf4197ae3dc58b7092260f98146920a7469 https://github.com/qemu/qemu/commit/4e999bf4197ae3dc58b7092260f98146920a7469 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/mips/cpu.h M target/mips/tcg/sysemu/tlb_helper.c Log Message: ----------- target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill Rather than adjust env->hflags so that the value computed by cpu_mmu_index() changes, compute the mmu_idx that we want directly and pass it down. Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX. Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 6ebf33c5dccf71ca7bbb0d3d799af82f79d6445b https://github.com/qemu/qemu/commit/6ebf33c5dccf71ca7bbb0d3d799af82f79d6445b Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/mips/cpu.h M target/mips/sysemu/physaddr.c M target/mips/tcg/msa_helper.c M target/mips/tcg/sysemu/cp0_helper.c M target/mips/tcg/sysemu/special_helper.c M target/mips/tcg/sysemu/tlb_helper.c Log Message: ----------- target/mips: Split out mips_env_mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 0efa3dc2757635e5a0dba745058e8eb2a126ffe5 https://github.com/qemu/qemu/commit/0efa3dc2757635e5a0dba745058e8eb2a126ffe5 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/mips/cpu.c Log Message: ----------- target/mips: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 498c7d78d3ef0346d3885842c505eb8d0ffb940e https://github.com/qemu/qemu/commit/498c7d78d3ef0346d3885842c505eb8d0ffb940e Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/nios2/cpu.c M target/nios2/cpu.h Log Message: ----------- target/nios2: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: db8b41941aabdfdc505b372ae8b8445581e96840 https://github.com/qemu/qemu/commit/db8b41941aabdfdc505b372ae8b8445581e96840 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/openrisc/cpu.c M target/openrisc/cpu.h Log Message: ----------- target/openrisc: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: fb00f730c5eb05b3c54da8b1f805008ca38672ea https://github.com/qemu/qemu/commit/fb00f730c5eb05b3c54da8b1f805008ca38672ea Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/ppc/cpu.h M target/ppc/cpu_init.c M target/ppc/mem_helper.c M target/ppc/mmu_common.c Log Message: ----------- target/ppc: Split out ppc_env_mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: f331e82c3d60ede1cf9482a31ba5fdb0a292b274 https://github.com/qemu/qemu/commit/f331e82c3d60ede1cf9482a31ba5fdb0a292b274 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/ppc/cpu_init.c Log Message: ----------- target/ppc: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 7f6f2ebbaa37d1c1db0e264d52d32893873aa635 https://github.com/qemu/qemu/commit/7f6f2ebbaa37d1c1db0e264d52d32893873aa635 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/riscv/cpu.h M target/riscv/cpu_helper.c Log Message: ----------- target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: d9996d0904398c236212e1d7678fd1b7f3554057 https://github.com/qemu/qemu/commit/d9996d0904398c236212e1d7678fd1b7f3554057 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/riscv/cpu_helper.c M target/riscv/op_helper.c M target/riscv/vector_helper.c Log Message: ----------- target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index Use the target-specific function name in preference to the generic name. Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: a5c7797496a276b695189015afcce31829b8705e https://github.com/qemu/qemu/commit/a5c7797496a276b695189015afcce31829b8705e Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/riscv/cpu.c Log Message: ----------- target/riscv: Populate CPUClass.mmu_index Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: ef5cc166da1934c3f9d430b82e7ce89c65f8b6aa https://github.com/qemu/qemu/commit/ef5cc166da1934c3f9d430b82e7ce89c65f8b6aa Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/rx/cpu.c Log Message: ----------- target/rx: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 90b7022e698d0d80e133957bb7baece66311247d https://github.com/qemu/qemu/commit/90b7022e698d0d80e133957bb7baece66311247d Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/s390x/cpu.h M target/s390x/tcg/mem_helper.c Log Message: ----------- target/s390x: Split out s390x_env_mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 4ef80b271fd59db418e43d8d37219b351f11a567 https://github.com/qemu/qemu/commit/4ef80b271fd59db418e43d8d37219b351f11a567 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/s390x/cpu.c Log Message: ----------- target/s390x: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 9ba49d722284b63ee9ccf20e27b1b31ad4a26c6c https://github.com/qemu/qemu/commit/9ba49d722284b63ee9ccf20e27b1b31ad4a26c6c Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sh4/cpu.c M target/sh4/cpu.h Log Message: ----------- target/sh4: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: e3547a7d0770ad3f8049d8f991abcf7756c0c96d https://github.com/qemu/qemu/commit/e3547a7d0770ad3f8049d8f991abcf7756c0c96d Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/cpu.c M target/sparc/cpu.h Log Message: ----------- target/sparc: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: eafa0f68c3924df193b64c121657bbffe3248076 https://github.com/qemu/qemu/commit/eafa0f68c3924df193b64c121657bbffe3248076 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/tricore/cpu.c Log Message: ----------- target/tricore: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 68283ff4b48344fb996384f0481b3d8d72c830fe https://github.com/qemu/qemu/commit/68283ff4b48344fb996384f0481b3d8d72c830fe Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/xtensa/cpu.c Log Message: ----------- target/xtensa: Populate CPUClass.mmu_index Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: a120d32097910edfc1612c604836582c3a4b83c6 https://github.com/qemu/qemu/commit/a120d32097910edfc1612c604836582c3a4b83c6 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M include/exec/cpu-all.h M include/exec/cpu-common.h M target/alpha/cpu.h M target/arm/cpu.h M target/avr/cpu.h M target/cris/cpu.h M target/hexagon/cpu.h M target/hppa/cpu.c M target/hppa/cpu.h M target/i386/cpu.c M target/i386/cpu.h M target/loongarch/cpu.c M target/loongarch/cpu.h M target/m68k/cpu.h M target/microblaze/cpu.c M target/microblaze/cpu.h M target/mips/cpu.h M target/nios2/cpu.c M target/nios2/cpu.h M target/openrisc/cpu.c M target/openrisc/cpu.h M target/ppc/cpu.h M target/riscv/cpu.h M target/rx/cpu.h M target/s390x/cpu.h M target/sh4/cpu.c M target/sh4/cpu.h M target/sparc/cpu.c M target/sparc/cpu.h M target/tricore/cpu.h M target/xtensa/cpu.h Log Message: ----------- include/exec: Implement cpu_mmu_index generically For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 3b916140043e2757dd8d51ec641a6885e960e6ca https://github.com/qemu/qemu/commit/3b916140043e2757dd8d51ec641a6885e960e6ca Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M accel/tcg/cputlb.c M accel/tcg/ldst_common.c.inc M include/exec/cpu-all.h M include/exec/cpu-common.h M semihosting/uaccess.c M target/cris/translate.c M target/hppa/mem_helper.c M target/hppa/op_helper.c M target/i386/tcg/translate.c M target/loongarch/cpu_helper.c M target/loongarch/tcg/tlb_helper.c M target/m68k/op_helper.c M target/microblaze/helper.c M target/microblaze/mmu.c M target/microblaze/translate.c M target/nios2/translate.c M target/openrisc/translate.c M target/sparc/cpu.h M target/sparc/ldst_helper.c M target/sparc/mmu_helper.c M target/tricore/helper.c M target/tricore/translate.c M target/xtensa/mmu_helper.c Log Message: ----------- include/exec: Change cpu_mmu_index argument to CPUState Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: da4038d2da6d3a3d5f86665bd51b2ba49df5d652 https://github.com/qemu/qemu/commit/da4038d2da6d3a3d5f86665bd51b2ba49df5d652 Author: Ilya Leoshkevich <i...@linux.ibm.com> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M tests/tcg/multiarch/gdbstub/prot-none.py Log Message: ----------- tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test The `if not probe_proc_self_mem` check never passes, because probe_proc_self_mem is a function object, which is a truthy value. Add parentheses in order to perform a function call. Fixes: dc84d50a7f9b ("tests/tcg: Add the PROT_NONE gdbstub test") Signed-off-by: Ilya Leoshkevich <i...@linux.ibm.com> Message-Id: <20240131220245.235993-1-...@linux.ibm.com> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Commit: 45bf0e7aa648369cf8ab2333bd20144806fc1be3 https://github.com/qemu/qemu/commit/45bf0e7aa648369cf8ab2333bd20144806fc1be3 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M tcg/loongarch64/tcg-target.c.inc Log Message: ----------- tcg/loongarch64: Set vector registers call clobbered Because there are more call clobbered registers than call saved registers, we begin with all registers as call clobbered and then reset those that are saved. This was missed when we introduced the LSX support. Cc: qemu-sta...@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136 Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Song Gao <gaos...@loongson.cn> Message-Id: <20240201233414.500588-1-richard.hender...@linaro.org> Commit: 98271007379bae8ca4300ae5d8cdc37ec662ee73 https://github.com/qemu/qemu/commit/98271007379bae8ca4300ae5d8cdc37ec662ee73 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/translate.c Log Message: ----------- target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY Align the operation to the 32-byte cacheline. Use 2 pair of i128 instead of 8 pair of i32. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-2-richard.hender...@linaro.org> Commit: 54c3e9534f81a733806ac823185918dfe88687a5 https://github.com/qemu/qemu/commit/54c3e9534f81a733806ac823185918dfe88687a5 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/translate.c Log Message: ----------- target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL Align the operation to the 32-byte cacheline. Use 2 i128 instead of 4 i64. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-3-richard.hender...@linaro.org> Commit: 388a6465957edea5759e727d5d54898fb4feba91 https://github.com/qemu/qemu/commit/388a6465957edea5759e727d5d54898fb4feba91 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/translate.c Log Message: ----------- target/sparc: Remove gen_dest_fpr_F Replace with tcg_temp_new_i32. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-4-richard.hender...@linaro.org> Commit: 33ec424535e2e8e5fa1fd78f691eb9c3c68fd449 https://github.com/qemu/qemu/commit/33ec424535e2e8e5fa1fd78f691eb9c3c68fd449 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/translate.c Log Message: ----------- target/sparc: Introduce gen_{load,store}_fpr_Q Use them for trans_FMOVq. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-5-richard.hender...@linaro.org> Commit: daf457d40f92dd5f957b206cc86d95d9c42350c6 https://github.com/qemu/qemu/commit/daf457d40f92dd5f957b206cc86d95d9c42350c6 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Inline FNEG, FABS These are simple bit manipulation insns. Begin using i128 for float128. Implement FMOVq with do_qq. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-6-richard.hender...@linaro.org> Commit: e41716be4db43446f7dd1688f66e9c27d2dace31 https://github.com/qemu/qemu/commit/e41716be4db43446f7dd1688f66e9c27d2dace31 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Use i128 for FSQRTq Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-7-richard.hender...@linaro.org> Commit: 16bedf89c1d5511e883a4b7ba41fc327ce1ccadb https://github.com/qemu/qemu/commit/16bedf89c1d5511e883a4b7ba41fc327ce1ccadb Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-8-richard.hender...@linaro.org> Commit: d81e3efed9c9c487c86bb834ab74302c643a703b https://github.com/qemu/qemu/commit/d81e3efed9c9c487c86bb834ab74302c643a703b Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Use i128 for FqTOs, FqTOi Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-9-richard.hender...@linaro.org> Commit: 25a5769e3b0da1c1f69e93af1ace8f7b5d0cd238 https://github.com/qemu/qemu/commit/25a5769e3b0da1c1f69e93af1ace8f7b5d0cd238 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Use i128 for FqTOd, FqTOx Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-10-richard.hender...@linaro.org> Commit: f3ceafad5e30891207282f18ad6c4e22d8902e6f https://github.com/qemu/qemu/commit/f3ceafad5e30891207282f18ad6c4e22d8902e6f Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Use i128 for FCMPq, FCMPEq Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-11-richard.hender...@linaro.org> Commit: 0b2a61cc26caa8e3ba6425f7c4159aa75fe520b9 https://github.com/qemu/qemu/commit/0b2a61cc26caa8e3ba6425f7c4159aa75fe520b9 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Use i128 for FsTOq, FiTOq Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-12-richard.hender...@linaro.org> Commit: fdc50716a0c9e522ea91a7e909a624f2a1c65e59 https://github.com/qemu/qemu/commit/fdc50716a0c9e522ea91a7e909a624f2a1c65e59 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Use i128 for FdTOq, FxTOq Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-13-richard.hender...@linaro.org> Commit: ba21dc991be87ee8e15d124a80b27ce626a77b14 https://github.com/qemu/qemu/commit/ba21dc991be87ee8e15d124a80b27ce626a77b14 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Use i128 for Fdmulq Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-14-richard.hender...@linaro.org> Commit: 41535ca6f4d708cf376d731930fd89f44c84c98a https://github.com/qemu/qemu/commit/41535ca6f4d708cf376d731930fd89f44c84c98a Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/cpu.h M target/sparc/fop_helper.c M target/sparc/ldst_helper.c Log Message: ----------- target/sparc: Remove qt0, qt1 temporaries These are no longer used for passing data to/from helpers. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-15-richard.hender...@linaro.org> Commit: 1ccd6e13ccc0913bd3750f47c697c3d7c31cd418 https://github.com/qemu/qemu/commit/1ccd6e13ccc0913bd3750f47c697c3d7c31cd418 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M linux-user/sparc/cpu_loop.c M linux-user/sparc/signal.c M target/sparc/cpu.c M target/sparc/cpu.h M target/sparc/fop_helper.c M target/sparc/gdbstub.c M target/sparc/helper.h M target/sparc/machine.c M target/sparc/translate.c Log Message: ----------- target/sparc: Introduce cpu_get_fsr, cpu_put_fsr Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-16-richard.hender...@linaro.org> Commit: 49bb972513ced00ac772c282246f3b46e3cd75c3 https://github.com/qemu/qemu/commit/49bb972513ced00ac772c282246f3b46e3cd75c3 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/cpu.c M target/sparc/cpu.h M target/sparc/fop_helper.c Log Message: ----------- target/sparc: Split ver from env->fsr This field is read-only. It is easier to store it separately and merge it only upon read. While we're at it, use FSR_VER_SHIFT to initialize fpu_version. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-17-richard.hender...@linaro.org> Commit: efeb8b07502570aa133a87f7430dd919a9f5c37a https://github.com/qemu/qemu/commit/efeb8b07502570aa133a87f7430dd919a9f5c37a Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/translate.c Log Message: ----------- target/sparc: Clear cexc and ftt in do_check_ieee_exceptions Don't do the clearing explicitly before each FPop, rather do it as part of the rest of exception handling. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-18-richard.hender...@linaro.org> Commit: db71391123dccccc2c8632a6f5ad451369a35391 https://github.com/qemu/qemu/commit/db71391123dccccc2c8632a6f5ad451369a35391 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Merge check_ieee_exceptions with FPop helpers If an exception is to be raised, the destination fp register should be unmodified. The current implementation is incorrect, in that double results will be written back before calling gen_helper_check_ieee_exceptions, despite the placement of gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[]. We can simplify the entire implementation by having each FPOp helper call check_ieee_exceptions. For the moment this requires that all FPop helpers write to the TCG global cpu_fsr, so remove TCG_CALL_NO_WG from the DEF_HELPER_FLAGS_*. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-19-richard.hender...@linaro.org> Commit: 3590f01ed288c23594ba4a1c54a9c3b68081526f https://github.com/qemu/qemu/commit/3590f01ed288c23594ba4a1c54a9c3b68081526f Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/cpu.h M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Split cexc and ftt from env->fsr These two fields are adjusted by all FPop insns. Having them separate makes it easier to set without masking. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-20-richard.hender...@linaro.org> Commit: c9fa8e586b2235cd173fdd8d4acaf2d84ed30009 https://github.com/qemu/qemu/commit/c9fa8e586b2235cd173fdd8d4acaf2d84ed30009 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Remove cpu_fsr Drop this field as a tcg global, loading it explicitly in the few places required. This means that all FPop helpers may once again be TCG_CALL_NO_WG. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-21-richard.hender...@linaro.org> Commit: d8c5b92f3f5982b16cf2058395d584d38b9143f7 https://github.com/qemu/qemu/commit/d8c5b92f3f5982b16cf2058395d584d38b9143f7 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/cpu.h M target/sparc/fop_helper.c M target/sparc/helper.h M target/sparc/translate.c Log Message: ----------- target/sparc: Split fcc out of env->fsr Represent each fcc field separately from the rest of fsr. This vastly simplifies floating-point comparisons. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-22-richard.hender...@linaro.org> Commit: 240f46b9f26f5aaa0495d30a6d49f94861d04014 https://github.com/qemu/qemu/commit/240f46b9f26f5aaa0495d30a6d49f94861d04014 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M target/sparc/cpu.h Log Message: ----------- target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK These macros are no longer used. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> Message-Id: <20231103173841.33651-23-richard.hender...@linaro.org> Commit: 6400be014f80e4c2c246eb8be709ea3a96428233 https://github.com/qemu/qemu/commit/6400be014f80e4c2c246eb8be709ea3a96428233 Author: Richard Henderson <richard.hender...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M linux-user/aarch64/vdso-be.so M linux-user/aarch64/vdso-le.so M linux-user/aarch64/vdso.S Log Message: ----------- linux-user/aarch64: Add padding before __kernel_rt_sigreturn Without this padding, an unwind through the signal handler will pick up the unwind info for the preceding syscall. This fixes gcc's 30_threads/thread/native_handle/cancel.cc. Cc: qemu-sta...@nongnu.org Fixes: ee95fae075c6 ("linux-user/aarch64: Add vdso") Resolves: https://linaro.atlassian.net/browse/GNU-974 Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alex Bennée <alex.ben...@linaro.org> Message-Id: <20240202034427.504686-1-richard.hender...@linaro.org> Commit: 709c5a650e030d7e651e4a72ba42016b44da7f93 https://github.com/qemu/qemu/commit/709c5a650e030d7e651e4a72ba42016b44da7f93 Author: Markus Armbruster <arm...@redhat.com> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M qapi/block-core.json M qapi/introspect.json Log Message: ----------- qapi: Drop redundant documentation of inherited members Documentation generated for SchemaInfo looks like The members of "SchemaInfoBuiltin" when "meta-type" is ""builtin"" The members of "SchemaInfoEnum" when "meta-type" is ""enum"" The members of "SchemaInfoArray" when "meta-type" is ""array"" The members of "SchemaInfoObject" when "meta-type" is ""object"" The members of "SchemaInfoAlternate" when "meta-type" is ""alternate"" The members of "SchemaInfoCommand" when "meta-type" is ""command"" The members of "SchemaInfoEvent" when "meta-type" is ""event"" Additional members depend on the value of "meta-type". The last line became redundant when commit 88f63467c57 (qapi2texi: Generate reference to base type members) added the lines preceding it. Drop it. BlockdevOptions has the same issue. Drop Remaining options are determined by the block driver. Signed-off-by: Markus Armbruster <arm...@redhat.com> Message-ID: <20240129115008.674248-2-arm...@redhat.com> Reviewed-by: Eric Blake <ebl...@redhat.com> Commit: 763db74d2b61e34b0747a353c791d0ad6eb8ad2b https://github.com/qemu/qemu/commit/763db74d2b61e34b0747a353c791d0ad6eb8ad2b Author: Markus Armbruster <arm...@redhat.com> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M qapi/misc-target.json Log Message: ----------- qapi: Drop redundant documentation of conditional Documentation generated for dump-skeys contains This command is only supported on s390 architecture. and If ~~ "TARGET_S390X" The former became redundant in commit 901a34a400a (qapi: add 'If:' section to generated documentation) added the latter. Drop the former. Signed-off-by: Markus Armbruster <arm...@redhat.com> Message-ID: <20240129115008.674248-3-arm...@redhat.com> Reviewed-by: Eric Blake <ebl...@redhat.com> Commit: e3240ac5800f11d0a00262d76180d9a3227131fb https://github.com/qemu/qemu/commit/e3240ac5800f11d0a00262d76180d9a3227131fb Author: Markus Armbruster <arm...@redhat.com> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M qapi/block-export.json Log Message: ----------- qapi: Elide "Potential additional modes" from generated docs Documentation of BlockExportRemoveMode has Potential additional modes to be added in the future: hide: Just hide export from new clients, leave existing connections as is. Remove export after all clients are disconnected. soft: Hide export from new clients, answer with ESHUTDOWN for all further requests from existing clients. I think this is useful only for developers. Elide it from generated documentation by turning it into a TODO section. This effectively reverts my own commit b71fd73cc45 (Revert "qapi: BlockExportRemoveMode: move comments to TODO"). At the time, I was about to elide TODO sections from the generated manual, I wasn't sure about this one, and decided to avoid change. And now I've made up my mind. Signed-off-by: Markus Armbruster <arm...@redhat.com> Message-ID: <20240129115008.674248-4-arm...@redhat.com> Reviewed-by: Eric Blake <ebl...@redhat.com> Commit: d6a5ca3acfcbc164bbb15a0690d997212b29d6c3 https://github.com/qemu/qemu/commit/d6a5ca3acfcbc164bbb15a0690d997212b29d6c3 Author: Markus Armbruster <arm...@redhat.com> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M qapi/block-core.json Log Message: ----------- qga: Move type description right after type name Documentation of type BlockdevOptionsIscsi describes the type's purpose after its members. Everywhere else, we do it the other way round. Move it for consistency. Signed-off-by: Markus Armbruster <arm...@redhat.com> Message-ID: <20240129115008.674248-5-arm...@redhat.com> Reviewed-by: Konstantin Kostiuk <kkost...@redhat.com> Commit: 3424ed6caf9759eb57405d965537fd5f3d70026b https://github.com/qemu/qemu/commit/3424ed6caf9759eb57405d965537fd5f3d70026b Author: Markus Armbruster <arm...@redhat.com> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M qga/qapi-schema.json Log Message: ----------- qga/qapi-schema: Move command description right after command name Documentation of commands guest-ssh-get-authorized-keys, guest-ssh-add-authorized-keys, and guest-ssh-remove-authorized-keys describes the command's purpose after its arguments. Everywhere else, we do it the other way round. Move it for consistency. Signed-off-by: Markus Armbruster <arm...@redhat.com> Message-ID: <20240129115008.674248-6-arm...@redhat.com> Reviewed-by: Konstantin Kostiuk <kkost...@redhat.com> Commit: 10eab96e1a03538ad658faed2afb680f041cc361 https://github.com/qemu/qemu/commit/10eab96e1a03538ad658faed2afb680f041cc361 Author: Peter Maydell <peter.mayd...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M accel/tcg/cputlb.c M accel/tcg/ldst_common.c.inc M include/exec/cpu-all.h M include/exec/cpu-common.h M include/hw/core/cpu.h M linux-user/aarch64/vdso-be.so M linux-user/aarch64/vdso-le.so M linux-user/aarch64/vdso.S M linux-user/sparc/cpu_loop.c M linux-user/sparc/signal.c M semihosting/uaccess.c M target/alpha/cpu.c M target/alpha/cpu.h M target/alpha/translate.c M target/arm/cpu.c M target/arm/cpu.h M target/arm/helper.c M target/arm/internals.h M target/arm/tcg/helper-a64.c M target/arm/tcg/mte_helper.c M target/arm/tcg/sve_helper.c M target/arm/tcg/tlb_helper.c M target/avr/cpu.c M target/avr/cpu.h M target/cris/cpu.c M target/cris/cpu.h M target/cris/translate.c M target/cris/translate_v10.c.inc M target/hexagon/cpu.h M target/hppa/cpu.c M target/hppa/cpu.h M target/hppa/mem_helper.c M target/hppa/op_helper.c M target/i386/cpu.c M target/i386/cpu.h M target/i386/tcg/translate.c M target/loongarch/cpu.c M target/loongarch/cpu.h M target/loongarch/cpu_helper.c M target/loongarch/tcg/insn_trans/trans_privileged.c.inc M target/loongarch/tcg/tlb_helper.c M target/loongarch/tcg/translate.c M target/m68k/cpu.c M target/m68k/cpu.h M target/m68k/op_helper.c M target/microblaze/cpu.c M target/microblaze/cpu.h M target/microblaze/helper.c M target/microblaze/mmu.c M target/microblaze/translate.c M target/mips/cpu.c M target/mips/cpu.h M target/mips/sysemu/physaddr.c M target/mips/tcg/msa_helper.c M target/mips/tcg/sysemu/cp0_helper.c M target/mips/tcg/sysemu/special_helper.c M target/mips/tcg/sysemu/tlb_helper.c M target/nios2/cpu.c M target/nios2/cpu.h M target/nios2/translate.c M target/openrisc/cpu.c M target/openrisc/cpu.h M target/openrisc/translate.c M target/ppc/cpu.h M target/ppc/cpu_init.c M target/ppc/mem_helper.c M target/ppc/mmu_common.c M target/riscv/cpu.c M target/riscv/cpu.h M target/riscv/cpu_helper.c M target/riscv/op_helper.c M target/riscv/vector_helper.c M target/rx/cpu.c M target/rx/cpu.h M target/s390x/cpu.c M target/s390x/cpu.h M target/s390x/tcg/mem_helper.c M target/sh4/cpu.c M target/sh4/cpu.h M target/sparc/cpu.c M target/sparc/cpu.h M target/sparc/fop_helper.c M target/sparc/gdbstub.c M target/sparc/helper.h M target/sparc/ldst_helper.c M target/sparc/machine.c M target/sparc/mmu_helper.c M target/sparc/translate.c M target/tricore/cpu.c M target/tricore/cpu.h M target/tricore/helper.c M target/tricore/translate.c M target/xtensa/cpu.c M target/xtensa/cpu.h M target/xtensa/mmu_helper.c M tcg/loongarch64/tcg-target.c.inc M tests/tcg/multiarch/gdbstub/prot-none.py Log Message: ----------- Merge tag 'pull-tcg-20240202-2' of https://gitlab.com/rth7680/qemu into staging tests/tcg: Fix multiarch/gdbstub/prot-none.py hw/core: Convert cpu_mmu_index to a CPUClass hook tcg/loongarch64: Set vector registers call clobbered target/sparc: floating-point cleanup linux-user/aarch64: Add padding before __kernel_rt_sigreturn # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmW95WkdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/p+Qf/eVmh5q0pZqcur7ft # 8FO0wlIz55OfhaA9MIpH7LEIHRKY37Ybebw2K6SPnx4FmPhLkaj4KXPPjT2nzdXw # J2nQM+TOyxOd18GG8P80qFQ1a72dj8VSIRVAl9T46KuPXS5B7luArImfBlUk/GwV # Qr/XkOPwVTp05E/ccMJ8PMlcVZw9osHVLqsaFVbsUv/FylTmstzA9c5Gw7/FTfkG # T2rk+7go+F4IXs/9uQuuFMOpQOZngXE621hnro+qle7j9oarEUVJloAgVn06o59O # fUjuoKO0aMCr2iQqNJTH7Dnqp5OIzzxUoXiNTOj0EimwWfAcUKthoFO2LGcy1/ew # wWNR/Q== # =e3J3 # -----END PGP SIGNATURE----- # gpg: Signature made Sat 03 Feb 2024 07:04:09 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.hender...@linaro.org" # gpg: Good signature from "Richard Henderson <richard.hender...@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240202-2' of https://gitlab.com/rth7680/qemu: (58 commits) linux-user/aarch64: Add padding before __kernel_rt_sigreturn target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK target/sparc: Split fcc out of env->fsr target/sparc: Remove cpu_fsr target/sparc: Split cexc and ftt from env->fsr target/sparc: Merge check_ieee_exceptions with FPop helpers target/sparc: Clear cexc and ftt in do_check_ieee_exceptions target/sparc: Split ver from env->fsr target/sparc: Introduce cpu_get_fsr, cpu_put_fsr target/sparc: Remove qt0, qt1 temporaries target/sparc: Use i128 for Fdmulq target/sparc: Use i128 for FdTOq, FxTOq target/sparc: Use i128 for FsTOq, FiTOq target/sparc: Use i128 for FCMPq, FCMPEq target/sparc: Use i128 for FqTOd, FqTOx target/sparc: Use i128 for FqTOs, FqTOi target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq target/sparc: Use i128 for FSQRTq target/sparc: Inline FNEG, FABS target/sparc: Introduce gen_{load,store}_fpr_Q ... Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Commit: 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440 https://github.com/qemu/qemu/commit/39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440 Author: Peter Maydell <peter.mayd...@linaro.org> Date: 2024-02-03 (Sat, 03 Feb 2024) Changed paths: M qapi/block-core.json M qapi/block-export.json M qapi/introspect.json M qapi/misc-target.json M qga/qapi-schema.json Log Message: ----------- Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging QAPI patches patches for 2024-02-03 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmW992gSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTgt4P/RLioQBDBeFw77RMVJqU7YHjvdPrFtVa # jpN3g+OqX7zN97aCfMnTueTi989qyHr7J8ufxcMsxKjxH8//Qs5vbkjVmzecxsiq # GOP0a1HrvvKvjAvttsM3OLYKWwwas5mvZ1wjerHItkC8t5QHIzAKHCHiJkzD5W0r # Kew9Mi9gzqRdETHlY+QFnwdr1ksG+L6iB3yefWu01emSPI5XXdQHGMyorYauwZGy # ettuSFwc/kVLd0wipsr7EKNEeK8c211EmAj4aqgpDSAzTDUyjNc/CjI1YGYvcBkz # 6ejgIRrUMmS3F9hytj0Gp0CC7mjAcZzMN3HNm1VHeuBR3Eo3iWnPAGeIV8w1bihp # GsioU+a6ZbcB1ylYRIadpUyrVABNGSlv9SLJiHYeZI+N/0Wz2ByWpYvjrmvvQIB9 # Kt7Tq+biab26OR+b7jZqae4d9EhTkYifP3cV2Bnv9gf9uONV8LRMDoCHSAm3EdCH # 3R361imS1y394YZbp2iMI4PxeNjh+PvL+rduNZbSGPNY+x9dEbBUH5YJBjnnw/Du # YM1yCiyoWyiQbSxGcILn9BCCBDcntof4XzFg7MYhN717fvQaLJMEuRlKE9LTC3GT # Wrbu4ZkTq7r//gXLtnO/L3S7y4inhKow3nKPXUmiqxVuRlRvLq06d1NHVI60FZFf # keNA4PC6X/6R # =2BzL # -----END PGP SIGNATURE----- # gpg: Signature made Sat 03 Feb 2024 08:20:56 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "arm...@redhat.com" # gpg: Good signature from "Markus Armbruster <arm...@redhat.com>" [full] # gpg: aka "Markus Armbruster <arm...@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru: qga/qapi-schema: Move command description right after command name qga: Move type description right after type name qapi: Elide "Potential additional modes" from generated docs qapi: Drop redundant documentation of conditional qapi: Drop redundant documentation of inherited members Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Compare: https://github.com/qemu/qemu/compare/4f2fdb10b5f7...39a6e4f87e7b