Branch: refs/heads/staging-9.1
Home: https://github.com/qemu/qemu
Commit: 20eee6cb3d3d75a471fbf200c68441893aa5491a
https://github.com/qemu/qemu/commit/20eee6cb3d3d75a471fbf200c68441893aa5491a
Author: Helge Deller <[email protected]>
Date: 2024-09-05 (Thu, 05 Sep 2024)
Changed paths:
M target/hppa/cpu.h
M target/hppa/helper.c
Log Message:
-----------
target/hppa: Fix PSW V-bit packaging in cpu_hppa_get for hppa64
While adding hppa64 support, the psw_v variable got extended from 32 to 64
bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt
processing, check bit 31 instead the 63th (sign) bit.
This fixes a hard to find Linux kernel boot issue where the loss of the PSW-V
bit due to an ITLB interruption in the middle of a series of ds/addc
instructions (from the divU milicode library) generated the wrong division
result and thus triggered a Linux kernel crash.
Link:
https://lore.kernel.org/lkml/[email protected]/
Reported-by: Guenter Roeck <[email protected]>
Signed-off-by: Helge Deller <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Tested-by: Guenter Roeck <[email protected]>
Fixes: 931adff31478 ("target/hppa: Update cpu_hppa_get/put_psw for hppa64")
Cc: [email protected] # v8.2+
(cherry picked from commit ead5078cf1a5f11d16e3e8462154c859620bcc7e)
Signed-off-by: Michael Tokarev <[email protected]>
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