Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 36324c6774d2da16edc97cd3c9b30aa34d3f7a83
https://github.com/qemu/qemu/commit/36324c6774d2da16edc97cd3c9b30aa34d3f7a83
Author: Akihiko Odaki <akihiko.od...@daynix.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M qom/object_interfaces.c
Log Message:
-----------
qom: Use command line syntax for default values in help
object_property_help() uses the conventional command line syntax instead
of the JSON syntax. In particular,
- Key-value pairs are written in the command line syntax.
- bool description passed to the function says on/off instead of
true/false.
However, there is one exception: default values are formatted into JSON.
While the command line and JSON syntaxes are consistent in many cases,
there are two types where they disagree:
string: The command line syntax omits quotes while JSON requires them.
bool: JSON only accepts true/false for bool but the command line syntax
accepts on/off too, and on/off are also more popular than
true/false. For example, the docs directory has 2045 "on"
occurances while it has only 194 "true" occurances.
on/off are also accepted by OnOffAuto so users do not have to
remember the type is bool or OnOffAuto to use the values.
Omit quotes for strings and use on/off for bools when formatting
default values for better consistency.
Signed-off-by: Akihiko Odaki <akihiko.od...@daynix.com>
Link: https://lore.kernel.org/r/20250207-bool-v1-1-5749d5d6d...@daynix.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 1433e38cc840957bafe6bc17a241c57cf93c90cd
https://github.com/qemu/qemu/commit/1433e38cc840957bafe6bc17a241c57cf93c90cd
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/timer/hpet.c
Log Message:
-----------
hpet: do not overwrite properties on post_load
Migration relies on having the same device configuration on the source
and destination. Therefore, there is no need to modify flags,
timer capabilities and the fw_cfg HPET block id on migration;
it was set to exactly the same values by realize.
Reviewed-by: Zhao Liu <zhao1....@intel.com> (hpet_post_load only)
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 9ee488670066b5fdeebf0015e9b4a40bdc3eccbf
https://github.com/qemu/qemu/commit/9ee488670066b5fdeebf0015e9b4a40bdc3eccbf
Author: Zhao Liu <zhao1....@intel.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/hw/timer/Kconfig
Log Message:
-----------
i386: Fix the missing Rust HPET configuration option
The configuration option of Rust HPET is missing, so that PC machine
can't boot with "hpet=on" when QEMU Rust support is enabled.
Add the Rust HPET configuration option.
Fixes: d128c341a744 ("i386: enable rust hpet for pc when rust is enabled")
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250217154416.3144571-1-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 4cfe9edb1b1961af9cda74351f73b0abb3159b67
https://github.com/qemu/qemu/commit/4cfe9edb1b1961af9cda74351f73b0abb3159b67
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/Cargo.lock
M rust/qemu-api/Cargo.toml
M scripts/archive-source.sh
M scripts/make-release
M subprojects/.gitignore
A subprojects/libc-0.2-rs.wrap
A subprojects/packagefiles/libc-0.2-rs/meson.build
Log Message:
-----------
rust: subprojects: add libc crate
This allows access to errno values.
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 23a4b3ebc74bbc6b6f44edf2255864042f122b82
https://github.com/qemu/qemu/commit/23a4b3ebc74bbc6b6f44edf2255864042f122b82
Author: Stephen Bates <sba...@raithlin.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/devices/nvme.rst
M hw/nvme/ctrl.c
M hw/nvme/nvme.h
M include/block/nvme.h
Log Message:
-----------
hw/nvme: Add OCP SMART / Health Information Extended Log Page
The Open Compute Project [1] includes a Datacenter NVMe
SSD Specification [2]. The most recent version of this specification
(as of November 2024) is 2.6.1. This specification layers on top of
the NVM Express specifications [3] to provide additional
functionality. A key part of of this is the 512 Byte OCP SMART / Health
Information Extended log page that is defined in Section 4.8.6 of the
specification.
We add a controller argument (ocp) that toggles on/off the SMART log
extended structure. To accommodate different vendor specific specifications
like OCP, we add a multiplexing function (nvme_vendor_specific_log) which
will route to the different log functions based on arguments and log ids.
We only return the OCP extended SMART log when the command is 0xC0 and ocp
has been turned on in the nvme argumants.
Though we add the whole nvme SMART log extended structure, we only populate
the physical_media_units_{read,written}, log_page_version and
log_page_uuid.
This patch is based on work done by Joel but has been modified enough
that he requested a co-developed-by tag rather than a signed-off-by.
[1]: https://www.opencompute.org/
[2]:
https://www.opencompute.org/documents/datacenter-nvme-ssd-specification-v2-6-1-pdf
[3]: https://nvmexpress.org/specifications/
Signed-off-by: Stephen Bates <sba...@raithlin.com>
Co-developed-by: Joel Granados <j.grana...@samsung.com>
Reviewed-by: Klaus Jensen <k.jen...@samsung.com>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: cd59f50ab017183805a0dd82f5e85159ecc355ce
https://github.com/qemu/qemu/commit/cd59f50ab017183805a0dd82f5e85159ecc355ce
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
M hw/nvme/ns.c
Log Message:
-----------
hw/nvme: always initialize a subsystem
If no nvme-subsys is explicitly configured, instantiate one.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: e7047adf1ebf4b5ad63e42c799d8334dcd3d139d
https://github.com/qemu/qemu/commit/e7047adf1ebf4b5ad63e42c799d8334dcd3d139d
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
M hw/nvme/nvme.h
M include/block/nvme.h
Log Message:
-----------
hw/nvme: make oacs dynamic
Virtualization Management needs sriov-related parameters. Only report
support for the command when that conditions are true.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: 9cf6ec06592dea1973e66cd5cedf96fc59639047
https://github.com/qemu/qemu/commit/9cf6ec06592dea1973e66cd5cedf96fc59639047
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
M hw/nvme/nvme.h
M include/block/nvme.h
Log Message:
-----------
hw/nvme: add knob for doorbell buffer config support
Add a 'dbcs' knob to allow Doorbell Buffer Config command to be
disabled.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: b202fb549dc487c5611564e5d03286748586aa34
https://github.com/qemu/qemu/commit/b202fb549dc487c5611564e5d03286748586aa34
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
M include/block/nvme.h
Log Message:
-----------
nvme: fix iocs status code values
The status codes related to I/O Command Sets are in the wrong group.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: d96a32de3fd0880a9340590fd279288e42e983c1
https://github.com/qemu/qemu/commit/d96a32de3fd0880a9340590fd279288e42e983c1
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
M include/block/nvme.h
Log Message:
-----------
hw/nvme: be compliant wrt. dsm processing limits
The specification states that,
> The controller shall set all three processing limit fields (i.e., the
> DMRL, DMRSL and DMSL fields) to non-zero values or shall clear all
> three processing limit fields to 0h.
So, set the DMRL and DMSL fields in addition to DMRSL.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: 8a420dd109b9e4e2244cfa32bc92829093268b3e
https://github.com/qemu/qemu/commit/8a420dd109b9e4e2244cfa32bc92829093268b3e
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/devel/rust.rst
M rust/qemu-api/meson.build
M rust/qemu-api/src/assertions.rs
A rust/qemu-api/src/errno.rs
M rust/qemu-api/src/lib.rs
M rust/qemu-api/src/prelude.rs
Log Message:
-----------
rust: add module to convert between success/-errno and io::Result
It is a common convention in QEMU to return a positive value in case of
success, and a negated errno value in case of error. Unfortunately,
using errno portably in Rust is a bit complicated; on Unix the errno
values are supported natively by io::Error, but on Windows they are not;
so, use the libc crate.
This is a set of utility functions that are used by both chardev and
block layer bindings.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 4cb7040d851cdd7b2622f83fd7d95a922225386b
https://github.com/qemu/qemu/commit/4cb7040d851cdd7b2622f83fd7d95a922225386b
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/qemu-api/tests/tests.rs
Log Message:
-----------
rust: tests: do not import bindings::*
Similar to the devices, spell the exact set of C functions that are
called directly.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: c48700e86d91004424e3a6496f194decb036dccb
https://github.com/qemu/qemu/commit/c48700e86d91004424e3a6496f194decb036dccb
Author: Zhao Liu <zhao1....@intel.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
M rust/hw/char/pl011/src/device_class.rs
M rust/qemu-api/src/irq.rs
Log Message:
-----------
rust: prefer importing std::ptr over core::ptr
The std::ptr is same as core::ptr, but std has already been used in many
cases and there's no need to choose non-std library.
So, use std::ptr directly to make the used ptr library as consistent as
possible.
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250218080835.3341082-1-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 7a2e40866cf45a016858c73b9a5699b72be8ce38
https://github.com/qemu/qemu/commit/7a2e40866cf45a016858c73b9a5699b72be8ce38
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/devel/rust.rst
Log Message:
-----------
docs: rust: fix typos
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 29b9a66f9186f028ec46b58c9914d2da68c25c2c
https://github.com/qemu/qemu/commit/29b9a66f9186f028ec46b58c9914d2da68c25c2c
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/devel/rust.rst
Log Message:
-----------
docs: rust: update description of crates
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 5384d92e22577306408cefff887bc5a4b154f470
https://github.com/qemu/qemu/commit/5384d92e22577306408cefff887bc5a4b154f470
Author: Ilya Leoshkevich <i...@linux.ibm.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M stubs/meson.build
R stubs/monitor-fd.c
Log Message:
-----------
stub: Remove monitor-fd.c
Both monitor-fd.c and monitor-internal.c contain a stub for
monitor_get_fd(), which causes a duplicate symbol linker error when
linking rust-qemu-api-integration. Use monitor-internal.c instead of
monitor-fd.c and remove the latter.
Reported-by: Zhao Liu <zhao1....@intel.com>
Suggested-by: Zhao Liu <zhao1....@intel.com>
Fixes: fccb744f41c6 ("gdbstub: Try unlinking the unix socket before binding")
Signed-off-by: Ilya Leoshkevich <i...@linux.ibm.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250217104900.230122-1-...@linux.ibm.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 6debfb2cb1795427d2dc6a741c7430a233c76695
https://github.com/qemu/qemu/commit/6debfb2cb1795427d2dc6a741c7430a233c76695
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M system/physmem.c
Log Message:
-----------
physmem: replace assertion with error
It is possible to start QEMU with a confidential-guest-support object
even in TCG mode. While there is already a check in qemu_machine_creation_done:
if (machine->cgs && !machine->cgs->ready) {
error_setg(errp, "accelerator does not support confidential guest %s",
object_get_typename(OBJECT(machine->cgs)));
exit(1);
}
the creation of RAMBlocks happens earlier, in qemu_init_board(), if
the command line does not override the default memory backend with
-M memdev. Then the RAMBlock will try to use guest_memfd (because
machine_require_guest_memfd correctly returns true; at least correctly
according to the current implementation) and trigger the assertion
failure for kvm_enabled(). This happend with a command line as
simple as the following:
qemu-system-x86_64 -m 512 -nographic -object
sev-snp-guest,reduced-phys-bits=48,id=sev0 \
-M q35,kernel-irqchip=split,confidential-guest-support=sev0
qemu-system-x86_64: ../system/physmem.c:1871: ram_block_add: Assertion
`kvm_enabled()' failed.
Cc: Xiaoyao Li <xiaoyao...@intel.com>
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: David Hildenbrand <da...@redhat.com>
Reviewed-by: Pankaj Gupta <pankaj.gu...@amd.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Link: https://lore.kernel.org/r/20250217120812.396522-1-pbonz...@redhat.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ae3a420fea8bfc545a4ca4b899d2fe6a3031aefa
https://github.com/qemu/qemu/commit/ae3a420fea8bfc545a4ca4b899d2fe6a3031aefa
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M Kconfig.host
M hw/display/Kconfig
M hw/display/meson.build
M meson.build
Log Message:
-----------
pvg: do not enable it on cross-architecture targets
PVG is not cross-architecture; the PVG guest drivers with x86-64 macOS do not
give
useful results with the aarch64 macOS host PVG framework, and vice versa.
To express this repurpose CONFIG_MAC_PVG, making it true only if the target has
the same architecture as the host. Furthermore, remove apple-gfx.m unless
one of the devices is actually present.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d50ea7f0e6fd2b0631abb61d213a396e3df32d7e
https://github.com/qemu/qemu/commit/d50ea7f0e6fd2b0631abb61d213a396e3df32d7e
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/display/meson.build
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
pvg: add option to configure it out
... and also to require it (--enable-pvg). While at it, unify the dependency()
call for pvg and metal, which simplifies the logic a bit.
Note that all other Apple frameworks are either required or always-present,
therefore do not add them to the summary in the same way as PVG.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 2540917285872ab08f3ce66990983edd19ef4ec0
https://github.com/qemu/qemu/commit/2540917285872ab08f3ce66990983edd19ef4ec0
Author: Wei Liu <li...@linux.microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/hvf/hvf.c
M target/i386/hvf/x86.c
M target/i386/hvf/x86.h
M target/i386/hvf/x86_descr.c
M target/i386/hvf/x86_descr.h
M target/i386/hvf/x86_task.c
M target/i386/hvf/x86_task.h
Log Message:
-----------
target/i386/hvf: fix a typo in a type name
The prefix x68 is wrong. Change it to x86.
Signed-off-by: Wei Liu <li...@linux.microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link:
https://lore.kernel.org/r/1740126987-8483-2-git-send-email-li...@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: bc4fa8c3c9b5e2ad945617b667362b71b13495ad
https://github.com/qemu/qemu/commit/bc4fa8c3c9b5e2ad945617b667362b71b13495ad
Author: Wei Liu <li...@linux.microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/hvf/hvf-i386.h
M target/i386/hvf/hvf.c
M target/i386/hvf/x86_emu.c
Log Message:
-----------
target/i386/hvf: fix the declaration of hvf_handle_io
There is a conflicting declaration for hvf_handle_io in x86_emu.c. The type of
the first argument is wrong. There has never been a problem because the first
argument is not used in hvf_handle_io.
That being said, the code shouldn't contain such an error. Use the proper
declaration from hvf-i386.h.
Take the chance to change the first argument's type to be CPUState.
Signed-off-by: Wei Liu <li...@linux.microsoft.com>
Link:
https://lore.kernel.org/r/1740126987-8483-3-git-send-email-li...@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d54d3346b86d7c08b7fb2dac2d9a889854c7d3ba
https://github.com/qemu/qemu/commit/d54d3346b86d7c08b7fb2dac2d9a889854c7d3ba
Author: Wei Liu <li...@linux.microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/hvf/x86_decode.c
Log Message:
-----------
target/i386/hvf: use x86_segment in x86_decode.c
Make the code to rely on the segment definition for checking cs.db.
This allows removing HVF specific VMX related definition from the
decoder.
Introduce a function for retrieving the CS descriptor.
No functional change intended.
Signed-off-by: Wei Liu <li...@linux.microsoft.com>
Link:
https://lore.kernel.org/r/1740126987-8483-4-git-send-email-li...@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: dbccd48df0954069c12e13883ee8b2929a57ac6a
https://github.com/qemu/qemu/commit/dbccd48df0954069c12e13883ee8b2929a57ac6a
Author: Wei Liu <li...@linux.microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/hvf/hvf.c
M target/i386/hvf/x86_emu.c
M target/i386/hvf/x86_emu.h
M target/i386/hvf/x86_task.c
M target/i386/hvf/x86hvf.h
Log Message:
-----------
target/i386/hvf: move and rename {load, store}_regs
They contain HVF specific code. Move them to a better location and
add "hvf_" prefix. Fix up all the call sites.
No functional change.
Signed-off-by: Wei Liu <li...@linux.microsoft.com>
Link:
https://lore.kernel.org/r/1740126987-8483-7-git-send-email-li...@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 99e5aaf9afeed3e0437f6dbc7672e3028d2b2f4b
https://github.com/qemu/qemu/commit/99e5aaf9afeed3e0437f6dbc7672e3028d2b2f4b
Author: Wei Liu <li...@linux.microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/hvf/hvf-i386.h
M target/i386/hvf/hvf.c
M target/i386/hvf/x86_emu.c
M target/i386/hvf/x86_emu.h
Log Message:
-----------
target/i386/hvf: move and rename simulate_{rdmsr, wrmsr}
This requires making raise_exception non-static. That function needs to be
renamed to avoid clashing with a function in TCG.
Mostly code movement. No functional change.
Signed-off-by: Wei Liu <li...@linux.microsoft.com>
Link:
https://lore.kernel.org/r/1740126987-8483-12-git-send-email-li...@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 646140dfebd42a9a9df8f15a22027b7efcb072cf
https://github.com/qemu/qemu/commit/646140dfebd42a9a9df8f15a22027b7efcb072cf
Author: Wei Liu <li...@linux.microsoft.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/hvf/x86_emu.c
Log Message:
-----------
target/i386/hvf: drop some dead code
Signed-off-by: Wei Liu <li...@linux.microsoft.com>
Link:
https://lore.kernel.org/r/1740126987-8483-16-git-send-email-li...@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ac5699c5da51fa9d39bc964e81645953796f7ad1
https://github.com/qemu/qemu/commit/ac5699c5da51fa9d39bc964e81645953796f7ad1
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/qemu-api/src/qdev.rs
M rust/qemu-api/src/qom.rs
Log Message:
-----------
rust: add IsA bounds to QOM implementation traits
Check that the right bounds are provided to the qom_isa! macro
whenever the class is defined to implement a certain class.
This removes the need to add IsA<> bounds together with the
*Impl trait bounds.
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 3212da0033530ae896d31d90d5e81a772fc37088
https://github.com/qemu/qemu/commit/3212da0033530ae896d31d90d5e81a772fc37088
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
M rust/hw/timer/hpet/src/hpet.rs
M rust/qemu-api/src/sysbus.rs
Log Message:
-----------
rust: add SysBusDeviceImpl
The only function, right now, is to ensure that anything with a
SysBusDeviceClass class is a SysBusDevice.
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 4551f342fed66af7f5e2b099fa06f4007db356e6
https://github.com/qemu/qemu/commit/4551f342fed66af7f5e2b099fa06f4007db356e6
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
M rust/hw/timer/hpet/src/hpet.rs
M rust/qemu-api/src/qom.rs
M rust/qemu-api/tests/tests.rs
Log Message:
-----------
rust: qom: add ObjectImpl::CLASS_INIT
As shown in the PL011 device, the orphan rules required a manual
implementation of ClassInitImpl for anything not in the qemu_api crate;
this gets in the way of moving system emulation-specific code (including
DeviceClass, which as a blanket ClassInitImpl<DeviceClass> implementation)
into its own crate.
Make ClassInitImpl optional, at the cost of having to specify the CLASS_INIT
member by hand in every implementation of ObjectImpl. The next commits will
get rid of it, replacing all the "impl<T> ClassInitImpl<Class> for T" blocks
with a generic class_init<T> method on Class.
Right now the definition is always the same, but do not provide a default
as that will not be true once ClassInitImpl goes away.
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 567c0c41a6700be72eb9e040ba0b8d7bf0cc5919
https://github.com/qemu/qemu/commit/567c0c41a6700be72eb9e040ba0b8d7bf0cc5919
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
M rust/qemu-api/tests/tests.rs
Log Message:
-----------
rust: pl011, qemu_api tests: do not use ClassInitImpl
Outside the qemu_api crate, orphan rules make the usage of ClassInitImpl
unwieldy. Now that it is optional, do not use it.
For PL011Class, this makes it easier to provide a PL011Impl trait similar
to the ones in the qemu_api crate. The device id consts are moved there.
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d556226d6965738e06a1d75faaf271b769bb5880
https://github.com/qemu/qemu/commit/d556226d6965738e06a1d75faaf271b769bb5880
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
M rust/hw/timer/hpet/src/hpet.rs
M rust/qemu-api/src/qdev.rs
M rust/qemu-api/src/qom.rs
M rust/qemu-api/src/sysbus.rs
M rust/qemu-api/tests/tests.rs
Log Message:
-----------
rust: qom: get rid of ClassInitImpl
Complete the conversion from the ClassInitImpl trait to class_init() methods.
This will provide more freedom to split the qemu_api crate in separate parts.
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 2152b4bfcd91d7d8b99cd502ed049b0ab8e38649
https://github.com/qemu/qemu/commit/2152b4bfcd91d7d8b99cd502ed049b0ab8e38649
Author: Zhao Liu <zhao1....@intel.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
i386/cpu: Support module level cache topology
Allow cache to be defined at the module level. This increases
flexibility for x86 users to customize their cache topology.
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Tested-by: Yongwei Ma <yongwei...@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin <m...@redhat.com>
Link: https://lore.kernel.org/r/20250110145115.1574345-3-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 5ca9282d25157004601c520ed59dcb380177f728
https://github.com/qemu/qemu/commit/5ca9282d25157004601c520ed59dcb380177f728
Author: Zhao Liu <zhao1....@intel.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
i386/cpu: Update cache topology with machine's configuration
User will configure smp cache topology via -machine smp-cache.
For this case, update the x86 CPUs' cache topology with user's
configuration in MachineState.
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Tested-by: Yongwei Ma <yongwei...@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin <m...@redhat.com>
Link: https://lore.kernel.org/r/20250110145115.1574345-4-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 90df2cac3700188acadd12948fdad8e9b1459646
https://github.com/qemu/qemu/commit/90df2cac3700188acadd12948fdad8e9b1459646
Author: Zhao Liu <zhao1....@intel.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/i386/pc.c
M qemu-options.hx
Log Message:
-----------
i386/pc: Support cache topology in -machine for PC machine
Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC
machine.
Additionally, add the document of "-machine smp-cache" in
qemu-options.hx.
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Tested-by: Yongwei Ma <yongwei...@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin <m...@redhat.com>
Link: https://lore.kernel.org/r/20250110145115.1574345-5-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 47fc56f36d333263a5865caad306336e3e61e348
https://github.com/qemu/qemu/commit/47fc56f36d333263a5865caad306336e3e61e348
Author: Alireza Sanaee <alireza.san...@huawei.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/core/machine-smp.c
M include/hw/boards.h
M target/i386/cpu.c
Log Message:
-----------
i386/cpu: add has_caches flag to check smp_cache configuration
Add has_caches flag to SMPCompatProps, which helps in avoiding
extra checks for every single layer of caches in x86 (and ARM in
future).
Signed-off-by: Alireza Sanaee <alireza.san...@huawei.com>
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin <m...@redhat.com>
Link: https://lore.kernel.org/r/20250110145115.1574345-6-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 4044f46978ca6c55e5fcdda84310d7435c7c26ac
https://github.com/qemu/qemu/commit/4044f46978ca6c55e5fcdda84310d7435c7c26ac
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: remove unused macro DEFINE_CPU
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: aeb7969cba971472aba7a3bf1e0df1bcc1b6f44c
https://github.com/qemu/qemu/commit/aeb7969cba971472aba7a3bf1e0df1bcc1b6f44c
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: move 128-bit check to TCG realize
Besides removing non-declarative code in instance_init, this also fixes
an issue with query-cpu-model-expansion. Just invoking it for the
x-rv128 CPU model causes QEMU to exit immediately. With this patch it
is possible to do
{'execute': 'query-cpu-model-expansion',
'arguments':{'type': 'full', 'model': {'name': 'x-rv128'}}}
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 5d20aa540b6991c0dbeef933d2055e5372f52e0e
https://github.com/qemu/qemu/commit/5d20aa540b6991c0dbeef933d2055e5372f52e0e
Author: EwanHai <ewanhai...@zhaoxin.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add support for Zhaoxin CPU vendor identification
Zhaoxin currently uses two vendors: "Shanghai" and "Centaurhauls".
It is important to note that the latter now belongs to Zhaoxin. Therefore,
this patch replaces CPUID_VENDOR_VIA with CPUID_VENDOR_ZHAOXIN1.
The previous CPUID_VENDOR_VIA macro was only defined but never used in
QEMU, making this change straightforward.
Additionally, the IS_ZHAOXIN_CPU macro has been added to simplify the
checks for Zhaoxin CPUs.
Signed-off-by: EwanHai <ewanhai...@zhaoxin.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250113074413.297793-2-ewanhai...@zhaoxin.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: c0799e8b003713e07b546faba600363eccd179ee
https://github.com/qemu/qemu/commit/c0799e8b003713e07b546faba600363eccd179ee
Author: EwanHai <ewanhai...@zhaoxin.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
Add new CPUID feature flags for various Zhaoxin PadLock extensions.
These definitions will be used for Zhaoxin CPU models.
Signed-off-by: EwanHai <ewanhai...@zhaoxin.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250113074413.297793-3-ewanhai...@zhaoxin.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ff04bc1ac478656e5d6a255bf4069edb3f55bc58
https://github.com/qemu/qemu/commit/ff04bc1ac478656e5d6a255bf4069edb3f55bc58
Author: EwanHai <ewanhai...@zhaoxin.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Introduce Zhaoxin Yongfeng CPU model
Introduce support for the Zhaoxin Yongfeng CPU model.
The Zhaoxin Yongfeng CPU is Zhaoxin's latest server CPU.
This new cpu model ensure that QEMU can correctly emulate the Zhaoxin
Yongfeng CPU, providing accurate functionality and performance characteristics.
Signed-off-by: EwanHai <ewanhai...@zhaoxin.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250113074413.297793-4-ewanhai...@zhaoxin.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: a4e749780bd20593c0c386612a51bf4d64a80132
https://github.com/qemu/qemu/commit/a4e749780bd20593c0c386612a51bf4d64a80132
Author: EwanHai <ewanhai...@zhaoxin.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Mask CMPLegacy bit in CPUID[0x80000001].ECX for Zhaoxin CPUs
Zhaoxin CPUs (including vendors "Shanghai" and "Centaurhauls") handle the
CMPLegacy bit similarly to Intel CPUs. Therefore, this commit masks the
CMPLegacy bit in CPUID[0x80000001].ECX for Zhaoxin CPUs, just as it is done
for Intel CPUs.
AMD uses the CMPLegacy bit (CPUID[0x80000001].ECX.bit1) along with other CPUID
information to enumerate platform topology (e.g., the number of logical
processors per package). However, for Intel and other CPUs that follow Intel's
behavior, CPUID[0x80000001].ECX.bit1 is reserved.
- Impact on Intel and similar CPUs:
This change has no effect on Intel and similar CPUs, as the goal is to
accurately emulate CPU CPUID information.
- Impact on Linux Guests running on Intel (and similar) vCPUs:
During boot, Linux checks if the CPU supports Hyper-Threading. For the Linux
kernel before v6.9, if it detects X86_FEATURE_CMP_LEGACY, it assumes
Hyper-Threading is not supported. For Intel and similar vCPUs, if the
CMPLegacy bit is not masked in CPUID[0x80000001].ECX, Linux will incorrectly
assume that Hyper-Threading is not supported, even if the vCPU does support it.
Signed-off-by: EwanHai <ewanhai...@zhaoxin.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250113074413.297793-5-ewanhai...@zhaoxin.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 6ccca4b6bb9f994cc04e71004e1767a3476d2b23
https://github.com/qemu/qemu/commit/6ccca4b6bb9f994cc04e71004e1767a3476d2b23
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
M hw/nvme/ns.c
M hw/nvme/nvme.h
M include/block/nvme.h
Log Message:
-----------
hw/nvme: rework csi handling
The controller incorrectly allows a zoned namespace to be attached even
if CS.CSS is configured to only support the NVM command set for I/O
queues.
Rework handling of namespace command sets in general by attaching
supported namespaces when the controller is started instead of, like
now, statically when realized.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: 304babd9401d8ce8fe139a70fe464332eef2cee0
https://github.com/qemu/qemu/commit/304babd9401d8ce8fe139a70fe464332eef2cee0
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
Log Message:
-----------
hw/nvme: only set command abort requested when cancelled due to Abort
The Command Abort Requested status code should only be set if the
command was explicitly cancelled due to an Abort command. Or, in the
case the cancel was due to Submission Queue deletion, set the status
code to Command Aborted due to SQ Deletion.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: 6fc39228ffe9d54388f6d1080b502634df13bb72
https://github.com/qemu/qemu/commit/6fc39228ffe9d54388f6d1080b502634df13bb72
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
M include/block/nvme.h
Log Message:
-----------
hw/nvme: set error status code explicitly for misc commands
The nvme_aio_err() does not handle Verify, Compare, Copy and other misc
commands and defaults to setting the error status code to Internal
Device Error. For some of these commands, we know better, so set it
explicitly.
For the commands using the nvme_misc_cb() callback (Copy, Flush, ...),
if no status code has explicitly been set by the lower handlers, default
to Internal Device Error as previously.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: cad58ada8f104bf342097a7a683ef594ac949c8d
https://github.com/qemu/qemu/commit/cad58ada8f104bf342097a7a683ef594ac949c8d
Author: Klaus Jensen <k.jen...@samsung.com>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M hw/nvme/ctrl.c
Log Message:
-----------
hw/nvme: remove nvme_aio_err()
nvme_rw_complete_cb() is the only remaining user of nvme_aio_err(), so
open code the status code setting instead.
Reviewed-by: Jesper Wendel Devantier <f...@defmacro.it>
Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Commit: fa4d79c64dae03ffa269e42e21822453856618b7
https://github.com/qemu/qemu/commit/fa4d79c64dae03ffa269e42e21822453856618b7
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M scripts/checkpatch.pl
Log Message:
-----------
scripts: mandate that new files have SPDX-License-Identifier
Going forward we want all newly created source files to have an
SPDX-License-Identifier tag present.
Initially mandate this for C, Python, Perl, Shell source files,
as well as JSON (QAPI) and Makefiles, while encouraging users
to consider it for other file types.
Reviewed-by: Brian Cain <bc...@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Commit: 2b96c1a4931e3b4e0294761c16759bcbb2652df4
https://github.com/qemu/qemu/commit/2b96c1a4931e3b4e0294761c16759bcbb2652df4
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M scripts/checkpatch.pl
Log Message:
-----------
scripts: validate SPDX license choices
We expect all new code to be contributed with the "GPL-2.0-or-later"
license tag. Divergence is permitted if the new file is derived from
pre-existing code under a different license, whether from elsewhere
in QEMU codebase, or outside.
Issue a warning if the declared license is not "GPL-2.0-or-later",
and an error if the license is not one of the handful of the
expected licenses to prevent unintended proliferation. The warning
asks users to explain their unusual choice of license in the commit
message.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Commit: 6b7521818b26134726b3494cd06f04e30659ce2c
https://github.com/qemu/qemu/commit/6b7521818b26134726b3494cd06f04e30659ce2c
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-02-28 (Fri, 28 Feb 2025)
Changed paths:
M scripts/checkpatch.pl
Log Message:
-----------
scripts: forbid use of arbitrary SPDX tags besides license identifiers
While SPDX-License-Identifier is a well known SPDX tag, there are a
great many more besides that[1]. These are mostly focused on making
machine readable metadata available to the 'reuse' tool and similar.
They cover concepts like author names, copyright owners, and much
more. It is even possible to define source file line groups and apply
different SPDX tags to regions of code within a file.
At this time we're only interested in adopting SPDX for recording the
file global licensing info, so detect & reject any other SPDX metadata.
If we want to explicitly collect extra data in SPDX format, we can
evaluate each data item on its merits when someone wants to propose it
at a later date.
[1] https://spdx.github.io/spdx-spec/v2.2.2/file-tags/
https://spdx.github.io/spdx-spec/v2.2.2/file-information/
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Commit: 09951f5a27a7f8633118c1808cf17e66b30c3c62
https://github.com/qemu/qemu/commit/09951f5a27a7f8633118c1808cf17e66b30c3c62
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M MAINTAINERS
A docs/system/arm/imx8mp-evk.rst
M docs/system/arm/virt.rst
M docs/system/target-arm.rst
M fpu/meson.build
M fpu/softfloat-parts.c.inc
M fpu/softfloat-specialize.c.inc
M fpu/softfloat.c
M hw/arm/Kconfig
M hw/arm/boot.c
A hw/arm/fsl-imx8mp.c
A hw/arm/imx8mp-evk.c
M hw/arm/meson.build
M hw/arm/smmuv3.c
M hw/arm/virt.c
M hw/core/loader-fit.c
M hw/core/machine.c
M hw/gpio/Kconfig
M hw/loongarch/virt-fdt-build.c
M hw/mips/boston.c
M hw/misc/Kconfig
A hw/misc/imx8mp_analog.c
A hw/misc/imx8mp_ccm.c
M hw/misc/meson.build
M hw/misc/npcm_clk.c
M hw/openrisc/boot.c
M hw/openrisc/openrisc_sim.c
M hw/openrisc/virt.c
M hw/pci-host/Kconfig
M hw/pci-host/designware.c
A hw/pci-host/fsl_imx8m_phy.c
M hw/pci-host/meson.build
M hw/ppc/e500.c
M hw/ppc/pegasos2.c
M hw/ppc/pnv.c
M hw/ppc/spapr.c
M hw/riscv/boot.c
M hw/timer/imx_gpt.c
M hw/usb/hcd-dwc3.c
M include/fpu/softfloat-helpers.h
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
A include/hw/arm/fsl-imx8mp.h
M include/hw/loader-fit.h
A include/hw/misc/imx8mp_analog.h
A include/hw/misc/imx8mp_ccm.h
M include/hw/openrisc/boot.h
M include/hw/pci-host/designware.h
A include/hw/pci-host/fsl_imx8m_phy.h
M include/hw/timer/imx_gpt.h
M include/hw/usb/hcd-dwc3.h
M include/system/device_tree.h
M monitor/hmp-cmds.c
M system/device_tree-stub.c
M system/device_tree.c
M target/arm/hvf/hvf.c
M target/arm/internals.h
M target/arm/meson.build
M target/arm/tcg-stubs.c
M target/arm/tcg/meson.build
A target/arm/tcg/vfp_helper.c
A target/arm/vfp_fpscr.c
R target/arm/vfp_helper.c
M target/hppa/fpu_helper.c
M target/i386/tcg/fpu_helper.c
M target/m68k/cpu.c
M target/m68k/fpu_helper.c
M target/m68k/softfloat.c
M target/sh4/cpu.c
Log Message:
-----------
Merge tag 'pull-target-arm-20250225' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/smmuv3: Fill u.f_cd_fetch.addr for SMMU_EVT_F_CD_FETCH
* hw/arm/virt: Support larger highmem MMIO regions
* machine: Centralize -machine dumpdtb option handling and report
attempt to dump nonexistent DTB as an error
* fpu: remove target ifdefs and build it only once
* target/arm: Refactor to move TCG-only vfp_helper code into tcg/
* target/arm/hvf: Disable SME feature
* target/arm/hvf: sign extend the data for a load operation when SSE=1
* hw/misc/npcm_clk: fix buffer-overflow
* hw/arm: Add i.MX 8M Plus EVK board ("imx8mp-evk")
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 26 Feb 2025 02:02:12 HKT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.mayd...@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmayd...@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <pe...@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250225' of
https://git.linaro.org/people/pmaydell/qemu-arm: (43 commits)
hw/arm/fsl-imx8mp: Add on-chip RAM
hw/arm/fsl-imx8mp: Add USB support
hw/arm/fsl-imx8mp: Add Ethernet controller
hw/arm/fsl-imx8mp: Implement general purpose timers
hw/arm/fsl-imx8mp: Add watchdog support
hw/arm/fsl-imx8mp: Add SPI controllers
hw/arm/fsl-imx8mp: Add I2C controllers
hw/arm/fsl-imx8mp: Add GPIO controllers
hw/arm/fsl-imx8mp: Add PCIe support
hw/arm/fsl-imx8mp: Add USDHC storage controllers
hw/arm/fsl-imx8mp: Add SNVS
hw/arm/fsl-imx8mp: Implement clock tree
hw/arm: Add i.MX 8M Plus EVK board
hw/gpio/pca955*: Move Kconfig switches next to implementations
hw/pci-host/designware: Prevent device attachment on internal PCIe root bus
hw/usb/hcd-dwc3: Align global registers size with Linux
hw/misc/npcm_clk: fix buffer-overflow
target/arm/hvf: sign extend the data for a load operation when SSE=1
target/arm/hvf: Disable SME feature
target/arm: Rename vfp_helper.c to vfp_fpscr.c
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: ee376948ebd9cf74b4456a7422e5073a72e4486a
https://github.com/qemu/qemu/commit/ee376948ebd9cf74b4456a7422e5073a72e4486a
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M .gitlab-ci.d/check-dco.py
M .gitlab-ci.d/check-patch.py
M tests/avocado/replay_kernel.py
M tests/functional/meson.build
M tests/functional/replay_kernel.py
A tests/functional/test_aarch64_replay.py
A tests/functional/test_alpha_replay.py
A tests/functional/test_arm_replay.py
M tests/functional/test_arm_sx1.py
A tests/functional/test_m68k_replay.py
A tests/functional/test_microblaze_replay.py
M tests/functional/test_microblaze_s3adsp1800.py
M tests/functional/test_microblazeel_s3adsp1800.py
A tests/functional/test_or1k_replay.py
M tests/functional/test_ppc64_e500.py
A tests/functional/test_ppc64_replay.py
A tests/functional/test_ppc_replay.py
A tests/functional/test_s390x_replay.py
A tests/functional/test_sparc_replay.py
A tests/functional/test_x86_64_replay.py
A tests/functional/test_xtensa_replay.py
M tests/qtest/qom-test.c
Log Message:
-----------
Merge tag 'pull-request-2025-02-26' of https://gitlab.com/thuth/qemu into
staging
* Convert more avocado tests to the functional framework
* Fix a problem with the check-patch/check-dco CI jobs
* Replace the ppc64 e500 functional test with a better one
* Test retrieval of machine class properties
# -----BEGIN PGP SIGNATURE-----
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# =KMhF
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 26 Feb 2025 17:56:07 HKT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "th...@redhat.com"
# gpg: Good signature from "Thomas Huth <th.h...@gmx.de>" [full]
# gpg: aka "Thomas Huth <th...@redhat.com>" [full]
# gpg: aka "Thomas Huth <h...@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.h...@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2025-02-26' of https://gitlab.com/thuth/qemu:
tests/functional: Replace the ppc64 e500 advent calendar test
gitlab: use --refetch in check-patch/check-dco jobs
tests/functional: Bump some arm test timeouts
tests/functional: Convert the x86_64 replay avocado tests
tests/functional: Convert the aarch64 replay avocado tests
tests/functional: Convert the s390x replay avocado tests
tests/functional: Convert the alpha replay avocado tests
tests/functional: Convert the arm replay avocado tests
tests/functional: Convert the m68k replay avocado tests
tests/functional: Convert the microblaze replay avocado tests
tests/functional: Convert the ppc64 replay avocado tests
tests/functional: Convert the or1k replay avocado tests
tests/functional: Convert the 32-bit ppc replay avocado tests
tests/functional: Convert the sparc replay avocado test
tests/functional: Convert the xtensa replay test to the functional framework
tests/functional: Provide a proper name for the VMs in the replay tests
tests/qtest/qom-test: Test retrieval of machine class properties
tests/functional: Have microblaze tests inherit common parent class
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: ef3b5f5cd89fb573729a6dc10f1a1c49b20d0113
https://github.com/qemu/qemu/commit/ef3b5f5cd89fb573729a6dc10f1a1c49b20d0113
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M qga/commands-posix.c
M qga/commands-win32.c
M qga/main.c
Log Message:
-----------
Merge tag 'qga-pull-2025-02-26' of https://github.com/kostyanf14/qemu into
staging
qga-pull-2025-02-26
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# =kmxC
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 26 Feb 2025 20:19:06 HKT
# gpg: using RSA key C2C2C109EA43C63C1423EB84EF5D5E8161BA84E7
# gpg: Good signature from "Kostiantyn Kostiuk (Upstream PR sign)
<kkost...@redhat.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: C2C2 C109 EA43 C63C 1423 EB84 EF5D 5E81 61BA 84E7
* tag 'qga-pull-2025-02-26' of https://github.com/kostyanf14/qemu:
qga: Don't daemonize before channel is initialized
qga: Invert logic on return value in main()
qga: Add log to guest-fsfreeze-thaw command
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 70fc2bde913ef8a6b77ded6831534d9c79541e17
https://github.com/qemu/qemu/commit/70fc2bde913ef8a6b77ded6831534d9c79541e17
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M docs/system/devices/nvme.rst
M hw/nvme/ctrl.c
M hw/nvme/ns.c
M hw/nvme/nvme.h
M include/block/nvme.h
Log Message:
-----------
Merge tag 'pull-nvme-20250227' of https://gitlab.com/birkelund/qemu into
staging
nvme queue
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 27 Feb 2025 17:28:49 HKT
# gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9
# gpg: Good signature from "Klaus Jensen <i...@irrelevant.dk>" [unknown]
# gpg: aka "Klaus Jensen <k.jen...@samsung.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838
# Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9
* tag 'pull-nvme-20250227' of https://gitlab.com/birkelund/qemu:
hw/nvme: remove nvme_aio_err()
hw/nvme: set error status code explicitly for misc commands
hw/nvme: only set command abort requested when cancelled due to Abort
hw/nvme: rework csi handling
hw/nvme: be compliant wrt. dsm processing limits
nvme: fix iocs status code values
hw/nvme: add knob for doorbell buffer config support
hw/nvme: make oacs dynamic
hw/nvme: always initialize a subsystem
hw/nvme: Add OCP SMART / Health Information Extended Log Page
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 8d56d0fd2fcb5a99cd2f722d983c9c1199ff19b0
https://github.com/qemu/qemu/commit/8d56d0fd2fcb5a99cd2f722d983c9c1199ff19b0
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M Kconfig.host
M docs/devel/rust.rst
M hw/core/machine-smp.c
M hw/display/Kconfig
M hw/display/meson.build
M hw/i386/pc.c
M hw/timer/hpet.c
M include/hw/boards.h
M meson.build
M meson_options.txt
M qemu-options.hx
M qom/object_interfaces.c
M rust/Cargo.lock
M rust/hw/char/pl011/src/device.rs
M rust/hw/char/pl011/src/device_class.rs
M rust/hw/timer/Kconfig
M rust/hw/timer/hpet/src/hpet.rs
M rust/qemu-api/Cargo.toml
M rust/qemu-api/meson.build
M rust/qemu-api/src/assertions.rs
A rust/qemu-api/src/errno.rs
M rust/qemu-api/src/irq.rs
M rust/qemu-api/src/lib.rs
M rust/qemu-api/src/prelude.rs
M rust/qemu-api/src/qdev.rs
M rust/qemu-api/src/qom.rs
M rust/qemu-api/src/sysbus.rs
M rust/qemu-api/tests/tests.rs
M scripts/archive-source.sh
M scripts/make-release
M scripts/meson-buildoptions.sh
M stubs/meson.build
R stubs/monitor-fd.c
M subprojects/.gitignore
A subprojects/libc-0.2-rs.wrap
A subprojects/packagefiles/libc-0.2-rs/meson.build
M system/physmem.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/hvf/hvf-i386.h
M target/i386/hvf/hvf.c
M target/i386/hvf/x86.c
M target/i386/hvf/x86.h
M target/i386/hvf/x86_decode.c
M target/i386/hvf/x86_descr.c
M target/i386/hvf/x86_descr.h
M target/i386/hvf/x86_emu.c
M target/i386/hvf/x86_emu.h
M target/i386/hvf/x86_task.c
M target/i386/hvf/x86_task.h
M target/i386/hvf/x86hvf.h
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* qom: Use command line syntax for default values in help
* i386: support cache topology with machine's configuration
* rust: fix duplicate symbols from monitor-fd.c
* rust: add module to convert between success/-errno and io::Result
* rust: move class_init implementation from trait to method
* pvg: configuration improvements
* kvm guestmemfd: replace assertion with error
* riscv: cleanups
* target/i386/hvf: cleanups to emulation
* target/i386: add Zhaoxin and Yongfeng CPU model
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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 26 Feb 2025 16:56:43 HKT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonz...@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonz...@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonz...@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (34 commits)
target/i386: Mask CMPLegacy bit in CPUID[0x80000001].ECX for Zhaoxin CPUs
target/i386: Introduce Zhaoxin Yongfeng CPU model
target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
target/i386: Add support for Zhaoxin CPU vendor identification
target/riscv: move 128-bit check to TCG realize
target/riscv: remove unused macro DEFINE_CPU
i386/cpu: add has_caches flag to check smp_cache configuration
i386/pc: Support cache topology in -machine for PC machine
i386/cpu: Update cache topology with machine's configuration
i386/cpu: Support module level cache topology
rust: qom: get rid of ClassInitImpl
rust: pl011, qemu_api tests: do not use ClassInitImpl
rust: qom: add ObjectImpl::CLASS_INIT
rust: add SysBusDeviceImpl
rust: add IsA bounds to QOM implementation traits
target/i386/hvf: drop some dead code
target/i386/hvf: move and rename simulate_{rdmsr, wrmsr}
target/i386/hvf: move and rename {load, store}_regs
target/i386/hvf: use x86_segment in x86_decode.c
target/i386/hvf: fix the declaration of hvf_handle_io
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 354925d42252f6f36a9e1e4a6b929aaafb2eaf45
https://github.com/qemu/qemu/commit/354925d42252f6f36a9e1e4a6b929aaafb2eaf45
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-03-03 (Mon, 03 Mar 2025)
Changed paths:
M scripts/checkpatch.pl
Log Message:
-----------
Merge tag 'spdx-check-pull-request' of https://gitlab.com/berrange/qemu into
staging
SPDX support for checkpatch
* Mandate use of SPDX-License-Identifier in new files
* Validate SPDX license choices
* Forbid other SPDX tags
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# =eGL+
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 28 Feb 2025 23:43:50 HKT
# gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <d...@berrange.com>" [full]
# gpg: aka "Daniel P. Berrange <berra...@redhat.com>" [full]
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF
* tag 'spdx-check-pull-request' of https://gitlab.com/berrange/qemu:
scripts: forbid use of arbitrary SPDX tags besides license identifiers
scripts: validate SPDX license choices
scripts: mandate that new files have SPDX-License-Identifier
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Compare: https://github.com/qemu/qemu/compare/b6403d88cb9f...354925d42252
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