Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 43625e35d9319821f6d51cbf2798991bca533b26
https://github.com/qemu/qemu/commit/43625e35d9319821f6d51cbf2798991bca533b26
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/user-exec.c
M include/user/page-protection.h
M linux-user/elfload.c
Log Message:
-----------
accel/tcg: Add CPUState argument to page_unprotect
In the next patch, page_unprotect will need to pass
the CPUState to tb_invalidate_phys_page_unwind.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 00f708841f00d8b7046d03ef88045908f394b27d
https://github.com/qemu/qemu/commit/00f708841f00d8b7046d03ef88045908f394b27d
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/tb-internal.h
M accel/tcg/tb-maint.c
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Add CPUState argument to tb_invalidate_phys_page_unwind
Replace existing usage of current_cpu.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: e4ad80ceac03cc47d8351172f0e4625bb40e2b78
https://github.com/qemu/qemu/commit/e4ad80ceac03cc47d8351172f0e4625bb40e2b78
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/tb-maint.c
Log Message:
-----------
accel/tcg: Add CPUState arg to tb_invalidate_phys_page_range__locked
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 4af02681ff77bf105b11ee1a5ca289ca29b64a54
https://github.com/qemu/qemu/commit/4af02681ff77bf105b11ee1a5ca289ca29b64a54
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/tb-maint.c
Log Message:
-----------
accel/tcg: Merge tb_invalidate_phys_range{__locked}
Merge tb_invalidate_phys_page_fast__locked into its
only caller, tb_invalidate_phys_range_fast.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 072e057ed90d6bbc4f01ac04e627e63f275f57f0
https://github.com/qemu/qemu/commit/072e057ed90d6bbc4f01ac04e627e63f275f57f0
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/tb-maint.c
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
M include/exec/exec-all.h
M system/physmem.c
M target/arm/helper.c
Log Message:
-----------
accel/tcg: Add CPUState arg to tb_invalidate_phys_range
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 7fa0f4a70c1550380b2a3ee1330f70ce6ee98072
https://github.com/qemu/qemu/commit/7fa0f4a70c1550380b2a3ee1330f70ce6ee98072
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tb-internal.h
M accel/tcg/tb-maint.c
Log Message:
-----------
accel/tcg: Add CPUState arg to tb_invalidate_phys_range_fast
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 77ad412b326031687f0eeb7935350e597337c93b
https://github.com/qemu/qemu/commit/77ad412b326031687f0eeb7935350e597337c93b
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/tb-maint.c
M accel/tcg/user-exec.c
M include/accel/tcg/cpu-ops.h
M include/exec/poison.h
M target/i386/cpu.h
M target/i386/tcg/tcg-cpu.c
M target/s390x/cpu.c
M target/s390x/cpu.h
Log Message:
-----------
accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc
Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition,
have each target set the 'precise_smc' field in the TCGCPUOps
structure.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 80e865668d953c012723c3af9fd1ff7258cef864
https://github.com/qemu/qemu/commit/80e865668d953c012723c3af9fd1ff7258cef864
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/tlb-bounds.h
Log Message:
-----------
accel/tcg: Simplify CPU_TLB_DYN_MAX_BITS
Stop taking TARGET_VIRT_ADDR_SPACE_BITS into account.
Since we currently bound CPU_TLB_DYN_MAX_BITS to 22,
the new bound with a 4k page size is 20, which isn't
so different.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 2e8fe327eb67f90822a3e8a8fb6c914dd573f299
https://github.com/qemu/qemu/commit/2e8fe327eb67f90822a3e8a8fb6c914dd573f299
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/tb-maint.c
Log Message:
-----------
accel/tcg: Simplify L1_MAP_ADDR_SPACE_BITS
Stop taking TARGET_PHYS_ADDR_SPACE_BITS into account.
Simply allow the entire ram_addr_t space.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: dfda9281266d57899dc03fc613a25587babd67aa
https://github.com/qemu/qemu/commit/dfda9281266d57899dc03fc613a25587babd67aa
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/internal-common.h
R accel/tcg/internal-target.h
M accel/tcg/tb-maint.c
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Merge internal-target.h into internal-common.h
There's nothing left in internal-target.h that is
target specific.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 54bd0b135e53d3afe666c5c960d7b2a0c1767bf4
https://github.com/qemu/qemu/commit/54bd0b135e53d3afe666c5c960d7b2a0c1767bf4
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/internal-common.h
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Reduce scope of tb_phys_invalidate, tb_set_jmp_target
Move the declarations of these functions out of exec/exec-all.h
to accel/tcg/internal-common.h.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: e1c8eb8cfec059e882066403819288d036fbbe8e
https://github.com/qemu/qemu/commit/e1c8eb8cfec059e882066403819288d036fbbe8e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/user-exec.c
M include/user/page-protection.h
M linux-user/elfload.c
M linux-user/syscall.c
Log Message:
-----------
accel/tcg: Use vaddr for walk_memory_regions callback
Use vaddr instead of target_ulong. At the same time,
use int instead of unsigned long for flags, to match
page_set_flags().
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 5627d5c00a256cc180b659f7c21383e36934a80c
https://github.com/qemu/qemu/commit/5627d5c00a256cc180b659f7c21383e36934a80c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/user-exec.c
M include/user/page-protection.h
Log Message:
-----------
accel/tcg: Use vaddr in user/page-protection.h
Reviewed-by: Anton Johansson <a...@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 5f2446eb82bcb89c0969feffdd88c4eea05edfcd
https://github.com/qemu/qemu/commit/5f2446eb82bcb89c0969feffdd88c4eea05edfcd
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M include/exec/exec-all.h
Log Message:
-----------
include/exec: Include missing headers in exec-all.h
"exec/exec-all.h" declares prototypes such:
void *probe_access(CPUArchState *env, vaddr addr, int size,
^^^^^
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
MemoryRegionSection *iotlb_to_section(CPUState *cpu,
hwaddr index,
^^^^^^
MemTxAttrs attrs);
^^^^^^^^^^
vaddr is defined in "exec/vaddr.h", hwaddr in "exec/hwaddr.h"
and MemTxAttrs in "exec/memattrs.h". All these headers are
indirectly pulled in via "exec/translation-block.h". Since
we will remove "exec/translation-block.h" in the next commit,
include the missing ones, otherwise we'd get errors such:
include/exec/exec-all.h:51:1: error: unknown type name 'hwaddr'
51 | hwaddr memory_region_section_get_iotlb(CPUState *cpu,
| ^
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.caveayl...@nutanix.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250424202412.91612-5-phi...@linaro.org>
Commit: 0b87b740c27cabbd4f8447631d026c28ca83f7db
https://github.com/qemu/qemu/commit/0b87b740c27cabbd4f8447631d026c28ca83f7db
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M include/exec/exec-all.h
M include/exec/translation-block.h
Log Message:
-----------
include/exec: Move tb_invalidate_phys_range to translation-block.h
Reviewed-by: Anton Johansson <a...@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 7795eded0477f21c8518176492c4e19d103dde2c
https://github.com/qemu/qemu/commit/7795eded0477f21c8518176492c4e19d103dde2c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/meson.build
M accel/tcg/tb-hash.h
M accel/tcg/tb-maint.c
Log Message:
-----------
accel/tcg: Compile tb-maint.c twice
Reviewed-by: Anton Johansson <a...@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 3ea423c27f4eabee5068fce27412761fa3db8b0f
https://github.com/qemu/qemu/commit/3ea423c27f4eabee5068fce27412761fa3db8b0f
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M include/accel/tcg/getpc.h
Log Message:
-----------
accel/tcg: Remove #error for non-tcg in getpc.h
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 0f81774dd1c19de5dedb3c8f2d74e5b9a73d8c12
https://github.com/qemu/qemu/commit/0f81774dd1c19de5dedb3c8f2d74e5b9a73d8c12
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c
"accel/tcg/getpc.h" is pulled in indirectly. Include it
explicitly to avoid when refactoring unrelated headers:
target/riscv/csr.c:2117:25: error: call to undeclared function 'GETPC'
[-Wimplicit-function-declaration]
2117 | if ((val & RVC) && (GETPC() & ~3) != 0) {
| ^
Note the TODO comment around GETPC() added upon introduction in
commit f18637cd611 ("RISC-V: Add misa runtime write support"):
2099 static RISCVException write_misa(CPURISCVState *env, int csrno,
2100 target_ulong val)
2101 {
...
2113 /*
2114 * Suppress 'C' if next instruction is not aligned
2115 * TODO: this should check next_pc
2116 */
2117 if ((val & RVC) && (GETPC() & ~3) != 0) {
2118 val &= ~RVC;
2119 }
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.caveayl...@nutanix.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250424202412.91612-8-phi...@linaro.org>
Commit: 98db62318ae98be9a57b3c01f7f97a984ac1b79b
https://github.com/qemu/qemu/commit/98db62318ae98be9a57b3c01f7f97a984ac1b79b
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M include/exec/helper-proto-common.h
M target/avr/helper.c
Log Message:
-----------
accel/tcg: Include 'accel/tcg/getpc.h' in 'exec/helper-proto'
Most files including "exec/helper-proto.h" call GETPC().
Include it there (in the common part) instead of the
unspecific "exec/exec-all.h" header.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250424202412.91612-10-phi...@linaro.org>
Commit: 1381ea53a84234a0aac212baeae922137ad4bbda
https://github.com/qemu/qemu/commit/1381ea53a84234a0aac212baeae922137ad4bbda
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M system/physmem.c
Log Message:
-----------
physmem: Move TCG IOTLB methods around
The next commit will restrict TCG specific code in physmem.c
using some #ifdef'ry. In order to keep it simple, move
iotlb_to_section() and memory_region_section_get_iotlb()
around close together.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.caveayl...@nutanix.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250424202412.91612-11-phi...@linaro.org>
Commit: f12b717717c45627d667b609326fda54f0ad0394
https://github.com/qemu/qemu/commit/f12b717717c45627d667b609326fda54f0ad0394
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M MAINTAINERS
M accel/tcg/cputlb.c
A include/accel/tcg/iommu.h
M include/exec/exec-all.h
M system/physmem.c
Log Message:
-----------
physmem: Restrict TCG IOTLB code to TCG accel
Restrict iotlb_to_section(), address_space_translate_for_iotlb()
and memory_region_section_get_iotlb() to TCG. Declare them in
the new "accel/tcg/iommu.h" header. Declare iotlb_to_section()
using the MemoryRegionSection typedef.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250424202412.91612-12-phi...@linaro.org>
Commit: fe1a3ace13a8b53fc20c74fb7e3337f754396e6b
https://github.com/qemu/qemu/commit/fe1a3ace13a8b53fc20c74fb7e3337f754396e6b
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
A include/accel/tcg/probe.h
M include/exec/exec-all.h
M semihosting/uaccess.c
M target/arm/helper.c
M target/arm/ptw.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/sve_helper.c
M target/hexagon/mmvec/macros.h
M target/hexagon/op_helper.c
M target/hppa/mem_helper.c
M target/hppa/op_helper.c
M target/i386/tcg/access.c
M target/i386/tcg/seg_helper.c
M target/i386/tcg/system/excp_helper.c
M target/mips/tcg/msa_helper.c
M target/ppc/mem_helper.c
M target/riscv/op_helper.c
M target/riscv/vector_helper.c
M target/s390x/tcg/mem_helper.c
M target/xtensa/mmu_helper.c
Log Message:
-----------
accel/tcg: Extract probe API out of 'exec/exec-all.h'
Declare probe methods in "accel/tcg/probe.h" to emphasize
they are specific to TCG accelerator.
Suggested-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.caveayl...@nutanix.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250424202412.91612-13-phi...@linaro.org>
Commit: 84307cd6027c4602913177ff09aeefa4743b7234
https://github.com/qemu/qemu/commit/84307cd6027c4602913177ff09aeefa4743b7234
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M MAINTAINERS
M accel/hvf/hvf-accel-ops.c
M accel/tcg/cputlb.c
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
M bsd-user/main.c
M bsd-user/qemu.h
M hw/ppc/spapr_nested.c
M hw/riscv/riscv-iommu-sys.c
M hw/sh4/sh7750.c
R include/exec/exec-all.h
M include/system/ram_addr.h
M linux-user/main.c
M linux-user/user-internals.h
M semihosting/uaccess.c
M system/physmem.c
M target/alpha/cpu.c
M target/alpha/fpu_helper.c
M target/alpha/int_helper.c
M target/alpha/mem_helper.c
M target/alpha/translate.c
M target/alpha/vax_helper.c
M target/arm/cpu.c
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/ptw.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/mve_helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/pauth_helper.c
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/tlb_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.h
M target/avr/cpu.c
M target/avr/translate.c
M target/hexagon/cpu.c
M target/hexagon/op_helper.c
M target/hppa/cpu.c
M target/hppa/fpu_helper.c
M target/hppa/helper.c
M target/hppa/mem_helper.c
M target/hppa/op_helper.c
M target/hppa/sys_helper.c
M target/hppa/translate.c
M target/i386/tcg/access.c
M target/i386/tcg/excp_helper.c
M target/i386/tcg/helper-tcg.h
M target/i386/tcg/int_helper.c
M target/i386/tcg/mem_helper.c
M target/i386/tcg/mpx_helper.c
M target/i386/tcg/seg_helper.c
M target/i386/tcg/system/bpt_helper.c
M target/i386/tcg/translate.c
M target/i386/tcg/user/excp_helper.c
M target/i386/tcg/user/seg_helper.c
M target/loongarch/cpu.c
M target/loongarch/tcg/fpu_helper.c
M target/loongarch/tcg/iocsr_helper.c
M target/loongarch/tcg/op_helper.c
M target/loongarch/tcg/tlb_helper.c
M target/loongarch/tcg/vec_helper.c
M target/m68k/fpu_helper.c
M target/m68k/helper.c
M target/m68k/op_helper.c
M target/m68k/translate.c
M target/microblaze/cpu.c
M target/microblaze/op_helper.c
M target/microblaze/translate.c
M target/mips/cpu.c
M target/mips/system/physaddr.c
M target/mips/tcg/exception.c
M target/mips/tcg/fpu_helper.c
M target/mips/tcg/ldst_helper.c
M target/mips/tcg/msa_helper.c
M target/mips/tcg/op_helper.c
M target/mips/tcg/system/special_helper.c
M target/mips/tcg/system/tlb_helper.c
M target/openrisc/cpu.c
M target/openrisc/exception.c
M target/openrisc/exception_helper.c
M target/openrisc/fpu_helper.c
M target/openrisc/interrupt.c
M target/openrisc/interrupt_helper.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/machine.c
M target/ppc/mem_helper.c
M target/ppc/misc_helper.c
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash64.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/power8-pmu.c
M target/ppc/tcg-excp_helper.c
M target/ppc/timebase_helper.c
M target/ppc/translate.c
M target/ppc/user_only_helper.c
M target/riscv/cpu.c
M target/riscv/cpu_helper.c
M target/riscv/crypto_helper.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/fpu_helper.c
M target/riscv/m128_helper.c
M target/riscv/op_helper.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
M target/riscv/vcrypto_helper.c
M target/riscv/vector_helper.c
M target/riscv/zce_helper.c
M target/rx/op_helper.c
M target/rx/translate.c
M target/s390x/interrupt.c
M target/s390x/mmu_helper.c
M target/s390x/sigp.c
M target/s390x/tcg/cc_helper.c
M target/s390x/tcg/crypto_helper.c
M target/s390x/tcg/excp_helper.c
M target/s390x/tcg/fpu_helper.c
M target/s390x/tcg/int_helper.c
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/misc_helper.c
M target/s390x/tcg/translate.c
M target/s390x/tcg/vec_fpu_helper.c
M target/s390x/tcg/vec_helper.c
M target/sh4/cpu.c
M target/sh4/helper.c
M target/sh4/op_helper.c
M target/sh4/translate.c
M target/sparc/cpu.c
M target/sparc/fop_helper.c
M target/sparc/helper.c
M target/sparc/ldst_helper.c
M target/sparc/machine.c
M target/sparc/translate.c
M target/sparc/win_helper.c
M target/tricore/cpu.c
M target/tricore/op_helper.c
M target/tricore/translate.c
M target/xtensa/dbg_helper.c
M target/xtensa/exc_helper.c
M target/xtensa/fpu_helper.c
M target/xtensa/mmu_helper.c
M target/xtensa/op_helper.c
M target/xtensa/translate.c
M target/xtensa/win_helper.c
Log Message:
-----------
include: Remove 'exec/exec-all.h'
"exec/exec-all.h" is now fully empty, let's remove it.
Mechanical change running:
$ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h)
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.caveayl...@nutanix.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250424202412.91612-14-phi...@linaro.org>
Commit: 9a1e3713232f9641353e63fd279eb83cc723faf2
https://github.com/qemu/qemu/commit/9a1e3713232f9641353e63fd279eb83cc723faf2
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Generalize fake_user_interrupt test
Test for the hook being present instead of ifdef TARGET_I386.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 81ef6a2295740c4b2de9db2f81ebb9ad346b8cfc
https://github.com/qemu/qemu/commit/81ef6a2295740c4b2de9db2f81ebb9ad346b8cfc
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Unconditionally use CPU_DUMP_CCOP in log_cpu_exec
This flag is only tested by target/i386, so including this
makes no functional change. This is similar to other places
like cpu-target.c which use CPU_DUMP_CCOP unconditionally.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 9181ab452893a3f45cdc0f6196fbb9e389a4e5cd
https://github.com/qemu/qemu/commit/9181ab452893a3f45cdc0f6196fbb9e389a4e5cd
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M include/accel/tcg/cpu-ops.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/tcg/cpu-v7m.c
M target/avr/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/tcg/tcg-cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
accel/tcg: Introduce TCGCPUOps.cpu_exec_reset
Initialize all instances with cpu_reset(), so that there
is no functional change.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: c2d5897d3b712402d9543570c550a40cc0836522
https://github.com/qemu/qemu/commit/c2d5897d3b712402d9543570c550a40cc0836522
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M target/i386/tcg/tcg-cpu.c
Log Message:
-----------
target/i386: Split out x86_cpu_exec_reset
Note that target/i386/cpu.h defines CPU_INTERRUPT_INIT
as CPU_INTERRUPT_RESET. Therefore we can handle the
new TCGCPUOps.cpu_exec_reset hook.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: a59a876999344be426144a3e6d163885220c1e93
https://github.com/qemu/qemu/commit/a59a876999344be426144a3e6d163885220c1e93
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M include/accel/tcg/cpu-ops.h
M target/alpha/cpu.c
M target/alpha/cpu.h
M target/arm/cpu.h
M target/arm/helper.c
M target/avr/cpu.c
M target/avr/cpu.h
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M target/hppa/cpu.c
M target/hppa/cpu.h
M target/i386/cpu.h
M target/i386/tcg/tcg-cpu.c
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/m68k/cpu.c
M target/m68k/cpu.h
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/mips/cpu.c
M target/mips/cpu.h
M target/openrisc/cpu.c
M target/openrisc/cpu.h
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/riscv/cpu.h
M target/rx/cpu.c
M target/rx/cpu.h
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/sh4/cpu.c
M target/sh4/cpu.h
M target/sparc/cpu.h
M target/tricore/cpu.c
M target/tricore/cpu.h
M target/xtensa/cpu.c
M target/xtensa/cpu.h
Log Message:
-----------
accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.h
For some targets, simply remove the local definition.
For other targets, move the inline definition out of line.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b6aeb8d243c5ab8b914b55f0036e8289a99322c8
https://github.com/qemu/qemu/commit/b6aeb8d243c5ab8b914b55f0036e8289a99322c8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M target/arm/helper.c
M target/arm/tcg/hflags.c
Log Message:
-----------
target/arm: Move cpu_get_tb_cpu_state to hflags.c
This is a tcg-specific function, so move it to a tcg file.
Also move mve_no_pred, a static function only used within
cpu_get_tb_cpu_state.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 9da84372c4e9efedc5326e71358197930ee06445
https://github.com/qemu/qemu/commit/9da84372c4e9efedc5326e71358197930ee06445
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M target/arm/internals.h
M target/arm/tcg-stubs.c
M target/arm/tcg/hflags.c
Log Message:
-----------
target/arm: Unexport assert_hflags_rebuild_correctly
This function is no longer used outside of hflags.c.
We can remove the stub as well.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 5b1c93be57ce6364eb7bbaaab6ecbf2b1d5d979e
https://github.com/qemu/qemu/commit/5b1c93be57ce6364eb7bbaaab6ecbf2b1d5d979e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c
This function is only relevant to tcg.
Move it to a tcg-specific file.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 4759aae43235cd00e1c9b67ff5bd920db89fddc5
https://github.com/qemu/qemu/commit/4759aae43235cd00e1c9b67ff5bd920db89fddc5
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/translate-all.c
M include/accel/tcg/cpu-ops.h
A include/accel/tcg/tb-cpu-state.h
M target/alpha/cpu.c
M target/arm/tcg/hflags.c
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/helper_regs.c
M target/riscv/tcg/tcg-cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state
Combine 3 different pointer returns into one structure return.
Include a cflags field in TCGTBCPUState, not filled in by
cpu_get_tb_cpu_state, but used by all callers. This fills
a hole in the structure and is useful in some subroutines.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: c37f8978d9e23066132a0717b8cb4ed37a0cbd96
https://github.com/qemu/qemu/commit/c37f8978d9e23066132a0717b8cb4ed37a0cbd96
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/translate-all.c
M include/accel/tcg/cpu-ops.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/internals.h
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/hflags.c
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/ppc/helper_regs.c
M target/ppc/internal.h
M target/riscv/tcg/tcg-cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps
Move the global function name to a hook on TCGCPUOps.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b46357db323bf21d2816970a2f15540dfff84ecc
https://github.com/qemu/qemu/commit/b46357db323bf21d2816970a2f15540dfff84ecc
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Pass TCGTBCPUState to tb_lookup
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 088caf3de4e48e70d6716195afc0e47edd823ac0
https://github.com/qemu/qemu/commit/088caf3de4e48e70d6716195afc0e47edd823ac0
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Pass TCGTBCPUState to tb_htable_lookup
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: cec7176a23bfb46ce54481f278e235f58eb9c456
https://github.com/qemu/qemu/commit/cec7176a23bfb46ce54481f278e235f58eb9c456
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Use TCGTBCPUState in struct tb_desc
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 18a77386f15d4fed13b3d162e73e784e1da1f862
https://github.com/qemu/qemu/commit/18a77386f15d4fed13b3d162e73e784e1da1f862
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/internal-common.h
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Pass TCGTBCPUState to tb_gen_code
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 0baf907b718e1602383b973de7822c25db4c4a36
https://github.com/qemu/qemu/commit/0baf907b718e1602383b973de7822c25db4c4a36
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/user-exec.c
M include/accel/tcg/cpu-ldst.h
A include/accel/tcg/helper-retaddr.h
M target/arm/tcg/helper-a64.c
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/ppc/mem_helper.c
M target/s390x/tcg/mem_helper.c
Log Message:
-----------
accel/tcg: Split out accel/tcg/helper-retaddr.h
Move set_helper_retaddr and clear_helper_retaddr
to a new header file.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 5e5a9aea793cfd67541153105b6046436f6ae4a8
https://github.com/qemu/qemu/commit/5e5a9aea793cfd67541153105b6046436f6ae4a8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/meson.build
Log Message:
-----------
accel/tcg: Compile cpu-exec.c twice
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 28502121be7b1422af55bbed6f65a273b889ef01
https://github.com/qemu/qemu/commit/28502121be7b1422af55bbed6f65a273b889ef01
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M include/qemu/target-info-impl.h
M include/qemu/target-info.h
M system/vl.c
M target-info-stub.c
M target-info.c
Log Message:
-----------
system/vl: Filter machine list available for a particular target binary
Binaries can register a QOM type to filter their machines
by filling their TargetInfo::machine_typename field.
This can be used by example by main() -> machine_help_func()
to filter the machines list.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b113dfa081a6a7e061551a70e6ede7af0941a845
https://github.com/qemu/qemu/commit/b113dfa081a6a7e061551a70e6ede7af0941a845
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M include/qemu/target-info-impl.h
M target-info-stub.c
M target-info.c
Log Message:
-----------
qemu/target_info: Add %target_cpu_type field to TargetInfo
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: c1be135ad5b124b08715ca836b95b738c6b9d7d4
https://github.com/qemu/qemu/commit/c1be135ad5b124b08715ca836b95b738c6b9d7d4
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M include/qemu/target-info-impl.h
M include/qemu/target-info.h
M target-info-stub.c
M target-info.c
Log Message:
-----------
qemu: Introduce target_long_bits()
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: e1d8fabc20adb6a766773adb4a9b5bfe93e329bb
https://github.com/qemu/qemu/commit/e1d8fabc20adb6a766773adb4a9b5bfe93e329bb
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-01 (Thu, 01 May 2025)
Changed paths:
M accel/tcg/translate-all.c
M include/tcg/insn-start-words.h
M include/tcg/tcg-op.h
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M target/i386/helper.c
M target/openrisc/sys_helper.c
M tcg/perf.c
M tcg/tcg.c
Log Message:
-----------
tcg: Define INSN_START_WORDS as constant 3
Use the same value for all targets.
Rename TARGET_INSN_START_WORDS and do not depend on
TARGET_INSN_START_EXTRA_WORDS.
Remove TCGContext.insn_start_words.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 9401f91b9b0c46886388735b3f2033a9c254895a
https://github.com/qemu/qemu/commit/9401f91b9b0c46886388735b3f2033a9c254895a
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-01 (Thu, 01 May 2025)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Don't use TARGET_LONG_BITS in decode_sleb128
When we changed decode_sleb128 from target_long to
int64_t, we failed to adjust the shift limit.
Cc: qemu-sta...@nongnu.org
Fixes: c9ad8d27caa ("tcg: Widen gen_insn_data to uint64_t")
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: d2bbc0d6b90cd82b3cecb2d57bb317ba982a30a3
https://github.com/qemu/qemu/commit/d2bbc0d6b90cd82b3cecb2d57bb317ba982a30a3
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-01 (Thu, 01 May 2025)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Use target_long_bits() in translate-all.c
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b5dee28732209eaf93656807810c9c5340e907e1
https://github.com/qemu/qemu/commit/b5dee28732209eaf93656807810c9c5340e907e1
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-01 (Thu, 01 May 2025)
Changed paths:
M accel/tcg/meson.build
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Build translate-all.c twice
Remove lots and lots of unused headers.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 97f0d52435ec9da8fd58dc73b6765181fcb25965
https://github.com/qemu/qemu/commit/97f0d52435ec9da8fd58dc73b6765181fcb25965
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-01 (Thu, 01 May 2025)
Changed paths:
M accel/tcg/meson.build
M accel/tcg/tcg-all.c
Log Message:
-----------
accel/tcg: Build tcg-all.c twice
Remove some unused headers.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: d551b822f7ac329c763267659950992849d7e735
https://github.com/qemu/qemu/commit/d551b822f7ac329c763267659950992849d7e735
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/user-exec.c
M bsd-user/signal.c
M include/user/cpu_loop.h
M linux-user/signal.c
Log Message:
-----------
accel/tcg: Use vaddr in cpu_loop.h
Use vaddr instead of abi_ptr or target_ulong for a guest address.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 9b74d403b30e64256b4b94cbc01c76a0382ca5e8
https://github.com/qemu/qemu/commit/9b74d403b30e64256b4b94cbc01c76a0382ca5e8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/user-exec.c
M include/accel/tcg/cpu-ldst.h
Log Message:
-----------
accel/tcg: Move user-only tlb_vaddr_to_host out of line
At the same time, fix a mis-match between user and system
by using vaddr not abi_ptr for the address parameter.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: a21959a8a835783b556d4a1d18aaa2fad4b7ea62
https://github.com/qemu/qemu/commit/a21959a8a835783b556d4a1d18aaa2fad4b7ea62
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M include/accel/tcg/cpu-ldst.h
M include/accel/tcg/probe.h
Log Message:
-----------
accel/tcg: Move tlb_vaddr_to_host declaration to probe.h
This is a probing function, not a load/store function.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b5555a077f7a2e655b0a4aec9328d70497a7dd65
https://github.com/qemu/qemu/commit/b5555a077f7a2e655b0a4aec9328d70497a7dd65
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Use target_long_bits() in cputlb.c
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 4b2de658f13df52ccbf41c3399ab4f7adbcc6080
https://github.com/qemu/qemu/commit/4b2de658f13df52ccbf41c3399ab4f7adbcc6080
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/ldst_common.c.inc
Log Message:
-----------
accel/tcg: Use vaddr for plugin_{load,store}_cb
Avoid the use of abi_ptr within ldst_common.c.inc.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 0566f364f79c452af99f437a7784397b03775c72
https://github.com/qemu/qemu/commit/0566f364f79c452af99f437a7784397b03775c72
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/meson.build
Log Message:
-----------
accel/tcg: Build cputlb.c once
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 30da476066d6470e1064eb564e348af945a1a656
https://github.com/qemu/qemu/commit/30da476066d6470e1064eb564e348af945a1a656
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/user-exec.c
M bsd-user/main.c
M include/user/guest-host.h
M linux-user/main.c
Log Message:
-----------
include/user: Convert GUEST_ADDR_MAX to a variable
Remove GUEST_ADDR_MAX and add guest_addr_max.
Initialize it in *-user/main.c, after reserved_va.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 7804c84a56f9265813eb87db0bdae063279af030
https://github.com/qemu/qemu/commit/7804c84a56f9265813eb87db0bdae063279af030
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M include/user/guest-host.h
Log Message:
-----------
include/user: Use vaddr in guest-host.h
Replace abi_ptr and abi_ulong with vaddr.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 2c0b261fcd259f0e027633c744d279d255b4ff49
https://github.com/qemu/qemu/commit/2c0b261fcd259f0e027633c744d279d255b4ff49
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M include/accel/tcg/cpu-ops.h
M include/user/guest-host.h
M target/arm/cpu-param.h
M target/arm/cpu.c
M target/arm/cpu.h
Log Message:
-----------
accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addr
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 964080d3563f1211b70051c8ea5add752586da09
https://github.com/qemu/qemu/commit/964080d3563f1211b70051c8ea5add752586da09
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/user-exec.c
M include/user/page-protection.h
M target/arm/cpu.h
M target/arm/tcg/mte_helper.c
Log Message:
-----------
accel/tcg: Remove TARGET_PAGE_DATA_SIZE
This macro is used by only one target, and even then under
unusual conditions -- AArch64 with mmap's PROT_MTE flag.
Since page size for aarch64-linux-user is variable, the
per-page data size is also variable.
Since page_reset_target_data via target_munmap does not
have ready access to CPUState, simply pass in the size
from the first allocation and remember that.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 03c981e7d63eaa03e6b7c4b9ef59b45b0b985876
https://github.com/qemu/qemu/commit/03c981e7d63eaa03e6b7c4b9ef59b45b0b985876
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Avoid abi_ptr in user-exec.c
In page_dump/dump_region, use guest_addr_max to check the
size of the guest address space and size the output
appropriately. This will change output with small values
of -R reserved_va, but shouldn't affect anything else.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 768cb76d14f1a50c00d60fbb1d393996c76645d8
https://github.com/qemu/qemu/commit/768cb76d14f1a50c00d60fbb1d393996c76645d8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-05 (Mon, 05 May 2025)
Changed paths:
M accel/tcg/meson.build
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Build user-exec.c once
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 36ad84ecb26d6a28c78d079dc51063d972600592
https://github.com/qemu/qemu/commit/36ad84ecb26d6a28c78d079dc51063d972600592
Author: Bibo Mao <maob...@loongson.cn>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
M include/hw/intc/loongarch_ipi.h
Log Message:
-----------
hw/intc/loongarch_ipi: Add reset support
Add reset support with ipi object, register reset callback and clear
internal registers when virt machine resets.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Song Gao <gaos...@loongson.cn>
Commit: 86e4a64751a728aae24fa95d76d6c313aa82cf82
https://github.com/qemu/qemu/commit/86e4a64751a728aae24fa95d76d6c313aa82cf82
Author: Bibo Mao <maob...@loongson.cn>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/intc/loongarch_extioi_common.c
M include/hw/intc/loongarch_extioi_common.h
Log Message:
-----------
hw/intc/loongarch_extioi: Add reset support
Add reset support with extioi irqchip, and register reset callback
support with new API resettable_class_set_parent_phases(). Clear
internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Song Gao <gaos...@loongson.cn>
Commit: bba709ff694cc6f844ca32d333b6be7adc7bd6b4
https://github.com/qemu/qemu/commit/bba709ff694cc6f844ca32d333b6be7adc7bd6b4
Author: Bibo Mao <maob...@loongson.cn>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/intc/loongarch_extioi.c
M include/hw/intc/loongarch_extioi.h
Log Message:
-----------
hw/intc/loongarch_extioi: Replace legacy reset callback with new api
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object and then itself.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Song Gao <gaos...@loongson.cn>
Commit: 5101435e6d784c6d5bb267ca019b721a028dbc47
https://github.com/qemu/qemu/commit/5101435e6d784c6d5bb267ca019b721a028dbc47
Author: Bibo Mao <maob...@loongson.cn>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/intc/loongarch_pic_common.c
M include/hw/intc/loongarch_pic_common.h
Log Message:
-----------
hw/intc/loongarch_pch: Add reset support
Add reset support with LoongArch pci irqchip, and register reset
callback support with new API resettable_class_set_parent_phases().
Clear internal HW registers and SW state when virt machine resets.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Song Gao <gaos...@loongson.cn>
Commit: a41a74ca5323f4d30ac7eb48ec1d54a09fae5baa
https://github.com/qemu/qemu/commit/a41a74ca5323f4d30ac7eb48ec1d54a09fae5baa
Author: Bibo Mao <maob...@loongson.cn>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/intc/loongarch_pch_pic.c
M include/hw/intc/loongarch_pch_pic.h
Log Message:
-----------
hw/intc/loongarch_pch: Replace legacy reset callback with new api
Replace legacy reset callback register device_class_set_legacy_reset()
with new function resettable_class_set_parent_phases(). With new API,
it will call reset callback of parent object.
The internal state has been cleared in parent object
LOONGARCH_PIC_COMMON, here parent_phases.hold() is directly called.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Song Gao <gaos...@loongson.cn>
Commit: 73047c825e25a18127dddb89eff0c0bf97a26aed
https://github.com/qemu/qemu/commit/73047c825e25a18127dddb89eff0c0bf97a26aed
Author: Bibo Mao <maob...@loongson.cn>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/loongarch/boot.c
M tests/tcg/loongarch64/system/kernel.ld
Log Message:
-----------
hw/loongarch/virt: Get physical entry address with elf file
With load_elf() api, image load low address and high address is converted
to physical address if parameter translate_fn is provided. However
executing entry address is still virtual address. Here convert entry
address into physical address, since MMU is disabled when system power on,
the first PC instruction should be physical address.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Tested-by: Song Gao <gaos...@loongson.cn>
Commit: d0897c6970b3717fe707c8d5a807fe2baf836ddd
https://github.com/qemu/qemu/commit/d0897c6970b3717fe707c8d5a807fe2baf836ddd
Author: Bibo Mao <maob...@loongson.cn>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/loongarch/virt-acpi-build.c
Log Message:
-----------
hw/loongarch/virt: Replace RSDT with XSDT table
XSDT table is introduced in ACPI Specification 5.0, it supports 64-bit
address in the table. There is LoongArch system support from ACPI
Specification 6.4 and later, XSDT is supported by LoongArch system.
Here replace RSDT with XSDT table.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Song Gao <gaos...@loongson.cn>
Commit: 445c9c645befa759b95b21108447704ab328ae03
https://github.com/qemu/qemu/commit/445c9c645befa759b95b21108447704ab328ae03
Author: Bibo Mao <maob...@loongson.cn>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/loongarch/virt.c
Log Message:
-----------
hw/loongarch/virt: Allow user to customize OEM ID and OEM table ID
On LoongArch virt machine, the default OEM ID and OEM table ID is
"BOCHS " and "BXPC ". Here property x-oem-id and x-oem-table-id
is added on virt machine to set customized OEM ID and OEM table ID.
Signed-off-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Song Gao <gaos...@loongson.cn>
Commit: 7cef6d686309e2792186504ae17cf4f3eb57ef68
https://github.com/qemu/qemu/commit/7cef6d686309e2792186504ae17cf4f3eb57ef68
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M MAINTAINERS
M accel/hvf/hvf-accel-ops.c
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/internal-common.h
R accel/tcg/internal-target.h
M accel/tcg/ldst_common.c.inc
M accel/tcg/meson.build
M accel/tcg/tb-hash.h
M accel/tcg/tb-internal.h
M accel/tcg/tb-maint.c
M accel/tcg/tcg-all.c
M accel/tcg/tlb-bounds.h
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
M bsd-user/main.c
M bsd-user/qemu.h
M bsd-user/signal.c
M hw/ppc/spapr_nested.c
M hw/riscv/riscv-iommu-sys.c
M hw/sh4/sh7750.c
M include/accel/tcg/cpu-ldst.h
M include/accel/tcg/cpu-ops.h
M include/accel/tcg/getpc.h
A include/accel/tcg/helper-retaddr.h
A include/accel/tcg/iommu.h
A include/accel/tcg/probe.h
A include/accel/tcg/tb-cpu-state.h
R include/exec/exec-all.h
M include/exec/helper-proto-common.h
M include/exec/poison.h
M include/exec/translation-block.h
M include/qemu/target-info-impl.h
M include/qemu/target-info.h
M include/system/ram_addr.h
M include/tcg/insn-start-words.h
M include/tcg/tcg-op.h
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M include/user/cpu_loop.h
M include/user/guest-host.h
M include/user/page-protection.h
M linux-user/elfload.c
M linux-user/main.c
M linux-user/signal.c
M linux-user/syscall.c
M linux-user/user-internals.h
M semihosting/uaccess.c
M system/physmem.c
M system/vl.c
M target-info-stub.c
M target-info.c
M target/alpha/cpu.c
M target/alpha/cpu.h
M target/alpha/fpu_helper.c
M target/alpha/int_helper.c
M target/alpha/mem_helper.c
M target/alpha/translate.c
M target/alpha/vax_helper.c
M target/arm/cpu-param.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg-stubs.c
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/hflags.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/mve_helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/pauth_helper.c
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/tlb_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.h
M target/avr/cpu.c
M target/avr/cpu.h
M target/avr/helper.c
M target/avr/translate.c
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M target/hexagon/mmvec/macros.h
M target/hexagon/op_helper.c
M target/hppa/cpu.c
M target/hppa/cpu.h
M target/hppa/fpu_helper.c
M target/hppa/helper.c
M target/hppa/mem_helper.c
M target/hppa/op_helper.c
M target/hppa/sys_helper.c
M target/hppa/translate.c
M target/i386/cpu.h
M target/i386/helper.c
M target/i386/tcg/access.c
M target/i386/tcg/excp_helper.c
M target/i386/tcg/helper-tcg.h
M target/i386/tcg/int_helper.c
M target/i386/tcg/mem_helper.c
M target/i386/tcg/mpx_helper.c
M target/i386/tcg/seg_helper.c
M target/i386/tcg/system/bpt_helper.c
M target/i386/tcg/system/excp_helper.c
M target/i386/tcg/tcg-cpu.c
M target/i386/tcg/translate.c
M target/i386/tcg/user/excp_helper.c
M target/i386/tcg/user/seg_helper.c
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/tcg/fpu_helper.c
M target/loongarch/tcg/iocsr_helper.c
M target/loongarch/tcg/op_helper.c
M target/loongarch/tcg/tlb_helper.c
M target/loongarch/tcg/vec_helper.c
M target/m68k/cpu.c
M target/m68k/cpu.h
M target/m68k/fpu_helper.c
M target/m68k/helper.c
M target/m68k/op_helper.c
M target/m68k/translate.c
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/op_helper.c
M target/microblaze/translate.c
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/system/physaddr.c
M target/mips/tcg/exception.c
M target/mips/tcg/fpu_helper.c
M target/mips/tcg/ldst_helper.c
M target/mips/tcg/msa_helper.c
M target/mips/tcg/op_helper.c
M target/mips/tcg/system/special_helper.c
M target/mips/tcg/system/tlb_helper.c
M target/openrisc/cpu.c
M target/openrisc/cpu.h
M target/openrisc/exception.c
M target/openrisc/exception_helper.c
M target/openrisc/fpu_helper.c
M target/openrisc/interrupt.c
M target/openrisc/interrupt_helper.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper_regs.c
M target/ppc/internal.h
M target/ppc/machine.c
M target/ppc/mem_helper.c
M target/ppc/misc_helper.c
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash64.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/power8-pmu.c
M target/ppc/tcg-excp_helper.c
M target/ppc/timebase_helper.c
M target/ppc/translate.c
M target/ppc/user_only_helper.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/crypto_helper.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/fpu_helper.c
M target/riscv/m128_helper.c
M target/riscv/op_helper.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
M target/riscv/vcrypto_helper.c
M target/riscv/vector_helper.c
M target/riscv/zce_helper.c
M target/rx/cpu.c
M target/rx/cpu.h
M target/rx/op_helper.c
M target/rx/translate.c
M target/s390x/cpu.c
M target/s390x/cpu.h
M target/s390x/interrupt.c
M target/s390x/mmu_helper.c
M target/s390x/sigp.c
M target/s390x/tcg/cc_helper.c
M target/s390x/tcg/crypto_helper.c
M target/s390x/tcg/excp_helper.c
M target/s390x/tcg/fpu_helper.c
M target/s390x/tcg/int_helper.c
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/misc_helper.c
M target/s390x/tcg/translate.c
M target/s390x/tcg/vec_fpu_helper.c
M target/s390x/tcg/vec_helper.c
M target/sh4/cpu.c
M target/sh4/cpu.h
M target/sh4/helper.c
M target/sh4/op_helper.c
M target/sh4/translate.c
M target/sparc/cpu.c
M target/sparc/cpu.h
M target/sparc/fop_helper.c
M target/sparc/helper.c
M target/sparc/ldst_helper.c
M target/sparc/machine.c
M target/sparc/translate.c
M target/sparc/win_helper.c
M target/tricore/cpu.c
M target/tricore/cpu.h
M target/tricore/op_helper.c
M target/tricore/translate.c
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/dbg_helper.c
M target/xtensa/exc_helper.c
M target/xtensa/fpu_helper.c
M target/xtensa/mmu_helper.c
M target/xtensa/op_helper.c
M target/xtensa/translate.c
M target/xtensa/win_helper.c
M tcg/perf.c
M tcg/tcg.c
Log Message:
-----------
Merge tag 'pull-tcg-20250501-v2' of https://gitlab.com/rth7680/qemu into
staging
include: Remove 'exec/exec-all.h'
accel/tcg: Build tb-maint.c twice
accel/tcg: Build cpu-exec.c twice
accel/tcg: Build translate-all.c twice
accel/tcg: Build tcg-all.c twice
accel/tcg: Build cputlb.c once
accel/tcg: Build user-exec.c once
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#
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# hP2YiNVfI+c9e3x3Bivx++9YUYfynWyPO774axnyhqYg3cJONWs+4HJ/MQHNSG/G
# qT+7EihGIDwnjWxTvu9wp5XucvaGKBqGEQ2IZrr0JBEnvrrpuhiauqP7Bjb37eAj
# kxw50NUxxz4wqk5Ql4UZyJ0h1peH5PFNr9uozhr6HJSEET7GxPMfUy611jAa/eXc
# MDkiDwd+0JGSKkMSQaCocMO2vL4OQGr3sTBNHQZ/RalEdMp+AJiQgjJ0fFfCInwK
# 4w8/8we8MKUBIwTn5kTUBjPrI7nlhJk5mFm5aV7fNvSClGf5Yb62SfPesQKm5qkE
# z3aApA==
# =Lpyu
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 05 May 2025 15:47:34 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.hender...@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.hender...@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20250501-v2' of https://gitlab.com/rth7680/qemu: (59 commits)
accel/tcg: Build user-exec.c once
accel/tcg: Avoid abi_ptr in user-exec.c
accel/tcg: Remove TARGET_PAGE_DATA_SIZE
accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addr
include/user: Use vaddr in guest-host.h
include/user: Convert GUEST_ADDR_MAX to a variable
accel/tcg: Build cputlb.c once
accel/tcg: Use vaddr for plugin_{load,store}_cb
accel/tcg: Use target_long_bits() in cputlb.c
accel/tcg: Move tlb_vaddr_to_host declaration to probe.h
accel/tcg: Move user-only tlb_vaddr_to_host out of line
accel/tcg: Use vaddr in cpu_loop.h
accel/tcg: Build tcg-all.c twice
accel/tcg: Build translate-all.c twice
accel/tcg: Use target_long_bits() in translate-all.c
accel/tcg: Don't use TARGET_LONG_BITS in decode_sleb128
tcg: Define INSN_START_WORDS as constant 3
qemu: Introduce target_long_bits()
qemu/target_info: Add %target_cpu_type field to TargetInfo
system/vl: Filter machine list available for a particular target binary
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: c5e2c4042e3c50b96cc5eaa9683325c5a96913b0
https://github.com/qemu/qemu/commit/c5e2c4042e3c50b96cc5eaa9683325c5a96913b0
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-06 (Tue, 06 May 2025)
Changed paths:
M hw/intc/loongarch_extioi.c
M hw/intc/loongarch_extioi_common.c
M hw/intc/loongarch_ipi.c
M hw/intc/loongarch_pch_pic.c
M hw/intc/loongarch_pic_common.c
M hw/loongarch/boot.c
M hw/loongarch/virt-acpi-build.c
M hw/loongarch/virt.c
M include/hw/intc/loongarch_extioi.h
M include/hw/intc/loongarch_extioi_common.h
M include/hw/intc/loongarch_ipi.h
M include/hw/intc/loongarch_pch_pic.h
M include/hw/intc/loongarch_pic_common.h
M tests/tcg/loongarch64/system/kernel.ld
Log Message:
-----------
Merge tag 'pull-loongarch-20250506' of https://github.com/bibo-mao/qemu into
staging
loongarch queue
# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCaBljTgAKCRAfewwSUazn
# 0cSzAPoCbqppm5lUPgFAacD4m1sUI6jLk5pJGMsQTQHkMZ34yQD7BswZhMWPL44Z
# LmrZgO7NfqAv96AF1mpRawV9ZXSOGAQ=
# =3itp
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 05 May 2025 21:18:06 EDT
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <maob...@loongson.cn>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20250506' of https://github.com/bibo-mao/qemu:
hw/loongarch/virt: Allow user to customize OEM ID and OEM table ID
hw/loongarch/virt: Replace RSDT with XSDT table
hw/loongarch/virt: Get physical entry address with elf file
hw/intc/loongarch_pch: Replace legacy reset callback with new api
hw/intc/loongarch_pch: Add reset support
hw/intc/loongarch_extioi: Replace legacy reset callback with new api
hw/intc/loongarch_extioi: Add reset support
hw/intc/loongarch_ipi: Add reset support
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Compare: https://github.com/qemu/qemu/compare/a9e0c9c0f14e...c5e2c4042e3c
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