Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: d75cdf6883fac728540798e42a8104d016ec762c
https://github.com/qemu/qemu/commit/d75cdf6883fac728540798e42a8104d016ec762c
Author: Fabiano Rosas <faro...@suse.de>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/ast2700-smc-test.c
Log Message:
-----------
tests/qtest/ast2700-smc-test: Fix leak
ASAN spotted a leak of the memory used to hold the tmp_path:
Direct leak of 35 byte(s) in 1 object(s) allocated from:
#0 0x55e29aa96da9 in malloc
../projects/compiler-rt/lib/asan/asan_malloc_linux.cpp:69:3
#1 0x7fe0cfb26518 in g_malloc ../glib/gmem.c:106
#2 0x7fe0cfb4146e in g_strconcat ../glib/gstrfuncs.c:629
#3 0x7fe0cfb0a78f in g_get_tmp_name ../glib/gfileutils.c:1742
#4 0x7fe0cfb0b00b in g_file_open_tmp ../glib/gfileutils.c:1802
#5 0x55e29ab53961 in test_ast2700_evb
../tests/qtest/ast2700-smc-test.c:20:10
#6 0x55e29ab53803 in main ../tests/qtest/ast2700-smc-test.c:65:5
#7 0x7fe0cf7bd24c in __libc_start_main ../csu/libc-start.c:308
#8 0x55e29a9f7759 in _start ../sysdeps/x86_64/start.S:120
Signed-off-by: Fabiano Rosas <faro...@suse.de>
Reviewed-by: Jamin Lin <jamin_...@aspeedtech.com>
Message-ID: <20250509175047.26066-1-faro...@suse.de>
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: d09c0939c97061fca0faa842184171f2f94b3339
https://github.com/qemu/qemu/commit/d09c0939c97061fca0faa842184171f2f94b3339
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed_smc-test.c
Log Message:
-----------
tests/qtest/aspeed_smc-test: Fix memory leaks
Link:
https://patchwork.kernel.org/project/qemu-devel/patch/20250509175047.26066-1-faro...@suse.de/
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Laurent Vivier <lviv...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250513080806.1005996-1-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: f05cc69c6ce0242e2eeae3cd1513454006b8f040
https://github.com/qemu/qemu/commit/f05cc69c6ce0242e2eeae3cd1513454006b8f040
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
hw/misc/aspeed_hace: Remove unused code for better readability
In the previous design of the hash framework, accumulative hashing was not
supported. To work around this limitation, commit 5cd7d85 introduced an
iov_cache array to store all the hash data from firmware.
Once the ASPEED HACE model collected all the data, it passed the iov_cache to
the hash API to calculate the final digest.
However, with commit e3c0752, the hash framework now supports accumulative
hashing. This allows us to refactor the ASPEED HACE model, removing redundant
logic and simplifying the implementation for better readability and
maintainability.
As a result, the iov_count variable is no longer needed—it was previously used
to track how many cached entries were used for hashing.
To maintain VMSTATE compatibility after removing this field, the VMSTATE_VERSION
is bumped to 2
This cleanup follows significant changes in commit 4c1d0af4a28d, making the
model more readable.
- Deleted "iov_cache" and "iov_count" from "AspeedHACEState".
- Removed "reconstruct_iov" function and related logic.
- Simplified "do_hash_operation" by eliminating redundant checks.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-2-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: c869da4edd7ad91975fd9887ec924ba621b3c7f8
https://github.com/qemu/qemu/commit/c869da4edd7ad91975fd9887ec924ba621b3c7f8
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Improve readability and consistency in variable naming
Currently, users define multiple local variables within different if-statements.
To improve readability and maintain consistency in variable naming, rename the
variables accordingly.
Introduced "sg_addr" to clearly indicate the scatter-gather mode buffer address.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-3-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: fb8e59abbe46957cd599bb9aa9221fad1e4e989e
https://github.com/qemu/qemu/commit/fb8e59abbe46957cd599bb9aa9221fad1e4e989e
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Ensure HASH_IRQ is always set to prevent firmware hang
Currently, if the program encounters an unsupported algorithm, it does not set
the HASH_IRQ bit in the status register and send an interrupt to indicate
command completion. As a result, the FW gets stuck waiting for a completion
signal from the HACE module.
Additionally, in do_hash_operation, if an error occurs within the conditional
statement, the HASH_IRQ bit is not set in the status register. This causes the
firmware to continuously send HASH commands, as it is unaware that the HACE
model has completed processing the command.
To fix this, the HASH_IRQ bit in the status register must always be set to
ensure that the firmware receives an interrupt from the HACE module, preventing
it from getting stuck or repeatedly sending HASH commands.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Fixes: c5475b3 ("hw: Model ASPEED's Hash and Crypto Engine")
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-4-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 7328c48b57c97e13863fdc3a76d6d9c8fe07d6ae
https://github.com/qemu/qemu/commit/7328c48b57c97e13863fdc3a76d6d9c8fe07d6ae
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Extract direct mode hash buffer setup into helper
function
To improve code readability and maintainability of do_hash_operation(), this
commit introduces a new helper function: hash_prepare_direct_iov().
This function encapsulates the logic for setting up the I/O vector (iov)
in direct mode (non-scatter-gather).
No functional changes are introduced.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-5-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 0b7dd5f9910c41d9a3faa51001b018a06f0c3ac7
https://github.com/qemu/qemu/commit/0b7dd5f9910c41d9a3faa51001b018a06f0c3ac7
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Extract SG-mode hash buffer setup into helper function
To improve code readability and maintainability of do_hash_operation(), this
commit introduces a new helper function: hash_prepare_sg_iov().
This function handles scatter-gather (SG) mode setup, including SG list
parsing, address mapping, and optional accumulation mode support with
padding detection.
No functional changes are introduced.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-6-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 047941978508e68215d01cc0e3e5408c430e9e9f
https://github.com/qemu/qemu/commit/047941978508e68215d01cc0e3e5408c430e9e9f
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Extract digest write and iov unmap into helper function
To improve code readability and maintainability of do_hash_operation(), this
commit introduces a new helper function: hash_write_digest_and_unmap_iov().
The helper consolidates the final digest writeback and subsequent unmapping of
the I/O vectors into a single routine.
No functional changes are introduced.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-7-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 02c4c448460e1370f767c56749a1756a5c4dcc3a
https://github.com/qemu/qemu/commit/02c4c448460e1370f767c56749a1756a5c4dcc3a
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Extract non-accumulation hash execution into helper
function
To improve code readability and maintainability of do_hash_operation(), this
commit introduces a new helper function: hash_execute_non_acc_mode().
The helper encapsulate the hashing logic for non-accumulation mode.
No functional changes are introduced.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-8-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: b9ccbe212e2443294dd636cb17b4e436db8774a7
https://github.com/qemu/qemu/commit/b9ccbe212e2443294dd636cb17b4e436db8774a7
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Extract accumulation-mode hash execution into helper
function
To improve code readability and maintainability of do_hash_operation(), this
commit introduces a new helper function: hash_execute_acc_mode().
This function encapsulates the full flow for accumulation mode, including
context initialization, update, conditional finalization, and digest writeback
with I/O vector unmapping.
No functional changes are introduced.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-9-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: c6c5fc5ab04533a22be11f377aa67d46e47056bf
https://github.com/qemu/qemu/commit/c6c5fc5ab04533a22be11f377aa67d46e47056bf
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Introduce 64-bit hash source address helper function
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DRAM
address space is also 64-bit. To support future AST2700 updates, the source
hash buffer address data type is being updated to 64-bit.
Introduces the "hash_get_source_addr()" helper function to extract the source
hash
buffer address.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-10-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 973fab3b3099aa5f6a4510c4da03056d6baf09a7
https://github.com/qemu/qemu/commit/973fab3b3099aa5f6a4510c4da03056d6baf09a7
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit
hash digest address helper
Renaming R_HASH_DEST to R_HASH_DIGEST for better semantic clarity.
The AST2700 CPU, based on the Cortex-A35, features a 64-bit DRAM address space.
To prepare for future AST2700 support, this change introduces a new helper
function hash_get_digest_addr() to encapsulate digest address extraction logic
and improve code readability.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-11-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 7b4e588000699701f5906746d1b5b845391705e6
https://github.com/qemu/qemu/commit/7b4e588000699701f5906746d1b5b845391705e6
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Support accumulative mode for direct access mode
Enable accumulative mode for direct access mode operations. In direct access
mode, only a single source buffer is used, so the "iovec" count is set to 1.
If "acc_mode" is enabled:
1. Accumulate "total_req_len" with the current request length ("plen").
2. Check for padding and determine whether this is the final request.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-12-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 89d2a9f3f7564c9421d61153bbf7e24af95d34ee
https://github.com/qemu/qemu/commit/89d2a9f3f7564c9421d61153bbf7e24af95d34ee
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
hw/misc/aspeed_hace: Move register size to instance class and dynamically
allocate regs
Dynamically allocate the register array by removing the hardcoded
ASPEED_HACE_NR_REGS macro.
To support different register sizes across SoC variants, introduce a new
"nr_regs" class attribute and replace the static "regs" array with dynamically
allocated memory.
Add a new "aspeed_hace_unrealize" function to properly free the allocated "regs"
memory during device cleanup.
Remove the bounds checking in the MMIO read/write handlers since the
MemoryRegion size now matches the (register array size << 2).
This commit updates the VMState fields accordingly. The VMState version was
already bumped in a previous patch of this series, so no further version change
is needed.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-13-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 6262c8addc8ed586dfa5f11606f1598fca45b3eb
https://github.com/qemu/qemu/commit/6262c8addc8ed586dfa5f11606f1598fca45b3eb
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit
addresses
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DIGEST_HI storing bits
[63:32] and R_HASH_DIGEST storing bits [31:0]. The HMAC key buffer address is
also
64-bit, with R_HASH_KEY_BUFF_HI storing bits [63:32] and R_HASH_KEY_BUFF storing
bits [31:0].
The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM addressable range
from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this range fits within 34 bits, only
bits [33:0] are needed to store the DRAM offset. To optimize address storage,
the high physical address bits [1:0] of the source, digest and key buffer
addresses are stored as dram_offset bits [33:32].
To achieve this, a src_hi_mask with a mask value of 0x3 is introduced, ensuring
that src_addr_hi consists of bits [1:0]. The final src_addr is computed as
(src_addr_hi[1:0] << 32) | src_addr[31:0], representing the DRAM offset within
bits [33:0].
Similarly, a dest_hi_mask with a mask value of 0x3 is introduced to ensure that
dest_addr_hi consists of bits [1:0]. The final dest_addr is calculated as
(dest_addr_hi[1:0] << 32) | dest_addr[31:0], representing the DRAM offset within
bits [33:0].
Additionally, a key_hi_mask with a mask value of 0x3 is introduced to ensure
that key_buf_addr_hi consists of bits [1:0]. The final key_buf_addr is
determined as (key_buf_addr_hi[1:0] << 32) | key_buf_addr[31:0], representing
the DRAM offset within bits [33:0].
This approach eliminates the need to reduce the high part of the DRAM physical
address for DMA operations. Previously, this was calculated as
(high physical address bits [7:0] - 4), since the DRAM start address is
0x4_00000000, making the high part address [7:0] - 4.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-14-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 7e65aa39b37cb189c4d0bc923d4d778bdd626f4b
https://github.com/qemu/qemu/commit/7e65aa39b37cb189c4d0bc923d4d778bdd626f4b
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
hw/misc/aspeed_hace: Support DMA 64 bits dram address
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits
[63:32] and R_HASH_DEST storing bits [31:0].
To maintain compatibility with older SoCs such as the AST2600, the AST2700 HW
automatically set bit 34 of the 64-bit sg_addr. As a result, the firmware
only needs to provide a 32-bit sg_addr containing bits [31:0]. This is
sufficient for the AST2700, as it uses a DRAM offset rather than a DRAM
address.
Introduce a has_dma64 class attribute and set it to true for the AST2700.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-15-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 555167a8fde2bf6c27d0df035324743ed5bfbb0d
https://github.com/qemu/qemu/commit/555167a8fde2bf6c27d0df035324743ed5bfbb0d
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
M hw/misc/trace-events
Log Message:
-----------
hw/misc/aspeed_hace: Add trace-events for better debugging
Introduced "trace_aspeed_hace_hash_addr", "trace_aspeed_hace_hash_sg",
"trace_aspeed_hace_read", "trace_aspeed_hace_hash_execute_acc_mode",
and "trace_aspeed_hace_write" trace events.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-16-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 22370d29e83753e4072457541ab59189edcd3947
https://github.com/qemu/qemu/commit/22370d29e83753e4072457541ab59189edcd3947
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/misc/aspeed_hace.c
M hw/misc/trace-events
Log Message:
-----------
hw/misc/aspeed_hace: Support to dump plaintext and digest for better debugging
1. Added "hace_hexdump()" to dump a contiguous buffer using qemu_hexdump.
2. Added "hace_iov_hexdump()" to flatten and dump scatter-gather source vectors.
3. Introduced a new trace event: "aspeed_hace_hexdump".
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-17-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 408326af1f05776eae0f4fc91dcf643b54f9240c
https://github.com/qemu/qemu/commit/408326af1f05776eae0f4fc91dcf643b54f9240c
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest: Reorder aspeed test list
Reordered the aspeed test list to keep the alphabetical order.
No functional changes in test behavior.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-18-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 70985b0ea776e0cd7d7ab2a173d9d35d31e8c21f
https://github.com/qemu/qemu/commit/70985b0ea776e0cd7d7ab2a173d9d35d31e8c21f
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
A tests/qtest/aspeed-hace-utils.c
A tests/qtest/aspeed-hace-utils.h
M tests/qtest/aspeed_hace-test.c
M tests/qtest/meson.build
Log Message:
-----------
test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases
The test cases for the ASPEED HACE model were originally placed in
aspeed_hace-test.c. However, this test file only supports ARM32. To enable
compatibility with all ASPEED SoCs, including the AST2700, which uses the
AArch64 architecture, this update introduces a new source file,
aspeed-hace-utils.c.
All common APIs and test cases have been moved from aspeed_hace-test.c to
aspeed-hace-utils.c to facilitate reuse across different ASPEED SoCs.
As a result, these test cases can now be reused for AST2700 and future ASPEED
SoC testing.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-19-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 33627ab237168fa624435eb8ae87f82a2ba9d7f5
https://github.com/qemu/qemu/commit/33627ab237168fa624435eb8ae87f82a2ba9d7f5
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed-hace-utils.c
Log Message:
-----------
test/qtest/hace: Specify explicit array sizes for test vectors and hash
results
To enhance code readability and prevent potential buffer overflows or unintended
size assumptions, this commit updates all fixed-size array declarations to use
explicit array sizes.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-20-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: a3e7f6d05d8bf38b0337fabc438d32c46948ccff
https://github.com/qemu/qemu/commit/a3e7f6d05d8bf38b0337fabc438d32c46948ccff
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed-hace-utils.c
Log Message:
-----------
test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations
The digest_addr is set to "src_addr + 0x1000000", where src_addr is the DRAM
base address. However, the value 0x1000000 (16MB) is too large because the
AST1030 does not support DRAM, and its SRAM size is only 768KB.
A range size of 0x10000 (64KB) is sufficient for HACE test cases, as the test
vector size does not exceed 64KB.
Updates:
1. Direct Access Mode
Update digest_addr to "src_addr + 0x10000" in the following functions:
aspeed_test_md5
aspeed_test_sha256
aspeed_test_sha512
2. Scatter-Gather (SG) Mode
Update source address for different SG buffer addresses in the following
functions:
src_addr1 = src_addr + 0x10000
src_addr2 = src_addr + 0x20000
src_addr3 = src_addr + 0x30000
digest_addr = src_addr + 0x40000
aspeed_test_sha256_sg
aspeed_test_sha512_sg
3. ACC Mode Update
Update the SG List start address: src_addr + 0x10000
Update the SG List buffer size to 0x30000 (192KB).
buffer_addr = src_addr + 0x10000
digest_addr = src_addr + 0x40000
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-21-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 3c13be86ba181faea21a1b4f66f54df5328574f7
https://github.com/qemu/qemu/commit/3c13be86ba181faea21a1b4f66f54df5328574f7
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed-hace-utils.c
M tests/qtest/aspeed-hace-utils.h
Log Message:
-----------
test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model
Introduced SHA-384 test functions to verify hashing operations.
Extended support for scatter-gather ("_sg") and accumulation ("_accum") tests.
Updated test result vectors for SHA-384 validation.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-22-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: adf2fb3951625dfba7ff95433c82a449e464a578
https://github.com/qemu/qemu/commit/adf2fb3951625dfba7ff95433c82a449e464a578
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed_hace-test.c
Log Message:
-----------
test/qtest/hace: Add SHA-384 tests for AST2600
Introduced "test_sha384_ast2600" to validate SHA-384 hashing.
Added "test_sha384_sg_ast2600" for scatter-gather SHA-384 verification.
Implemented "test_sha384_accum_ast2600" to test SHA-384 accumulation.
Registered new test cases in "main" to ensure execution.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-23-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 4f4e25507de719605936c955df3a5a5c560c9986
https://github.com/qemu/qemu/commit/4f4e25507de719605936c955df3a5a5c560c9986
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed_hace-test.c
Log Message:
-----------
test/qtest/hace: Add tests for AST1030
The HACE model in AST2600 and AST1030 is identical. Referencing the AST2600
test cases, new tests have been created for AST1030.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5.
Added scatter-gather and accumulation test variants.
For AST1030, the HACE controller base address starts at "0x7e6d0000", and the
SDRAM start address is "0x0".
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-24-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: dcdbbd45a86ad47327282aa3301622cbe65e9fdb
https://github.com/qemu/qemu/commit/dcdbbd45a86ad47327282aa3301622cbe65e9fdb
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed-hace-utils.c
M tests/qtest/aspeed-hace-utils.h
Log Message:
-----------
test/qtest/hace: Update source data and digest data type to 64-bit
Currently, the hash data source and digest result buffer addresses are set to
32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35 architecture, and its
DRAM base address is also 64-bit.
To support AST2700, update the hash data source address and digest result buffer
address to use 64-bit addressing.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-25-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 5ced818e42ddb9516137e68556eb03c16a486758
https://github.com/qemu/qemu/commit/5ced818e42ddb9516137e68556eb03c16a486758
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed-hace-utils.c
M tests/qtest/aspeed-hace-utils.h
Log Message:
-----------
test/qtest/hace: Support 64-bit source and digest addresses for AST2700
Added "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI", "HACE_HASH_KEY_BUFF_HI"
registers to store upper 32 bits.
Updated "write_regs" to handle 64-bit source and digest addresses.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-26-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 88d8515fb76ca7b3de8a4cc89264e8494655567e
https://github.com/qemu/qemu/commit/88d8515fb76ca7b3de8a4cc89264e8494655567e
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed-hace-utils.c
M tests/qtest/aspeed-hace-utils.h
Log Message:
-----------
test/qtest/hace: Support to test upper 32 bits of digest and source addresses
Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses test.
Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and
"HACE_HASH_DIGEST_HI".
Ensured correct masking of 64-bit addresses by checking both lower and upper
32-bit registers.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-27-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 823288fc136f8d4b165d2eb573306893e43bcdff
https://github.com/qemu/qemu/commit/823288fc136f8d4b165d2eb573306893e43bcdff
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M tests/qtest/aspeed-hace-utils.c
M tests/qtest/aspeed-hace-utils.h
M tests/qtest/aspeed_hace-test.c
Log Message:
-----------
test/qtest/hace: Support to validate 64-bit hmac key buffer addresses
Added "key" and "key_hi" fields to "AspeedMasks" for 64-bit addresses test.
Updated "aspeed_test_addresses" to validate "HACE_HASH_KEY_BUFF" and
"HACE_HASH_KEY_BUFF_HI".
Ensured correct masking of 64-bit addresses by checking both lower and upper
32-bit registers.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-28-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 5071c229106dc6fc46fd1b7667ffa12e0bc47b1d
https://github.com/qemu/qemu/commit/5071c229106dc6fc46fd1b7667ffa12e0bc47b1d
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
A tests/qtest/ast2700-hace-test.c
M tests/qtest/meson.build
Log Message:
-----------
test/qtest/hace: Add tests for AST2700
The HACE models in AST2600 and AST2700 are nearly identical. Based on the
AST2600 test cases, new tests have been added for AST2700.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5.
Added scatter-gather and accumulation test variants.
For AST2700, the HACE controller base address starts at "0x12070000", and
the DRAM start address is "0x4_00000000".
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Acked-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250515081008.583578-29-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 5c14d7cbd42326bf35d18cb765015edfc9883272
https://github.com/qemu/qemu/commit/5c14d7cbd42326bf35d18cb765015edfc9883272
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/intc/aspeed_intc.c
Log Message:
-----------
hw/intc/aspeed: Set impl.min_access_size to 4
This patch explicitly sets ".impl.min_access_size = 4" to match the
declared ".valid.min_access_size = 4", enforcing stricter access size
checking and preventing inconsistent partial accesses to the interrupt
controller registers.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250522023305.2486536-2-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 567accba673326a37b7c9210f613c86afe2965ff
https://github.com/qemu/qemu/commit/567accba673326a37b7c9210f613c86afe2965ff
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/intc/aspeed_intc.c
Log Message:
-----------
hw/intc/aspeed Fix coding style
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250522023305.2486536-3-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: e6941ac106190490d8b455eedc5b368e6d94d4cc
https://github.com/qemu/qemu/commit/e6941ac106190490d8b455eedc5b368e6d94d4cc
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts
On big-endian hosts, the aspeed_ram_capacity_write() function previously passed
the address of a 64-bit "data" variable directly to address_space_write(),
assuming host and guest endianness matched.
However, the data is expected to be written in little-endian format to DRAM.
On big-endian hosts, this led to incorrect data being written into DRAM,
which caused the guest firmware to misdetect the DRAM size.
As a result, U-Boot fails to boot and hangs.
- Replaces the "address_space_write()" call with "address_space_stl_le()",
which performs an explicit 32-bit little-endian write.
- Updating the MemoryRegionOps to restrict access to exactly 4 bytes
using .valid.{min,max}_access_size = 4 and .impl.min_access_size = 4.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Fixes: 7436db1 ("aspeed/soc: fix incorrect dram size for AST2700")
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250522023305.2486536-4-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 453b928ab93415ebf5519d946a77e905a2f1ec12
https://github.com/qemu/qemu/commit/453b928ab93415ebf5519d946a77e905a2f1ec12
Author: Steven Lee <steven_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
Log Message:
-----------
hw/arm/aspeed_ast2700-fc: Add network support
This patch adds network support to the ast2700fc machine by initializing
the NIC device in the ca35.
Signed-off-by: Steven Lee <steven_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250523093144.991408-2-steven_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 61162c6f89d1e07788c5bd8a9b7f778102f8a1eb
https://github.com/qemu/qemu/commit/61162c6f89d1e07788c5bd8a9b7f778102f8a1eb
Author: Steven Lee <steven_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
Log Message:
-----------
hw/arm/aspeed_ast2700-fc: Reduce ca35 ram size to align with ast2700a1
Reduce ca35 ram size from 2GiB to 1GiB to align with ast2700a1-evb,
where the ram-container is defined as 1GiB in its class.
Signed-off-by: Steven Lee <steven_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250523093144.991408-3-steven_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 221d22d830eb1a96f780eec28e6a45286b85fe85
https://github.com/qemu/qemu/commit/221d22d830eb1a96f780eec28e6a45286b85fe85
Author: Steven Lee <steven_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom
The unimplemented memory region overlaps with the VBootROM address
range, causing incorrect memory layout.
This patch adjusts the size and start address of the unimplemented
region to avoid collision. The IO memory region (ASPEED_DEV_IOMEM) is
now moved to 0x20000 to reserve space for VBootROM at 0x0.
Although the memory range 0x20000 - 0x10000000 is undefined in the
datasheet and should not be required, further testing shows OP-TEE
or U-Boot may access 0x400000 during early boot.
Removing the unimplemented region causes firmware hangs.
To prevent unexpected accesses, retain the region as a safeguard.
Signed-off-by: Steven Lee <steven_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250523093144.991408-4-steven_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: bb1747a39b162bdfbf33d53846ed4e7a99f2e75f
https://github.com/qemu/qemu/commit/bb1747a39b162bdfbf33d53846ed4e7a99f2e75f
Author: Steven Lee <steven_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
Log Message:
-----------
hw/arm/aspeed_ast27x0-fc: Map ca35 memory into system memory
Map the CA35 memory region as a subregion of system_memory to ensure
a valid FlatView. This prevents failures in APIs that rely on the
global memory view, such as rom_check_and_register_reset().
Signed-off-by: Steven Lee <steven_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250523093144.991408-5-steven_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: b21d68c34ec25391f6c1a588bdb5c88bd24bb87f
https://github.com/qemu/qemu/commit/b21d68c34ec25391f6c1a588bdb5c88bd24bb87f
Author: Steven Lee <steven_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M hw/arm/fby35.c
Log Message:
-----------
hw/arm/fby35: Map BMC memory into system memory
Add the BMC memory region as a subregion of system_memory so that
modules relying on system memory can operate correctly.
Signed-off-by: Steven Lee <steven_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250523093144.991408-6-steven_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 8eaea4012c215a610b2bd6dcc7812e805e14dd0c
https://github.com/qemu/qemu/commit/8eaea4012c215a610b2bd6dcc7812e805e14dd0c
Author: Steven Lee <steven_...@aspeedtech.com>
Date: 2025-05-25 (Sun, 25 May 2025)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: Remove ast2700fc from Aspeed family boards
The ast2700fc machine is now covered in the dedicated ast2700-evb
section. Listing it in the general Aspeed board family list is
redundant.
Signed-off-by: Steven Lee <steven_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250523093144.991408-7-steven_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e
https://github.com/qemu/qemu/commit/80db93b2b88f9b3ed8927ae7ac74ca30e643a83e
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M docs/system/arm/aspeed.rst
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0.c
M hw/arm/fby35.c
M hw/intc/aspeed_intc.c
M hw/misc/aspeed_hace.c
M hw/misc/trace-events
M include/hw/misc/aspeed_hace.h
A tests/qtest/aspeed-hace-utils.c
A tests/qtest/aspeed-hace-utils.h
M tests/qtest/aspeed_hace-test.c
M tests/qtest/aspeed_smc-test.c
A tests/qtest/ast2700-hace-test.c
M tests/qtest/ast2700-smc-test.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Fixed memory leaks in qtest tests
* Reworked and fixed HACE (crypto) model for AST2700 SoC
* Extended HACE qtest tests
* Fixed RAM size detection on BE hosts
* Added network backends to ast2700fc machine
* Mapped main SoC memory into system memory on multi SoC machines
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 26 May 2025 04:04:38 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <c...@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <c...@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu: (39 commits)
docs: Remove ast2700fc from Aspeed family boards
hw/arm/fby35: Map BMC memory into system memory
hw/arm/aspeed_ast27x0-fc: Map ca35 memory into system memory
hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom
hw/arm/aspeed_ast2700-fc: Reduce ca35 ram size to align with ast2700a1
hw/arm/aspeed_ast2700-fc: Add network support
hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts
hw/intc/aspeed Fix coding style
hw/intc/aspeed: Set impl.min_access_size to 4
test/qtest/hace: Add tests for AST2700
test/qtest/hace: Support to validate 64-bit hmac key buffer addresses
test/qtest/hace: Support to test upper 32 bits of digest and source addresses
test/qtest/hace: Support 64-bit source and digest addresses for AST2700
test/qtest/hace: Update source data and digest data type to 64-bit
test/qtest/hace: Add tests for AST1030
test/qtest/hace: Add SHA-384 tests for AST2600
test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model
test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations
test/qtest/hace: Specify explicit array sizes for test vectors and hash
results
test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Compare: https://github.com/qemu/qemu/compare/3c5a5e213e5f...80db93b2b88f
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