Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 4ec799dd17dcbb0fa4e90e685d5d6fcf8f72338a
https://github.com/qemu/qemu/commit/4ec799dd17dcbb0fa4e90e685d5d6fcf8f72338a
Author: Clément Chigot <chi...@adacore.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M target/sparc/fop_helper.c
Log Message:
-----------
target/sparc: don't set FSR_NVA when comparing unordered floats
FSR_NVA should be set when one of the operands is a signaling NaN or
when using FCMPEx instructions. But those cases are already handled
within check_ieee_exception or floatxx_compare functions.
Otherwise, it should be left untouched.
FTR, this was detected by inf-compare-[5678] tests within gcc
testsuites.
Signed-off-by: Clément Chigot <chi...@adacore.com>
Message-Id: <20250425093513.863289-1-chi...@adacore.com>
Acked-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Commit: 428d1789df911bc863e55eed2d8f33ce991cbd09
https://github.com/qemu/qemu/commit/428d1789df911bc863e55eed2d8f33ce991cbd09
Author: Markus Armbruster <arm...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
Log Message:
-----------
docs/about: Belatedly document tightening of QMP device_add checking
Commit 4d8b0f0a9536 (v6.2.0) deprecated incorrectly typed device_add
arguments. Commit be93fd53723c (qdev-monitor: avoid QemuOpts in QMP
device_add) fixed them for v9.2.0, but neglected to update
documentation. Do that now.
Cc: Stefan Hajnoczi <stefa...@redhat.com>
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Message-ID: <20250521063711.29840-2-arm...@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefa...@redhat.com>
[Commit message typo corrected]
Commit: c2fb6eaeb9d479a80b104914f459a0c6c32e5a88
https://github.com/qemu/qemu/commit/c2fb6eaeb9d479a80b104914f459a0c6c32e5a88
Author: Markus Armbruster <arm...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
M qapi/migration.json
Log Message:
-----------
qapi/migration: Deprecate migrate argument @detach
Argument @detach has always been ignored. Start the clock to get rid
of it.
Cc: Peter Xu <pet...@redhat.com>
Cc: Fabiano Rosas <faro...@suse.de>
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Message-ID: <20250521063711.29840-3-arm...@redhat.com>
ACKed-by: Peter Krempa <pkre...@redhat.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Reviewed-by: Peter Xu <pet...@redhat.com>
Commit: 977dfcd552d0bef725f89bcabcedeb51593000ab
https://github.com/qemu/qemu/commit/977dfcd552d0bef725f89bcabcedeb51593000ab
Author: Markus Armbruster <arm...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
Log Message:
-----------
docs/about/deprecated: Move deprecation notes to tidy up order
The deprecation notes within a section are mostly in version order.
Move the few that aren't so they are.
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Message-ID: <20250521063711.29840-4-arm...@redhat.com>
Reviewed-by: Eric Blake <ebl...@redhat.com>
Commit: 662b85aae131e7cb8dd8b03c9e44a95bc87573ca
https://github.com/qemu/qemu/commit/662b85aae131e7cb8dd8b03c9e44a95bc87573ca
Author: Markus Armbruster <arm...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/removed-features.rst
Log Message:
-----------
docs/about/removed-features: Move removal notes to tidy up order
The removal notes within a section are mostly in version order. Move
the few that aren't so they are.
Signed-off-by: Markus Armbruster <arm...@redhat.com>
Message-ID: <20250521063711.29840-5-arm...@redhat.com>
Reviewed-by: Eric Blake <ebl...@redhat.com>
Commit: 319b0c8d077401f51bf6314039b82db20d5267ee
https://github.com/qemu/qemu/commit/319b0c8d077401f51bf6314039b82db20d5267ee
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW
When we moved TLB_MMIO and TLB_DISCARD_WRITE to TLB_SLOW_FLAGS_MASK,
we failed to update atomic_mmu_lookup to properly reconstruct flags.
Fixes: 24b5e0fdb543 ("include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slow
flags")
Reported-by: Jonathan Cameron <jonathan.came...@huawei.com>
Tested-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 556d05d1e2ac687463ce2877cb4acd1b0589deed
https://github.com/qemu/qemu/commit/556d05d1e2ac687463ce2877cb4acd1b0589deed
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M system/main.c
Log Message:
-----------
system/main: comment lock rationale
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250515174641.4000309-1-pierrick.bouv...@linaro.org>
Commit: 19f036726a416c9248c19befe544a2d30b099a25
https://github.com/qemu/qemu/commit/19f036726a416c9248c19befe544a2d30b099a25
Author: Andreas Schwab <sch...@suse.de>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user: implement pgid field of /proc/self/stat
Signed-off-by: Andreas Schwab <sch...@suse.de>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <mvmfrgzcr4m....@suse.de>
Commit: 67f2d507ca444cfff993c1a05df3aaa4346a372c
https://github.com/qemu/qemu/commit/67f2d507ca444cfff993c1a05df3aaa4346a372c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/helper.c
Log Message:
-----------
target/microblaze: Split out mb_unaligned_access_internal
Use an explicit 64-bit type for the address to store in EAR.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 3f8d6b432dbdd63eecfb454d59d36b08f76c0c95
https://github.com/qemu/qemu/commit/3f8d6b432dbdd63eecfb454d59d36b08f76c0c95
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/helper.c
M target/microblaze/helper.h
Log Message:
-----------
target/microblaze: Introduce helper_unaligned_access
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 526b0d364af081792e469adabbc67aeaca8a4343
https://github.com/qemu/qemu/commit/526b0d364af081792e469adabbc67aeaca8a4343
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/op_helper.c
Log Message:
-----------
target/microblaze: Split out mb_transaction_failed_internal
Use an explicit 64-bit type for the address to store in EAR.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: beea772666fb1bb86136042fd8ee7140a01bb36f
https://github.com/qemu/qemu/commit/beea772666fb1bb86136042fd8ee7140a01bb36f
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/helper.h
M target/microblaze/op_helper.c
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Implement extended address load/store out of line
Use helpers and address_space_ld/st instead of inline
loads and stores. This allows us to perform operations
on physical addresses wider than virtual addresses.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 8cea8bd4d3909b7828310a0f76d5194d1bf0095a
https://github.com/qemu/qemu/commit/8cea8bd4d3909b7828310a0f76d5194d1bf0095a
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/cpu.h
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Use uint64_t for CPUMBState.ear
Use an explicit 64-bit type for EAR.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 14c1d81354c425d98423c41f60db5907f70cf216
https://github.com/qemu/qemu/commit/14c1d81354c425d98423c41f60db5907f70cf216
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea
Use an explicit 64-bit type for extended addresses.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 17ac97a9581fa9dd9c433d7562506a514f7292b3
https://github.com/qemu/qemu/commit/17ac97a9581fa9dd9c433d7562506a514f7292b3
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/mmu.c
Log Message:
-----------
target/microblaze: Fix printf format in mmu_translate
Use TARGET_FMT_lx to match the target_ulong type of vaddr.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b52ee0c1a4205c8d698c37557401d2f55e071fba
https://github.com/qemu/qemu/commit/b52ee0c1a4205c8d698c37557401d2f55e071fba
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M configs/targets/microblaze-softmmu.mak
M configs/targets/microblazeel-softmmu.mak
Log Message:
-----------
target/microblaze: Use TARGET_LONG_BITS == 32 for system mode
Now that the extended address instructions are handled separately
from virtual addresses, we can narrow the emulation to 32-bit.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: bd07403fc146a9bfc5312404a63f24cc48701c97
https://github.com/qemu/qemu/commit/bd07403fc146a9bfc5312404a63f24cc48701c97
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Drop DisasContext.r0
Return a constant 0 from reg_for_read, and a new
temporary from reg_for_write.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 36a9529e60e09b0d0b6b5ebad614255c97bf9322
https://github.com/qemu/qemu/commit/36a9529e60e09b0d0b6b5ebad614255c97bf9322
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Simplify compute_ldst_addr_type{a,b}
Require TCGv_i32 and TCGv be identical, so drop
the extensions. Return constants when possible
instead of a mov into a temporary. Return register
inputs unchanged when possible.
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 9cfcf8c3b7b7a95e754a9fce565a88c6c76ce128
https://github.com/qemu/qemu/commit/9cfcf8c3b7b7a95e754a9fce565a88c6c76ce128
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/translate-all.c
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg: Drop TCGContext.tlb_dyn_max_bits
This was an extremely minor optimization for aarch64
and x86_64, to use a 32-bit AND instruction when the
guest softmmu tlb maximum was sufficiently small.
Both hosts can simply use a 64-bit AND insn instead.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 11efde54f248c2da9e164910b8b1945e78a7168e
https://github.com/qemu/qemu/commit/11efde54f248c2da9e164910b8b1945e78a7168e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/translate-all.c
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/perf.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
Log Message:
-----------
tcg: Drop TCGContext.page_{mask,bits}
Use exec/target_page.h instead of independent variables.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: eb978e50e42f3439e7a7a104e76aafc81bc4a028
https://github.com/qemu/qemu/commit/eb978e50e42f3439e7a7a104e76aafc81bc4a028
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/sh4/translate.c
Log Message:
-----------
target/sh4: Use MO_ALIGN for system UNALIGN()
This should have been done before removing TARGET_ALIGNED_ONLY,
as we did for hppa and alpha.
Cc: Yoshinori Sato <ys...@users.sourceforge.jp>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Fixes: 8244189419f9 ("target/sh4: Remove TARGET_ALIGNED_ONLY")
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: bdf26b5d16dd2264553308aa6bbf24b4749fcc07
https://github.com/qemu/qemu/commit/bdf26b5d16dd2264553308aa6bbf24b4749fcc07
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/accel/tcg/cpu-ops.h
Log Message:
-----------
accel/tcg: Add TCGCPUOps.pointer_wrap
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: a4027ed7d4becb4cb67c912c75ecd4846b148829
https://github.com/qemu/qemu/commit/a4027ed7d4becb4cb67c912c75ecd4846b148829
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/accel/tcg/cpu-ops.h
M target/alpha/cpu.c
M target/hppa/cpu.c
M target/sh4/cpu.c
Log Message:
-----------
target: Use cpu_pointer_wrap_notreached for strict align targets
Alpha, HPPA, and SH4 always use aligned addresses,
and therefore never produce accesses that cross pages.
Cc: Helge Deller <del...@gmx.de>
Cc: Yoshinori Sato <ys...@users.sourceforge.jp>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 981f2beb161b9bcaeedc1f91ad22bff255856cb2
https://github.com/qemu/qemu/commit/981f2beb161b9bcaeedc1f91ad22bff255856cb2
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/accel/tcg/cpu-ops.h
M target/avr/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/openrisc/cpu.c
M target/rx/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
target: Use cpu_pointer_wrap_uint32 for 32-bit targets
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are
all 32-bit targets. AVR is more complicated, but using
a 32-bit wrap preserves current behaviour.
Cc: Michael Rolnik <mrol...@gmail.com>
Cc: Laurent Vivier <laur...@vivier.eu>
Cc: Stafford Horne <sho...@gmail.com>
Cc: Yoshinori Sato <ys...@users.sourceforge.jp>
Cc: Max Filippov <jcmvb...@gmail.com>
Tested-by Bastian Koppelmann <kbast...@mail.uni-paderborn.de> (tricore)
Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: d21144a48c1a9d1998c594d976d5e906276eca4c
https://github.com/qemu/qemu/commit/d21144a48c1a9d1998c594d976d5e906276eca4c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/tcg/cpu-v7m.c
Log Message:
-----------
target/arm: Fill in TCGCPUOps.pointer_wrap
For a-profile, check A32 vs A64 state.
For m-profile, use cpu_pointer_wrap_uint32.
Cc: qemu-...@nongnu.org
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 7174cd2eec67d9b7bf969cdc87e656b4c4c93465
https://github.com/qemu/qemu/commit/7174cd2eec67d9b7bf969cdc87e656b4c4c93465
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/tcg/tcg-cpu.c
Log Message:
-----------
target/i386: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit state.
Cc: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 353f703cf1959228affc23b5bba8a18738736cf4
https://github.com/qemu/qemu/commit/353f703cf1959228affc23b5bba8a18738736cf4
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Fill in TCGCPUOps.pointer_wrap
Check va32 state.
Reviewed-by: Song Gao <gaos...@loongson.cn>
Reviewed-by: Bibo Mao <maob...@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 396c12d00e3944e79159c9f3cb934f26f32ef861
https://github.com/qemu/qemu/commit/396c12d00e3944e79159c9f3cb934f26f32ef861
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/mips/cpu.c
Log Message:
-----------
target/mips: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit addressing state.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 4031eb4facfd8793defeb83c05712643c161e32e
https://github.com/qemu/qemu/commit/4031eb4facfd8793defeb83c05712643c161e32e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit state.
Cc: qemu-...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 8024f004155ea5a3f492c35a792ea7863176e1a9
https://github.com/qemu/qemu/commit/8024f004155ea5a3f492c35a792ea7863176e1a9
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Fill in TCGCPUOps.pointer_wrap
Check 32 vs 64-bit and pointer masking state.
Cc: qemu-ri...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: c2a0439f1ee99cb29883311f75ba08d9cca759c9
https://github.com/qemu/qemu/commit/c2a0439f1ee99cb29883311f75ba08d9cca759c9
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/s390x/cpu.c
Log Message:
-----------
target/s390x: Fill in TCGCPUOps.pointer_wrap
Use the existing wrap_address function.
Cc: qemu-s3...@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 90f80e4b0fedfc78163c1c112bb74ccbfcae2365
https://github.com/qemu/qemu/commit/90f80e4b0fedfc78163c1c112bb74ccbfcae2365
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/sparc/cpu.c
Log Message:
-----------
target/sparc: Fill in TCGCPUOps.pointer_wrap
Check address masking state for sparc64.
Cc: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 5c2891601ccdaa41427187ef95bc25c828b355e4
https://github.com/qemu/qemu/commit/5c2891601ccdaa41427187ef95bc25c828b355e4
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Assert TCGCPUOps.pointer_wrap is set
All targets now provide the function, so we can
make the call unconditional.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 606ad17b8708d13221fdf102d68e64068ad246c1
https://github.com/qemu/qemu/commit/606ad17b8708d13221fdf102d68e64068ad246c1
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M tests/functional/test_sparc64_tuxrun.py
Log Message:
-----------
tests/functional/test_sparc64_tuxrun: Explicitly set the 'sun4u' machine
Use self.set_machine() to set the machine instead of relying on the
default machine of the binary. This way the test can be skipped in
case the machine has not been compiled into the QEMU binary.
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250521145112.142222-1-th...@redhat.com>
Commit: c93fd441c15faa8cdda6f1489d0cf14b73e7f9c3
https://github.com/qemu/qemu/commit/c93fd441c15faa8cdda6f1489d0cf14b73e7f9c3
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M tests/functional/test_mips_malta.py
Log Message:
-----------
tests/functional/test_mips_malta: Re-enable the check for the PCI host bridge
The problem with the PCI bridge has been fixed in commit e5894fd6f411c1
("hw/pci-host/gt64120: Fix endianness handling"), so we can enable the
corresponding test again.
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250522080208.205489-1-th...@redhat.com>
Commit: cb4b7406177683853466121e731a23acdf308467
https://github.com/qemu/qemu/commit/cb4b7406177683853466121e731a23acdf308467
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M tests/functional/test_mem_addr_space.py
Log Message:
-----------
tests/functional/test_mem_addr_space: Use set_machine() to select the machine
By using self.set_machine() the tests get properly skipped in case
the machine has not been compiled into the QEMU binary, e.g. when
"configure" has been run with "--without-default-devices".
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250521143732.140711-1-th...@redhat.com>
Commit: f650b5a8789f56c335b34026c3689fb5dbd6866a
https://github.com/qemu/qemu/commit/f650b5a8789f56c335b34026c3689fb5dbd6866a
Author: Alexandr Moshkov <dtalexund...@yandex-team.ru>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M tests/functional/qemu_test/__init__.py
M tests/functional/qemu_test/decorators.py
Log Message:
-----------
tests/functional: add skipLockedMemoryTest decorator
Used in future commit to skipping execution of a tests if the system's
locked memory limit is below the required threshold.
Signed-off-by: Alexandr Moshkov <dtalexund...@yandex-team.ru>
Reviewed-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250525070737.54267-2-dtalexund...@yandex-team.ru>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 98b663f9bce7c506455d9c33cc52eaa94fa23c1c
https://github.com/qemu/qemu/commit/98b663f9bce7c506455d9c33cc52eaa94fa23c1c
Author: Alexandr Moshkov <dtalexund...@yandex-team.ru>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M tests/functional/meson.build
A tests/functional/test_memlock.py
Log Message:
-----------
tests/functional: add memlock tests
Add new tests to check the correctness of the `-overcommit memlock`
option (possible values: off, on, on-fault) by using
`/proc/{qemu_pid}/status` file to check in VmSize, VmRSS and VmLck
values:
* if `memlock=off`, then VmLck = 0;
* if `memlock=on`, then VmLck > 0 and almost all memory is resident;
* if `memlock=on-fault`, then VmLck > 0 and only few memory is resident.
Signed-off-by: Alexandr Moshkov <dtalexund...@yandex-team.ru>
Message-ID: <20250525070737.54267-3-dtalexund...@yandex-team.ru>
[thuth: improved the text in a comment]
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: f5beda6d029dee153ef67a7bb1e4a12e60c20ec7
https://github.com/qemu/qemu/commit/f5beda6d029dee153ef67a7bb1e4a12e60c20ec7
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/microblaze/petalogix_s3adsp1800_mmu.c
Log Message:
-----------
hw/microblaze: Add endianness property to the petalogix_s3adsp1800 machine
Since the microblaze target can now handle both endianness, big and
little, we should provide a config knob for the user to select the
desired endianness.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250515132019.569365-2-th...@redhat.com>
Commit: 6f0073967c5b567f6de6fab51f3ca33ce1af40eb
https://github.com/qemu/qemu/commit/6f0073967c5b567f6de6fab51f3ca33ce1af40eb
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M tests/functional/test_microblaze_s3adsp1800.py
M tests/functional/test_microblazeel_s3adsp1800.py
Log Message:
-----------
tests/functional: Test both microblaze s3adsp1800 endianness variants
Now that the endianness of the petalogix-s3adsp1800 can be configured,
we should test that the cross-endianness also works as expected, thus
test the big endian variant on the little endian target and vice versa.
(based on an original idea from Philippe Mathieu-Daudé)
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250515132019.569365-3-th...@redhat.com>
Commit: ed2e1d9f17e577a8889c9099fc877c0395ae9b72
https://github.com/qemu/qemu/commit/ed2e1d9f17e577a8889c9099fc877c0395ae9b72
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/microblaze/petalogix_ml605_mmu.c
M hw/microblaze/xlnx-zynqmp-pmu.c
Log Message:
-----------
hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu
Both machines were added with little-endian in mind only (the
"endianness" CPU property was hard-wired to "true", see commits
133d23b3ad1 and a88bbb006a52), so the variants that showed up
on the big endian target likely never worked. We deprecated these
non-working machine variants two releases ago, and so far nobody
complained, so it should be fine now to disable them. Hard-wire
the machines to little endian now.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250515132019.569365-4-th...@redhat.com>
Commit: 246f9c7a0f5f9af0cd193464ddd93225580adf7b
https://github.com/qemu/qemu/commit/246f9c7a0f5f9af0cd193464ddd93225580adf7b
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
Log Message:
-----------
docs: Deprecate the qemu-system-microblazeel binary
The (former big-endian only) binary qemu-system-microblaze can
handle both endiannesses nowadays, so we don't need the separate
qemu-system-microblazeel binary for little endian anymore. Let's
deprecate it to avoid unnecessary compilation and test time in
the future.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250515132019.569365-5-th...@redhat.com>
Commit: db23d0a96a7c73c00264ce28220494dd53cefd87
https://github.com/qemu/qemu/commit/db23d0a96a7c73c00264ce28220494dd53cefd87
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M tests/qtest/test-x86-cpuid-compat.c
Log Message:
-----------
hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the qtest in test-x86-cpuid-compat.c file.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-2-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: eb814fe5e4fde7581454753dc4fd630c590b6700
https://github.com/qemu/qemu/commit/eb814fe5e4fde7581454753dc4fd630c590b6700
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/i386/pc: Remove PCMachineClass::broken_reserved_end field
The PCMachineClass::broken_reserved_end field was only used
by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed.
Remove it and simplify pc_memory_init().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-3-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: eddb0890dee9fec724fc30e8713e8a70b5444bc7
https://github.com/qemu/qemu/commit/eddb0890dee9fec724fc30e8713e8a70b5444bc7
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/i386/pc: Remove pc_compat_2_4[] array
The pc_compat_2_4[] array was only used by the pc-q35-2.4
and pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-4-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 713329b5d463f7e680a867ecc0921c2195b6d768
https://github.com/qemu/qemu/commit/713329b5d463f7e680a867ecc0921c2195b6d768
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/core/machine.c
M include/hw/boards.h
Log Message:
-----------
hw/core/machine: Remove hw_compat_2_4[] array
The hw_compat_2_4[] array was only used by the pc-q35-2.4 and
pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-6-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 92656566740a7870563a1bbbefede3a42452e8e5
https://github.com/qemu/qemu/commit/92656566740a7870563a1bbbefede3a42452e8e5
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/net/e1000.c
Log Message:
-----------
hw/net/e1000: Remove unused E1000_FLAG_MAC flag
E1000_FLAG_MAC was only used by the hw_compat_2_4[] array,
via the 'extra_mac_registers=off' property. We removed all
machines using that array, lets remove all the code around
E1000_FLAG_MAC, including the MAC_ACCESS_FLAG_NEEDED enum,
similarly to commit fa4ec9ffda7 ("e1000: remove old
compatibility code").
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-ID: <20250512083948.39294-7-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 1c201de42510a777a77d496281afa3ecbdc8e5dc
https://github.com/qemu/qemu/commit/1c201de42510a777a77d496281afa3ecbdc8e5dc
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/virtio/virtio-pci.c
M include/hw/virtio/virtio-pci.h
Log Message:
-----------
hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition
VIRTIO_PCI_FLAG_MIGRATE_EXTRA was only used by the
hw_compat_2_4[] array, via the 'migrate-extra=true'
property. We removed all machines using that array,
lets remove all the code around VIRTIO_PCI_FLAG_MIGRATE_EXTRA.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-ID: <20250512083948.39294-8-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: d9ae5023a7f4d51b03a82303f1393cc3afc6b16b
https://github.com/qemu/qemu/commit/d9ae5023a7f4d51b03a82303f1393cc3afc6b16b
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/virtio/virtio-pci.c
M include/hw/virtio/virtio-pci.h
Log Message:
-----------
hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition
VIRTIO_PCI_FLAG_DISABLE_PCIE was only used by the hw_compat_2_4[]
array, via the 'x-disable-pcie=false' property. We removed all
machines using that array, lets remove all the code around
VIRTIO_PCI_FLAG_DISABLE_PCIE (see commit 9a4c0e220d8 for similar
VIRTIO_PCI_FLAG_* enum removal).
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-9-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 88382fbd296616987bf247a4a88c0cf904da2a32
https://github.com/qemu/qemu/commit/88382fbd296616987bf247a4a88c0cf904da2a32
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the now unused empty pc_compat_2_5[] array.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-10-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 644ac886d41e493134794892ed25550007da2b81
https://github.com/qemu/qemu/commit/644ac886d41e493134794892ed25550007da2b81
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/x86.c
M include/hw/i386/x86.h
M target/i386/machine.c
Log Message:
-----------
hw/i386/x86: Remove X86MachineClass::save_tsc_khz field
The X86MachineClass::save_tsc_khz boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it and simplify tsc_khz_needed().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-11-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: beedab961b88d452e4c0c845815c3921109bfc1f
https://github.com/qemu/qemu/commit/beedab961b88d452e4c0c845815c3921109bfc1f
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/core/loader.c
M hw/i386/pc.c
M hw/nvram/fw_cfg.c
M include/hw/boards.h
M include/hw/loader.h
M include/hw/nvram/fw_cfg.h
M system/vl.c
Log Message:
-----------
hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE
The MachineClass::legacy_fw_cfg_order boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it along with:
- FW_CFG_ORDER_OVERRIDE_* definitions
- fw_cfg_set_order_override()
- fw_cfg_reset_order_override()
- fw_cfg_order[]
- rom_set_order_override()
- rom_reset_order_override()
Simplify CLI and pc_vga_init() / pc_nic_init().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-12-phi...@linaro.org>
[thuth: Fix error from check_patch.pl wrt to an empty "for" loop]
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 122d3e68ebf5b925591ac237a72dd96908d51ee1
https://github.com/qemu/qemu/commit/122d3e68ebf5b925591ac237a72dd96908d51ee1
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/core/machine.c
M include/hw/boards.h
Log Message:
-----------
hw/core/machine: Remove hw_compat_2_5[] array
The hw_compat_2_5[] array was only used by the pc-q35-2.5 and
pc-i440fx-2.5 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-13-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 27ecb0e146ed1682fc894f7765f8bee3217ba8ed
https://github.com/qemu/qemu/commit/27ecb0e146ed1682fc894f7765f8bee3217ba8ed
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/scsi/vmw_pvscsi.c
Log Message:
-----------
hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition
PVSCSI_COMPAT_OLD_PCI_CONFIGURATION was only used by the
hw_compat_2_5[] array, via the 'x-old-pci-configuration=on'
property. We removed all machines using that array, lets remove
all the code around PVSCSI_COMPAT_OLD_PCI_CONFIGURATION.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-15-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: ff83a6c56c4e124bafdde880c0ebb30ebfab8d35
https://github.com/qemu/qemu/commit/ff83a6c56c4e124bafdde880c0ebb30ebfab8d35
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/scsi/vmw_pvscsi.c
Log Message:
-----------
hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition
PVSCSI_COMPAT_DISABLE_PCIE_BIT was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around PVSCSI_COMPAT_DISABLE_PCIE_BIT, including the now
unused PVSCSIState::compat_flags field.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-16-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 424d9a408931b93ac177533227ca73ba1538cd61
https://github.com/qemu/qemu/commit/424d9a408931b93ac177533227ca73ba1538cd61
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/scsi/vmw_pvscsi.c
Log Message:
-----------
hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit
Simplify replacing pvscsi_realize() by pvscsi_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-17-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: d935d9ad8ed3e2395a07e746bded9b8ed045087f
https://github.com/qemu/qemu/commit/d935d9ad8ed3e2395a07e746bded9b8ed045087f
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/net/vmxnet3.c
Log Message:
-----------
hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition
VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS was only used by the
hw_compat_2_5[] array, via the 'x-old-msi-offsets=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-18-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 70ed57ba5412960b283540421b182afb44c8a502
https://github.com/qemu/qemu/commit/70ed57ba5412960b283540421b182afb44c8a502
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/net/vmxnet3.c
Log Message:
-----------
hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition
VMXNET3_COMPAT_FLAG_DISABLE_PCIE was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_DISABLE_PCIE.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-19-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 352f6bf725b52fbf1e15028adcfd65c2052c1088
https://github.com/qemu/qemu/commit/352f6bf725b52fbf1e15028adcfd65c2052c1088
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/net/vmxnet3.c
Log Message:
-----------
hw/net/vmxnet3: Merge DeviceRealize in InstanceInit
Simplify merging vmxnet3_realize() within vmxnet3_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-20-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 9c2da02e184fddfa7cd7d7813455c2306daae99a
https://github.com/qemu/qemu/commit/9c2da02e184fddfa7cd7d7813455c2306daae99a
Author: Matheus Tavares Bernardino <matheus.bernard...@oss.qualcomm.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M tests/unit/test-util-sockets.c
Log Message:
-----------
tests/unit/test-util-sockets: fix mem-leak on error object
The test fails with --enable-asan as the error struct is never freed.
In the case where the test expects a success but it fails, let's also
report the error for debugging (it will be freed internally).
Fixes 316e8ee8d6 ("util/qemu-sockets: Refactor inet_parse() to use QemuOpts")
Signed-off-by: Matheus Tavares Bernardino <matheus.bernard...@oss.qualcomm.com>
Reviewed-by: Juraj Marcin <jmar...@redhat.com>
Message-ID:
<518d94c7db20060b2a086cf55ee9bffab992a907.1748280011.git.matheus.bernard...@oss.qualcomm.com>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: bff6236c7e984a710741b34c44fee002e686e6ce
https://github.com/qemu/qemu/commit/bff6236c7e984a710741b34c44fee002e686e6ce
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/sparc/fop_helper.c
Log Message:
-----------
Merge tag 'qemu-sparc-20250527' of https://github.com/mcayland/qemu into
staging
qemu-sparc queue
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 27 May 2025 17:16:20 EDT
# gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg: issuer "mark.cave-ayl...@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>"
[full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* tag 'qemu-sparc-20250527' of https://github.com/mcayland/qemu:
target/sparc: don't set FSR_NVA when comparing unordered floats
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: e21076e9f721fc264f6c919d80d0984d3eb56ff4
https://github.com/qemu/qemu/commit/e21076e9f721fc264f6c919d80d0984d3eb56ff4
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/translate-all.c
M configs/targets/microblaze-softmmu.mak
M configs/targets/microblazeel-softmmu.mak
M include/accel/tcg/cpu-ops.h
M include/tcg/tcg.h
M linux-user/syscall.c
M system/main.c
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/tcg/cpu-v7m.c
M target/avr/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/helper.c
M target/microblaze/helper.h
M target/microblaze/mmu.c
M target/microblaze/op_helper.c
M target/microblaze/translate.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/tcg/tcg-cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sh4/translate.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/perf.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
Log Message:
-----------
Merge tag 'pull-tcg-20250528' of https://gitlab.com/rth7680/qemu into staging
accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW
linux-user: implement pgid field of /proc/self/stat
target/sh4: Use MO_ALIGN for system UNALIGN()
target/microblaze: Use TARGET_LONG_BITS == 32 for system mode
accel/tcg: Add TCGCPUOps.pointer_wrap
target/*: Populate TCGCPUOps.pointer_wrap
# -----BEGIN PGP SIGNATURE-----
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# gpg: Signature made Wed 28 May 2025 04:13:04 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.hender...@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.hender...@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20250528' of https://gitlab.com/rth7680/qemu: (28 commits)
accel/tcg: Assert TCGCPUOps.pointer_wrap is set
target/sparc: Fill in TCGCPUOps.pointer_wrap
target/s390x: Fill in TCGCPUOps.pointer_wrap
target/riscv: Fill in TCGCPUOps.pointer_wrap
target/ppc: Fill in TCGCPUOps.pointer_wrap
target/mips: Fill in TCGCPUOps.pointer_wrap
target/loongarch: Fill in TCGCPUOps.pointer_wrap
target/i386: Fill in TCGCPUOps.pointer_wrap
target/arm: Fill in TCGCPUOps.pointer_wrap
target: Use cpu_pointer_wrap_uint32 for 32-bit targets
target: Use cpu_pointer_wrap_notreached for strict align targets
accel/tcg: Add TCGCPUOps.pointer_wrap
target/sh4: Use MO_ALIGN for system UNALIGN()
tcg: Drop TCGContext.page_{mask,bits}
tcg: Drop TCGContext.tlb_dyn_max_bits
target/microblaze: Simplify compute_ldst_addr_type{a,b}
target/microblaze: Drop DisasContext.r0
target/microblaze: Use TARGET_LONG_BITS == 32 for system mode
target/microblaze: Fix printf format in mmu_translate
target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 2eda596d379c94bcc998f97b1c227597e69f6d2a
https://github.com/qemu/qemu/commit/2eda596d379c94bcc998f97b1c227597e69f6d2a
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/core/loader.c
M hw/core/machine.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/i386/x86.c
M hw/microblaze/petalogix_ml605_mmu.c
M hw/microblaze/petalogix_s3adsp1800_mmu.c
M hw/microblaze/xlnx-zynqmp-pmu.c
M hw/net/e1000.c
M hw/net/vmxnet3.c
M hw/nvram/fw_cfg.c
M hw/scsi/vmw_pvscsi.c
M hw/virtio/virtio-pci.c
M include/hw/boards.h
M include/hw/i386/pc.h
M include/hw/i386/x86.h
M include/hw/loader.h
M include/hw/nvram/fw_cfg.h
M include/hw/virtio/virtio-pci.h
M system/vl.c
M target/i386/machine.c
M tests/functional/meson.build
M tests/functional/qemu_test/__init__.py
M tests/functional/qemu_test/decorators.py
M tests/functional/test_mem_addr_space.py
A tests/functional/test_memlock.py
M tests/functional/test_microblaze_s3adsp1800.py
M tests/functional/test_microblazeel_s3adsp1800.py
M tests/functional/test_mips_malta.py
M tests/functional/test_sparc64_tuxrun.py
M tests/qtest/test-x86-cpuid-compat.c
M tests/unit/test-util-sockets.c
Log Message:
-----------
Merge tag 'pull-request-2025-05-28' of https://gitlab.com/thuth/qemu into
staging
* Functional tests improvements
* Endianness improvements/clean-ups for the Microblaze machines
* Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and related code
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# gpg: Signature made Wed 28 May 2025 06:02:42 EDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "th...@redhat.com"
# gpg: Good signature from "Thomas Huth <th.h...@gmx.de>" [full]
# gpg: aka "Thomas Huth <th...@redhat.com>" [full]
# gpg: aka "Thomas Huth <h...@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.h...@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2025-05-28' of https://gitlab.com/thuth/qemu: (27 commits)
tests/unit/test-util-sockets: fix mem-leak on error object
hw/net/vmxnet3: Merge DeviceRealize in InstanceInit
hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition
hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition
hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit
hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition
hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition
hw/core/machine: Remove hw_compat_2_5[] array
hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE
hw/i386/x86: Remove X86MachineClass::save_tsc_khz field
hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines
hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition
hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition
hw/net/e1000: Remove unused E1000_FLAG_MAC flag
hw/core/machine: Remove hw_compat_2_4[] array
hw/i386/pc: Remove pc_compat_2_4[] array
hw/i386/pc: Remove PCMachineClass::broken_reserved_end field
hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines
docs: Deprecate the qemu-system-microblazeel binary
hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 90441ed4cb3096184d515d47000e2526c0fc6cac
https://github.com/qemu/qemu/commit/90441ed4cb3096184d515d47000e2526c0fc6cac
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M qapi/migration.json
Log Message:
-----------
Merge tag 'pull-misc-2025-05-28' of https://repo.or.cz/qemu/armbru into
staging
Miscellaneous patches for 2025-05-28
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# gpg: Signature made Wed 28 May 2025 08:03:30 EDT
# gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "arm...@redhat.com"
# gpg: Good signature from "Markus Armbruster <arm...@redhat.com>" [full]
# gpg: aka "Markus Armbruster <arm...@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* tag 'pull-misc-2025-05-28' of https://repo.or.cz/qemu/armbru:
docs/about/removed-features: Move removal notes to tidy up order
docs/about/deprecated: Move deprecation notes to tidy up order
qapi/migration: Deprecate migrate argument @detach
docs/about: Belatedly document tightening of QMP device_add checking
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Compare: https://github.com/qemu/qemu/compare/80db93b2b88f...90441ed4cb30
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