Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 4fb54de823e9d5b88b7f708516a2a9bf997d15c2
https://github.com/qemu/qemu/commit/4fb54de823e9d5b88b7f708516a2a9bf997d15c2
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M meson.build
Log Message:
-----------
meson: build target libraries with common dependencies
As mentioned in [1], dependencies
were missing when compiling per target libraries, thus breaking
compilation on certain host systems.
We now explicitly add common dependencies to those libraries, so it
solves the problem.
[1] https://lore.kernel.org/qemu-devel/20250513115637.184940-1-th...@redhat.com/
Tested-by: Thomas Huth <th...@redhat.com>
Fixes: 6f4e8a92bbd ("hw/arm: make most of the compilation units common")
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link:
https://lore.kernel.org/r/20250521223414.248276-2-pierrick.bouv...@linaro.org
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 0ca26a51791f2601238129c6c2724cc4c604392c
https://github.com/qemu/qemu/commit/0ca26a51791f2601238129c6c2724cc4c604392c
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M hw/arm/meson.build
Log Message:
-----------
hw/arm: remove explicit dependencies listed
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link:
https://lore.kernel.org/r/20250521223414.248276-3-pierrick.bouv...@linaro.org
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 598a0ba8e6df8c113c77e69ee18c3872fda7b6e9
https://github.com/qemu/qemu/commit/598a0ba8e6df8c113c77e69ee18c3872fda7b6e9
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M target/arm/meson.build
Log Message:
-----------
target/arm: remove explicit dependencies listed
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link:
https://lore.kernel.org/r/20250521223414.248276-4-pierrick.bouv...@linaro.org
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: b17b51d325130bc9d0f1189461a9a681fbd554e5
https://github.com/qemu/qemu/commit/b17b51d325130bc9d0f1189461a9a681fbd554e5
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M meson.build
Log Message:
-----------
meson: apply target config for picking files from lib{system, user}
semihosting code needs to be included only if CONFIG_SEMIHOSTING is set.
However, this is a target configuration, so we need to apply it to the
lib{system, user}_ss.
As well, this prepares merging lib{system, user}_ss with
{system, user}_ss.
Acked-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link:
https://lore.kernel.org/r/20250521223414.248276-5-pierrick.bouv...@linaro.org
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 7ca433244c6dde497bb36184f70b442b399fda3e
https://github.com/qemu/qemu/commit/7ca433244c6dde497bb36184f70b442b399fda3e
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M meson.build
Log Message:
-----------
meson: merge lib{system, user}_ss with {system, user}_ss
Now that target configuration can be applied to lib{system, user}_ss,
there is no reason to keep that separate from the existing {system,
user}_ss.
The only difference is that we'll now compile those files with
-DCOMPILING_SYSTEM_VS_USER, which removes poison for
CONFIG_USER_ONLY and CONFIG_SOFTMMU, without any other side effect.
We extract existing system/user code common common libraries to
lib{system, user}.
To not break existing meson files, we alias libsystem_ss to system_ss
and libuser_ss to user_ss, so we can do the cleanup in next commit.
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link:
https://lore.kernel.org/r/20250521223414.248276-6-pierrick.bouv...@linaro.org
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d33717d7fca6a599aa991f771e3ea34b15978cee
https://github.com/qemu/qemu/commit/d33717d7fca6a599aa991f771e3ea34b15978cee
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M accel/tcg/meson.build
M gdbstub/meson.build
M hw/core/meson.build
M meson.build
M plugins/meson.build
M system/meson.build
M tcg/meson.build
Log Message:
-----------
meson: remove lib{system, user}_ss aliases
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link:
https://lore.kernel.org/r/20250521223414.248276-7-pierrick.bouv...@linaro.org
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ddc25eb40444f4bbcfea276d22beee6494c3f18e
https://github.com/qemu/qemu/commit/ddc25eb40444f4bbcfea276d22beee6494c3f18e
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M meson.build
Log Message:
-----------
meson: merge hw_common_arch in target_common_system_arch
No need to keep two different libraries, as both are compiled with exact
same flags. As well, rename target common libraries to common_{arch} and
system_{arch}, to follow what exists for common and system libraries.
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link:
https://lore.kernel.org/r/20250521223414.248276-8-pierrick.bouv...@linaro.org
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d74169e09e1d424aaca138966f460520a0d4dd0d
https://github.com/qemu/qemu/commit/d74169e09e1d424aaca138966f460520a0d4dd0d
Author: Zhao Liu <zhao1....@intel.com>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M hw/timer/hpet.c
Log Message:
-----------
hw/timer/hpet: Reorganize register decoding
For Rust HPET, since the commit 519088b7cf6d ("rust: hpet: decode HPET
registers into enums"), it decodes register address by checking if the
register belongs to global register space. And for C HPET, it checks
timer register space first.
While both approaches are fine, it's best to be as consistent as
possible.
Synchronize changes from the rust side to C side.
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250520152750.2542612-2-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 86c54a3a418e462e67444ac4db25b2757fd62079
https://github.com/qemu/qemu/commit/86c54a3a418e462e67444ac4db25b2757fd62079
Author: Zhao Liu <zhao1....@intel.com>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M rust/hw/timer/hpet/src/fw_cfg.rs
M rust/hw/timer/hpet/src/hpet.rs
M rust/hw/timer/hpet/src/lib.rs
M rust/qemu-api/src/bitops.rs
M rust/qemu-api/src/timer.rs
M rust/qemu-api/tests/vmstate_tests.rs
Log Message:
-----------
rust: Fix Zhao's email address
No one could find Zhao Liu via zhai1....@intel.com.
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250520152750.2542612-5-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: aef5ac8624c7b826ae2adde48bc6997286ee1303
https://github.com/qemu/qemu/commit/aef5ac8624c7b826ae2adde48bc6997286ee1303
Author: Zhao Liu <zhao1....@intel.com>
Date: 2025-05-26 (Mon, 26 May 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
M rust/qemu-api/src/qom.rs
M rust/qemu-api/src/vmstate.rs
Log Message:
-----------
rust: Fix the typos in doc
These typos are found by "cargo spellcheck". Though it outputs a lot of
noise and false positives, there still are some real typos.
Signed-off-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250520152750.2542612-6-zhao1....@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 734a1e9eeed2c791c8906d0ee08ad5c9b1f41fa0
https://github.com/qemu/qemu/commit/734a1e9eeed2c791c8906d0ee08ad5c9b1f41fa0
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
A rust/hw/timer/hpet/src/device.rs
R rust/hw/timer/hpet/src/hpet.rs
M rust/hw/timer/hpet/src/lib.rs
Log Message:
-----------
rust: hpet: rename hpet module to "device"
Follow a similar convention as pl011.
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 341ed3eae4179273788d2f74579862a10e18cf81
https://github.com/qemu/qemu/commit/341ed3eae4179273788d2f74579862a10e18cf81
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-05-27 (Tue, 27 May 2025)
Changed paths:
M target/i386/emulate/x86_flags.c
Log Message:
-----------
target/i386/emulate: more lflags cleanups
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 5150004ccf5fe72c35b3263fbed6f4d06ed3cc6a
https://github.com/qemu/qemu/commit/5150004ccf5fe72c35b3263fbed6f4d06ed3cc6a
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/net/rocker/rocker.h
M hw/net/rocker/rocker_hw.h
M hw/net/rocker/rocker_of_dpa.c
Log Message:
-----------
rocker: do not pollute the namespace
Do not leave the __le* macros defined, in fact do not use them at all. Fixes a
build failure on Alpine with the TDX patches:
In file included from ../hw/net/rocker/rocker_of_dpa.c:25:
../hw/net/rocker/rocker_hw.h:14:16: error: conflicting types for 'uint64_t';
have '__u64' {aka 'long long unsigned int'}
14 | #define __le64 uint64_t
| ^~~~~~~~
In file included from /usr/include/stdint.h:20,
from ../include/qemu/osdep.h:111,
from ../hw/net/rocker/rocker_of_dpa.c:17:
/usr/include/bits/alltypes.h:136:25: note: previous declaration of 'uint64_t'
with type 'uint64_t' {aka 'long unsigned int'}
136 | typedef unsigned _Int64 uint64_t;
| ^~~~~~~~
because the Linux headers include a typedef of __leNN.
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 756e12e791771034ac105a5d2c9887bbbb6b7c73
https://github.com/qemu/qemu/commit/756e12e791771034ac105a5d2c9887bbbb6b7c73
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M configs/devices/i386-softmmu/default.mak
M hw/i386/Kconfig
M qapi/qom.json
M target/i386/kvm/meson.build
A target/i386/kvm/tdx.c
A target/i386/kvm/tdx.h
Log Message:
-----------
i386: Introduce tdx-guest object
Introduce tdx-guest object which inherits X86_CONFIDENTIAL_GUEST,
and will be used to create TDX VMs (TDs) by
qemu -machine ...,confidential-guest-support=tdx0 \
-object tdx-guest,id=tdx0
It has one QAPI member 'attributes' defined, which allows user to set
TD's attributes directly.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Markus Armbruster <arm...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-3-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: b455880e5515a9fc2b923bfc6c60bb54519b51d3
https://github.com/qemu/qemu/commit/b455880e5515a9fc2b923bfc6c60bb54519b51d3
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/kvm.c
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Implement tdx_kvm_type() for TDX
TDX VM requires VM type to be KVM_X86_TDX_VM. Implement tdx_kvm_type()
as X86ConfidentialGuestClass->kvm_type.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-4-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 631a2ac5a4beab740b342367550562cd659b4c4a
https://github.com/qemu/qemu/commit/631a2ac5a4beab740b342367550562cd659b4c4a
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/kvm.c
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Implement tdx_kvm_init() to initialize TDX VM context
Implement TDX specific ConfidentialGuestSupportClass::kvm_init()
callback, tdx_kvm_init().
Mark guest state is proctected for TDX VM. More TDX specific
initialization will be added later.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-5-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 8eddedc3701d2190db976a05155a8263c8ec175b
https://github.com/qemu/qemu/commit/8eddedc3701d2190db976a05155a8263c8ec175b
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES
KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing
TDX context. It will be used to validate user's setting later.
Since there is no interface reporting how many cpuid configs contains in
KVM_TDX_CAPABILITIES, QEMU chooses to try starting with a known number
and abort when it exceeds KVM_MAX_CPUID_ENTRIES.
Besides, introduce the interfaces to invoke TDX "ioctls" at VCPU scope
in preparation.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-6-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 1619d0e45be0d1e48a46d80963b4e77dc1b000a2
https://github.com/qemu/qemu/commit/1619d0e45be0d1e48a46d80963b4e77dc1b000a2
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
M target/i386/kvm/tdx.h
Log Message:
-----------
i386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object
It will need special handling for TDX VMs all around the QEMU.
Introduce is_tdx_vm() helper to query if it's a TDX VM.
Cache tdx_guest object thus no need to cast from ms->cgs every time.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Isaku Yamahata <isaku.yamah...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-7-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: a668268dc08f7f4d30cecd513054bb38ce48c0d6
https://github.com/qemu/qemu/commit/a668268dc08f7f4d30cecd513054bb38ce48c0d6
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/kvm/kvm-all.c
M include/system/kvm.h
M target/arm/kvm.c
M target/i386/kvm/kvm.c
M target/loongarch/kvm/kvm.c
M target/mips/kvm.c
M target/ppc/kvm.c
M target/riscv/kvm/kvm-cpu.c
M target/s390x/kvm/kvm.c
Log Message:
-----------
kvm: Introduce kvm_arch_pre_create_vcpu()
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
The specific implementation for i386 will be added in the future patch.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-8-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: f15898b0f50609d66465326221aa54b6699da674
https://github.com/qemu/qemu/commit/f15898b0f50609d66465326221aa54b6699da674
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/kvm/meson.build
A target/i386/kvm/tdx-stub.c
M target/i386/kvm/tdx.c
M target/i386/kvm/tdx.h
Log Message:
-----------
i386/tdx: Initialize TDX before creating TD vcpus
Invoke KVM_TDX_INIT_VM in kvm_arch_pre_create_vcpu() that
KVM_TDX_INIT_VM configures global TD configurations, e.g. the canonical
CPUID config, and must be executed prior to creating vCPUs.
Use kvm_x86_arch_cpuid() to setup the CPUID settings for TDX VM.
Note, this doesn't address the fact that QEMU may change the CPUID
configuration when creating vCPUs, i.e. punts on refactoring QEMU to
provide a stable CPUID config prior to kvm_arch_init().
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Markus Armbruster <arm...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-9-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 6016e2972d94c90307b6caf55a8e3aee5424c09b
https://github.com/qemu/qemu/commit/6016e2972d94c90307b6caf55a8e3aee5424c09b
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M qapi/qom.json
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Add property sept-ve-disable for tdx-guest object
Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
EPT violation conversion to #VE on guest TD access of PENDING pages.
Some guest OS (e.g., Linux TD guest) may require this bit as 1.
Otherwise refuse to boot.
Add sept-ve-disable property for tdx-guest object, for user to configure
this bit.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Acked-by: Markus Armbruster <arm...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-10-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 714af52276e74a1829674d180ef26ecb6261834c
https://github.com/qemu/qemu/commit/714af52276e74a1829674d180ef26ecb6261834c
Author: Isaku Yamahata <isaku.yamah...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Make sept_ve_disable set by default
For TDX KVM use case, Linux guest is the most major one. It requires
sept_ve_disable set. Make it default for the main use case. For other use
case, it can be enabled/disabled via qemu command line.
Signed-off-by: Isaku Yamahata <isaku.yamah...@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-11-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: bb3be394cf80d68251e5b89e823dddc679b6e644
https://github.com/qemu/qemu/commit/bb3be394cf80d68251e5b89e823dddc679b6e644
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Wire CPU features up with attributes of TD guest
For QEMU VMs,
- PKS is configured via CPUID_7_0_ECX_PKS, e.g., -cpu xxx,+pks and
- PMU is configured by x86cpu->enable_pmu, e.g., -cpu xxx,pmu=on
While the bit 30 (PKS) and bit 63 (PERFMON) of TD's attributes are also
used to configure the PKS and PERFMON/PMU of TD, reuse the existing
configuration interfaces of 'cpu' for TD's attributes.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-12-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 53b6f406b4f1a215fb3ec60e56ddba2e019a45ef
https://github.com/qemu/qemu/commit/53b6f406b4f1a215fb3ec60e56ddba2e019a45ef
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Validate TD attributes
Validate TD attributes with tdx_caps that only supported bits are
allowed by KVM.
Besides, sanity check the attribute bits that have not been supported by
QEMU yet. e.g., debug bit, it will be allowed in the future when debug
TD support lands in QEMU.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Link: https://lore.kernel.org/r/20250508150002.689633-13-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d05a0858cf876f79b57a622716fbad07f5b2ea08
https://github.com/qemu/qemu/commit/d05a0858cf876f79b57a622716fbad07f5b2ea08
Author: Isaku Yamahata <isaku.yamah...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M qapi/qom.json
M target/i386/kvm/tdx.c
M target/i386/kvm/tdx.h
Log Message:
-----------
i386/tdx: Support user configurable mrconfigid/mrowner/mrownerconfig
Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them can be
found:
https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef-ab08-4813f4e0f...@intel.com/
Allow user to specify those values via property mrconfigid, mrowner and
mrownerconfig. They are all in base64 format.
example
-object tdx-guest, \
mrconfigid=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v,\
mrowner=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v,\
mrownerconfig=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v
Signed-off-by: Isaku Yamahata <isaku.yamah...@intel.com>
Co-developed-by: Xiaoyao Li <xiaoyao...@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Markus Armbruster <arm...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-14-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: d529a2ac5ef4620173439942f78ec668f9165fc1
https://github.com/qemu/qemu/commit/d529a2ac5ef4620173439942f78ec668f9165fc1
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
M target/i386/kvm/tdx.h
Log Message:
-----------
i386/tdx: Set APIC bus rate to match with what TDX module enforces
TDX advertises core crystal clock with cpuid[0x15] as 25MHz for TD
guests and it's unchangeable from VMM. As a result, TDX guest reads
the APIC timer at the same frequency, 25MHz.
While KVM's default emulated frequency for APIC bus is 1GHz, set the
APIC bus rate to match with TDX explicitly to ensure KVM provide correct
emulated APIC timer for TD guest.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-15-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 0e73b843616e52882940ab89e1b0e86e22be2162
https://github.com/qemu/qemu/commit/0e73b843616e52882940ab89e1b0e86e22be2162
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/kvm.c
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Implement user specified tsc frequency
Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency and call VM
scope VM_SET_TSC_KHZ to set the tsc frequency of TD before KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity (required by TDX module).
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-16-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 0dd5fe5ebeabefc7b3d7f043991b1edfe6b8eda9
https://github.com/qemu/qemu/commit/0dd5fe5ebeabefc7b3d7f043991b1edfe6b8eda9
Author: Chao Peng <chao.p.p...@linux.intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/x86-common.c
M target/i386/kvm/tdx.c
M target/i386/kvm/tdx.h
Log Message:
-----------
i386/tdx: load TDVF for TD guest
TDVF(OVMF) needs to run at private memory for TD guest. TDX cannot
support pflash device since it doesn't support read-only private memory.
Thus load TDVF(OVMF) with -bios option for TDs.
Use memory_region_init_ram_guest_memfd() to allocate the MemoryRegion
for TDVF because it needs to be located at private memory.
Also store the MemoryRegion pointer of TDVF since the shared ramblock of
it can be discared after it gets copied to private ramblock.
Signed-off-by: Chao Peng <chao.p.p...@linux.intel.com>
Co-developed-by: Xiaoyao Li <xiaoyao...@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-17-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: b65a6011d16c4f7cb2eb227ab1bc735850475288
https://github.com/qemu/qemu/commit/b65a6011d16c4f7cb2eb227ab1bc735850475288
Author: Isaku Yamahata <isaku.yamah...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/Kconfig
M hw/i386/meson.build
A hw/i386/tdvf.c
A include/hw/i386/tdvf.h
Log Message:
-----------
i386/tdvf: Introduce function to parse TDVF metadata
TDX VM needs to boot with its specialized firmware, Trusted Domain
Virtual Firmware (TDVF). QEMU needs to parse TDVF and map it in TD
guest memory prior to running the TDX VM.
A TDVF Metadata in TDVF image describes the structure of firmware.
QEMU refers to it to setup memory for TDVF. Introduce function
tdvf_parse_metadata() to parse the metadata from TDVF image and store
the info of each TDVF section.
TDX metadata is located by a TDX metadata offset block, which is a
GUID-ed structure. The data portion of the GUID structure contains
only an 4-byte field that is the offset of TDX metadata to the end
of firmware file.
Select X86_FW_OVMF when TDX is enable to leverage existing functions
to parse and search OVMF's GUID-ed structures.
Signed-off-by: Isaku Yamahata <isaku.yamah...@intel.com>
Co-developed-by: Xiaoyao Li <xiaoyao...@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-18-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: cb5d65a854e58abeb705a2ce14cc3eb28973c606
https://github.com/qemu/qemu/commit/cb5d65a854e58abeb705a2ce14cc3eb28973c606
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/pc_sysfw.c
M target/i386/kvm/tdx-stub.c
M target/i386/kvm/tdx.c
M target/i386/kvm/tdx.h
Log Message:
-----------
i386/tdx: Parse TDVF metadata for TDX VM
After TDVF is loaded to bios MemoryRegion, it needs parse TDVF metadata.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-19-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 49b1f0f812372129736c1df0421c8f67d86d362b
https://github.com/qemu/qemu/commit/49b1f0f812372129736c1df0421c8f67d86d362b
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
i386/tdx: Don't initialize pc.rom for TDX VMs
For TDX, the address below 1MB are entirely general RAM. No need to
initialize pc.rom memory region for TDs.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-20-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 4420ba0ebbf014acc68f78669e0767e288313ed6
https://github.com/qemu/qemu/commit/4420ba0ebbf014acc68f78669e0767e288313ed6
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/tdvf.c
M include/hw/i386/tdvf.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Track mem_ptr for each firmware entry of TDVF
For each TDVF sections, QEMU needs to copy the content to guest
private memory via KVM API (KVM_TDX_INIT_MEM_REGION).
Introduce a field @mem_ptr for TdxFirmwareEntry to track the memory
pointer of each TDVF sections. So that QEMU can add/copy them to guest
private memory later.
TDVF sections can be classified into two groups:
- Firmware itself, e.g., TDVF BFV and CFV, that located separately from
guest RAM. Its memory pointer is the bios pointer.
- Sections located at guest RAM, e.g., TEMP_MEM and TD_HOB.
mmap a new memory range for them.
Register a machine_init_done callback to do the stuff.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-21-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: f18672e4cf91feed4b91ef85a264a500935a2865
https://github.com/qemu/qemu/commit/f18672e4cf91feed4b91ef85a264a500935a2865
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
M target/i386/kvm/tdx.h
Log Message:
-----------
i386/tdx: Track RAM entries for TDX VM
The RAM of TDX VM can be classified into two types:
- TDX_RAM_UNACCEPTED: default type of TDX memory, which needs to be
accepted by TDX guest before it can be used and will be all-zeros
after being accepted.
- TDX_RAM_ADDED: the RAM that is ADD'ed to TD guest before running, and
can be used directly. E.g., TD HOB and TEMP MEM that needed by TDVF.
Maintain TdxRamEntries[] which grabs the initial RAM info from e820 table
and mark each RAM range as default type TDX_RAM_UNACCEPTED.
Then turn the range of TD HOB and TEMP MEM to TDX_RAM_ADDED since these
ranges will be ADD'ed before TD runs and no need to be accepted runtime.
The TdxRamEntries[] are later used to setup the memory TD resource HOB
that passes memory info from QEMU to TDVF.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-22-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 88aa6576e4ab40b538f543852128cb17fce37f87
https://github.com/qemu/qemu/commit/88aa6576e4ab40b538f543852128cb17fce37f87
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
A include/standard-headers/uefi/uefi.h
Log Message:
-----------
headers: Add definitions from UEFI spec for volumes, resources, etc...
Add UEFI definitions for literals, enums, structs, GUIDs, etc... that
will be used by TDX to build the UEFI Hand-Off Block (HOB) that is passed
to the Trusted Domain Virtual Firmware (TDVF).
All values come from the UEFI specification [1], PI spec [2] and TDVF
design guide[3].
[1] UEFI Specification v2.1.0
https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
[2] UEFI PI spec v1.8
https://uefi.org/sites/default/files/resources/UEFI_PI_Spec_1_8_March3.pdf
[3]
https://software.intel.com/content/dam/develop/external/us/en/documents/tdx-virtual-firmware-design-guide-rev-1.pdf
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-23-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: a731425980a4d3f8bb96fc41893b6437672875ee
https://github.com/qemu/qemu/commit/a731425980a4d3f8bb96fc41893b6437672875ee
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/meson.build
A hw/i386/tdvf-hob.c
A hw/i386/tdvf-hob.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Setup the TD HOB list
The TD HOB list is used to pass the information from VMM to TDVF. The TD
HOB must include PHIT HOB and Resource Descriptor HOB. More details can
be found in TDVF specification and PI specification.
Build the TD HOB in TDX's machine_init_done callback.
Co-developed-by: Isaku Yamahata <isaku.yamah...@intel.com>
Signed-off-by: Isaku Yamahata <isaku.yamah...@intel.com>
Co-developed-by: Sean Christopherson <sean.j.christopher...@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopher...@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-24-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ebc2d2b497c59414ac3c91de32bc546d27940e74
https://github.com/qemu/qemu/commit/ebc2d2b497c59414ac3c91de32bc546d27940e74
Author: Isaku Yamahata <isaku.yamah...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Add TDVF memory via KVM_TDX_INIT_MEM_REGION
TDVF firmware (CODE and VARS) needs to be copied to TD's private
memory via KVM_TDX_INIT_MEM_REGION, as well as TD HOB and TEMP memory.
If the TDVF section has TDVF_SECTION_ATTRIBUTES_MR_EXTEND set in the
flag, calling KVM_TDX_EXTEND_MEMORY to extend the measurement.
After populating the TDVF memory, the original image located in shared
ramblock can be discarded.
Signed-off-by: Isaku Yamahata <isaku.yamah...@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-25-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 41f7fd22073561a23229c0479d9d708dee9d3a1e
https://github.com/qemu/qemu/commit/41f7fd22073561a23229c0479d9d708dee9d3a1e
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Call KVM_TDX_INIT_VCPU to initialize TDX vcpu
TDX vcpu needs to be initialized by SEAMCALL(TDH.VP.INIT) and KVM
provides vcpu level IOCTL KVM_TDX_INIT_VCPU for it.
KVM_TDX_INIT_VCPU needs the address of the HOB as input. Invoke it for
each vcpu after HOB list is created.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-26-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ae60ff4e9f9e5790f79abf866ec67270c28ca477
https://github.com/qemu/qemu/commit/ae60ff4e9f9e5790f79abf866ec67270c28ca477
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Finalize TDX VM
Invoke KVM_TDX_FINALIZE_VM to finalize the TD's measurement and make
the TD vCPUs runnable once machine initialization is complete.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-27-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 1ff5048d74e661943260c33e864c4118acb37ab4
https://github.com/qemu/qemu/commit/1ff5048d74e661943260c33e864c4118acb37ab4
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Enable user exit on KVM_HC_MAP_GPA_RANGE
KVM translates TDG.VP.VMCALL<MapGPA> to KVM_HC_MAP_GPA_RANGE, and QEMU
needs to enable user exit on KVM_HC_MAP_GPA_RANGE in order to handle the
memory conversion requested by TD guest.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-28-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 98dbfd6849f117de02ac6f513f2a1f95563e60ae
https://github.com/qemu/qemu/commit/98dbfd6849f117de02ac6f513f2a1f95563e60ae
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/kvm.c
M target/i386/kvm/tdx-stub.c
M target/i386/kvm/tdx.c
M target/i386/kvm/tdx.h
Log Message:
-----------
i386/tdx: Handle KVM_SYSTEM_EVENT_TDX_FATAL
TD guest can use TDG.VP.VMCALL<REPORT_FATAL_ERROR> to request
termination. KVM translates such request into KVM_EXIT_SYSTEM_EVENT with
type of KVM_SYSTEM_EVENT_TDX_FATAL.
Add hanlder for such exit. Parse and print the error message, and
terminate the TD guest in the handler.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-29-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 6e250463b08b4028123f201343ee72099ef81e68
https://github.com/qemu/qemu/commit/6e250463b08b4028123f201343ee72099ef81e68
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M qapi/run-state.json
M system/runstate.c
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Wire TDX_REPORT_FATAL_ERROR with GuestPanic facility
Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility
Originated-from: Isaku Yamahata <isaku.yamah...@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Markus Armbruster <arm...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-30-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 77b5403a0298a5460554f768a2098fd21588e555
https://github.com/qemu/qemu/commit/77b5403a0298a5460554f768a2098fd21588e555
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
kvm: Check KVM_CAP_MAX_VCPUS at vm level
KVM with TDX support starts to report different KVM_CAP_MAX_VCPUS per
different VM types. So switch to check the KVM_CAP_MAX_VCPUS at vm level.
KVM still returns the global KVM_CAP_MAX_VCPUS when the KVM is old that
doesn't report different value at vm level.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-31-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 8583c53e2b619b1b9569d3f2d3f3cb2904a573ad
https://github.com/qemu/qemu/commit/8583c53e2b619b1b9569d3f2d3f3cb2904a573ad
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/confidential-guest.h
M target/i386/cpu.c
Log Message:
-----------
i386/cpu: introduce x86_confidential_guest_cpu_instance_init()
To allow execute confidential guest specific cpu init operations.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-32-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 7c615242671dbe65e198c20889dcaa9b4b9a1624
https://github.com/qemu/qemu/commit/7c615242671dbe65e198c20889dcaa9b4b9a1624
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: implement tdx_cpu_instance_init()
Currently, pmu is not supported for TDX by KVM.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-33-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ab8bd85adf75900edc2764d0ebe8b53867cc54aa
https://github.com/qemu/qemu/commit/ab8bd85adf75900edc2764d0ebe8b53867cc54aa
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
Log Message:
-----------
i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f
Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
when topology level that cannot be enumerated by leaf 0xB, e.g., die or
module level, are configured for the guest, e.g., -smp xx,dies=2.
However, TDX architecture forces to require CPUID 0x1f to configure CPU
topology.
Introduce a bool flag, enable_cpuid_0x1f, in CPU for the case that
requires CPUID leaf 0x1f to be exposed to guest.
Introduce a new function x86_has_cpuid_0x1f(), which is the wrapper of
cpu->enable_cpuid_0x1f and x86_has_extended_topo() to check if it needs
to enable cpuid leaf 0x1f for the guest.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-34-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 9002494f80b751a7655045c5f46bf90bc1d3bbd0
https://github.com/qemu/qemu/commit/9002494f80b751a7655045c5f46bf90bc1d3bbd0
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Force exposing CPUID 0x1f
TDX uses CPUID 0x1f to configure TD guest's CPU topology. So set
enable_cpuid_0x1f for TDs.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-35-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: da6728658bf63d6a3989f1587a33566b3e54bed8
https://github.com/qemu/qemu/commit/da6728658bf63d6a3989f1587a33566b3e54bed8
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Set kvm_readonly_mem_enabled to false for TDX VM
TDX only supports readonly for shared memory but not for private memory.
In the view of QEMU, it has no idea whether a memslot is used as shared
memory of private. Thus just mark kvm_readonly_mem_enabled to false to
TDX VM for simplicity.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-36-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 810d4e83d07ca0d072205453a42c324a51d5a5fa
https://github.com/qemu/qemu/commit/810d4e83d07ca0d072205453a42c324a51d5a5fa
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Disable SMM for TDX VMs
TDX doesn't support SMM and VMM cannot emulate SMM for TDX VMs because
VMM cannot manipulate TDX VM's memory.
Disable SMM for TDX VMs and error out if user requests to enable SMM.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-37-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: e7ef60892c80a9ce5b8504ceb13a81f4e0d4b3f7
https://github.com/qemu/qemu/commit/e7ef60892c80a9ce5b8504ceb13a81f4e0d4b3f7
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Disable PIC for TDX VMs
Legacy PIC (8259) cannot be supported for TDX VMs since TDX module
doesn't allow directly interrupt injection. Using posted interrupts
for the PIC is not a viable option as the guest BIOS/kernel will not
do EOI for PIC IRQs, i.e. will leave the vIRR bit set.
Hence disable PIC for TDX VMs and error out if user wants PIC.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-38-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: bb45580d842530d78b58179eaf80b6331b15324e
https://github.com/qemu/qemu/commit/bb45580d842530d78b58179eaf80b6331b15324e
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Set and check kernel_irqchip mode for TDX
KVM mandates kernel_irqchip to be split mode.
Set it to split mode automatically when users don't provide an explicit
value, otherwise check it to be the split mode.
Suggested-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-39-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 0ed55865b49b703af93e160d48935812a7114e07
https://github.com/qemu/qemu/commit/0ed55865b49b703af93e160d48935812a7114e07
Author: Isaku Yamahata <isaku.yamah...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386/tdx: Don't synchronize guest tsc for TDs
TSC of TDs is not accessible and KVM doesn't allow access of
MSR_IA32_TSC for TDs. To avoid the assert() in kvm_get_tsc, make
kvm_synchronize_all_tsc() noop for TDs,
Signed-off-by: Isaku Yamahata <isaku.yamah...@intel.com>
Reviewed-by: Connor Kuehl <cku...@redhat.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-40-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: f9aaad3362a5886d78e7d4d50d563ac16c6acdde
https://github.com/qemu/qemu/commit/f9aaad3362a5886d78e7d4d50d563ac16c6acdde
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386/tdx: Only configure MSR_IA32_UCODE_REV in kvm_init_msrs() for TDs
For TDs, only MSR_IA32_UCODE_REV in kvm_init_msrs() can be configured
by VMM, while the features enumerated/controlled by other MSRs except
MSR_IA32_UCODE_REV in kvm_init_msrs() are not under control of VMM.
Only configure MSR_IA32_UCODE_REV for TDs.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Acked-by: Gerd Hoffmann <kra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-41-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 62a1a8b89d90cd3fbee0e6d38e6a4c0d833e978a
https://github.com/qemu/qemu/commit/62a1a8b89d90cd3fbee0e6d38e6a4c0d833e978a
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M hw/i386/kvm/apic.c
Log Message:
-----------
i386/apic: Skip kvm_apic_put() for TDX
KVM neithers allow writing to MSR_IA32_APICBASE for TDs, nor allow for
KVM_SET_LAPIC[*].
Note, KVM_GET_LAPIC is also disallowed for TDX. It is called in the path
do_kvm_cpu_synchronize_state()
-> kvm_arch_get_registers()
-> kvm_get_apic()
and it's already disllowed for confidential guest through
guest_state_protected.
[*] https://lore.kernel.org/all/z3w4ku4jq0crt...@google.com/
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-42-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: b4b7fb5a773e1d2215c2aaa99789eca51914b78f
https://github.com/qemu/qemu/commit/b4b7fb5a773e1d2215c2aaa99789eca51914b78f
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
cpu: Don't set vcpu_dirty when guest_state_protected
QEMU calls kvm_arch_put_registers() when vcpu_dirty is true in
kvm_vcpu_exec(). However, for confidential guest, like TDX, putting
registers is disallowed due to guest state is protected.
Only set vcpu_dirty to true with guest state is not protected when
creating the vcpu.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-43-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 695bfaee7153153708228946aa26c6d879599c04
https://github.com/qemu/qemu/commit/695bfaee7153153708228946aa26c6d879599c04
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/confidential-guest.h
M target/i386/kvm/kvm.c
M target/i386/sev.c
Log Message:
-----------
i386/cgs: Rename *mask_cpuid_features() to *adjust_cpuid_features()
Because for TDX case, there are also fixed-1 bits that enforced by TDX
module.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-44-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 75ec6189f5c65cab210dd9f16cf4eef368038d45
https://github.com/qemu/qemu/commit/75ec6189f5c65cab210dd9f16cf4eef368038d45
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Implement adjust_cpuid_features() for TDX
Maintain a TDX specific supported CPUID set, and use it to mask the
common supported CPUID value of KVM. It can avoid newly added supported
features (reported via KVM_GET_SUPPORTED_CPUID) for common VMs being
falsely reported as supported for TDX.
As the first step, initialize the TDX supported CPUID set with all the
configurable CPUID bits. It's not complete because there are other CPUID
bits are supported for TDX but not reported as directly configurable.
E.g. the XFAM related bits, attribute related bits and fixed-1 bits.
They will be handled in the future.
Also, what matters are the CPUID bits related to QEMU's feature word.
Only mask the CPUID leafs which are feature word leaf.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-45-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 0ba06e46d09b84a2cb97a268da5576aaca3a24ca
https://github.com/qemu/qemu/commit/0ba06e46d09b84a2cb97a268da5576aaca3a24ca
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.h
M target/i386/kvm/kvm_i386.h
M target/i386/kvm/tdx.c
M target/i386/sev.c
Log Message:
-----------
i386/tdx: Add TDX fixed1 bits to supported CPUIDs
TDX architecture forcibly sets some CPUID bits for TD guest that VMM
cannot disable it. They are fixed1 bits.
Fixed1 bits are not covered by tdx_caps.cpuid (which only contains the
directly configurable bits), while fixed1 bits are supported for TD guest
obviously.
Add fixed1 bits to tdx_supported_cpuid. Besides, set all the fixed1
bits to the initial set of KVM's support since KVM might not report them
as supported.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-46-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 31df29c532a9ef473c6efd497950a620099bf1da
https://github.com/qemu/qemu/commit/31df29c532a9ef473c6efd497950a620099bf1da
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Add supported CPUID bits related to TD Attributes
For TDX, some CPUID feature bit is configured via TD attributes. They
are not covered by tdx_caps.cpuid (which only contians the directly
configurable CPUID bits), but they are actually supported when the
related attributre bit is supported.
Note, LASS and KeyLocker are not supported by KVM for TDX, nor does
QEMU support it (see TDX_SUPPORTED_TD_ATTRS). They are defined in
tdx_attrs_maps[] for the completeness of the existing TD Attribute
bits that are related with CPUID features.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-47-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 8c94c84cb9e0140b48acc9c9d404525ca7ef7457
https://github.com/qemu/qemu/commit/8c94c84cb9e0140b48acc9c9d404525ca7ef7457
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Add supported CPUID bits relates to XFAM
Some CPUID bits are controlled by XFAM. They are not covered by
tdx_caps.cpuid (which only contians the directly configurable bits), but
they are actually supported when the related XFAM bit is supported.
Add these XFAM controlled bits to TDX supported CPUID bits based on the
supported_xfam.
Besides, incorporate the supported_xfam into the supported CPUID leaf of
0xD.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-48-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 9f5771c57dbe92d46361afd992a5851c846d0322
https://github.com/qemu/qemu/commit/9f5771c57dbe92d46361afd992a5851c846d0322
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Add XFD to supported bit of TDX
Just mark XFD as always supported for TDX. This simple solution relies
on the fact KVM will report XFD as 0 when it's not supported by the
hardware.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-49-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 4d6e288a350a977b0fb0613db952087928ccd93e
https://github.com/qemu/qemu/commit/4d6e288a350a977b0fb0613db952087928ccd93e
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Define supported KVM features for TDX
For TDX, only limited KVM PV features are supported.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-50-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: dc0b08b303ad34983b43936a4c978672e0f9a9d8
https://github.com/qemu/qemu/commit/dc0b08b303ad34983b43936a4c978672e0f9a9d8
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/confidential-guest.h
M target/i386/kvm/kvm.c
Log Message:
-----------
i386/cgs: Introduce x86_confidential_guest_check_features()
To do cgs specific feature checking. Note the feature checking in
x86_cpu_filter_features() is valid for non-cgs VMs. For cgs VMs like
TDX, what features can be supported has more restrictions.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-51-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 4a2fb19669bb41eee5b2fb8e5b5ba30e1daaeaf5
https://github.com/qemu/qemu/commit/4a2fb19669bb41eee5b2fb8e5b5ba30e1daaeaf5
Author: Lei Wang <lei4.w...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
i386: Remove unused parameter "uint32_t bit" in feature_word_description()
Parameter "uint32_t bit" is not used in function feature_word_description(),
so remove it.
Signed-off-by: Lei Wang <lei4.w...@intel.com>
Reviewed-by: Igor Mammedov <imamm...@redhat.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20241217123932.948789-2-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: adf25ad70f2f989e63c2cd3e9de4e38152d05e84
https://github.com/qemu/qemu/commit/adf25ad70f2f989e63c2cd3e9de4e38152d05e84
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Print CPUID subleaf info for unsupported feature
Some CPUID leaves have meaningful subleaf index. Print the subleaf info
in feature_word_description for CPUID features.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Eduardo Habkost <ehabk...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20241217123932.948789-3-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: e3d1a4a6d1d61cf5fbd0e4b389cfb3976093739f
https://github.com/qemu/qemu/commit/e3d1a4a6d1d61cf5fbd0e4b389cfb3976093739f
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Fetch and validate CPUID of TD guest
Use KVM_TDX_GET_CPUID to get the CPUIDs that are managed and enfored
by TDX module for TD guest. Check QEMU's configuration against the
fetched data.
Print wanring message when 1. a feature is not supported but requested
by QEMU or 2. QEMU doesn't want to expose a feature while it is enforced
enabled.
- If cpu->enforced_cpuid is not set, prints the warning message of both
1) and 2) and tweak QEMU's configuration.
- If cpu->enforced_cpuid is set, quit if any case of 1) or 2).
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-52-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: deb9db6fb789cfe80527b75983e86137589227a4
https://github.com/qemu/qemu/commit/deb9db6fb789cfe80527b75983e86137589227a4
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Don't treat SYSCALL as unavailable
On Intel CPU, the value of CPUID_EXT2_SYSCALL depends on the mode of
the vcpu. It's 0 outside 64-bit mode and 1 in 64-bit mode.
The initial state of TDX vcpu is 32-bit protected mode. At the time of
calling KVM_TDX_GET_CPUID, vcpu hasn't started running so the value read
is 0.
In reality, 64-bit mode should always be supported. So mark
CPUID_EXT2_SYSCALL always supported to avoid false warning.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-53-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: ea4867b911fc2f6d4c8bd50ec62f0dc0fa190fab
https://github.com/qemu/qemu/commit/ea4867b911fc2f6d4c8bd50ec62f0dc0fa190fab
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Make invtsc default on
Because it's fixed1 bit that enforced by TDX module.
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-54-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 907ee7b67e50a7eea2768c66e3ad67c9aa4ffd3c
https://github.com/qemu/qemu/commit/907ee7b67e50a7eea2768c66e3ad67c9aa4ffd3c
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/host-cpu.c
M target/i386/host-cpu.h
M target/i386/kvm/tdx.c
Log Message:
-----------
i386/tdx: Validate phys_bits against host value
For TDX guest, the phys_bits is not configurable and can only be
host/native value.
Validate phys_bits inside tdx_check_features().
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-55-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: dc1424319311f86449c6825ceec2364ee645a363
https://github.com/qemu/qemu/commit/dc1424319311f86449c6825ceec2364ee645a363
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M docs/system/confidential-guest-support.rst
A docs/system/i386/tdx.rst
M docs/system/target-i386.rst
Log Message:
-----------
docs: Add TDX documentation
Add docs/system/i386/tdx.rst for TDX support, and add tdx in
confidential-guest-support.rst
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-56-xiaoyao...@intel.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 1297b285cc3ffbd06dc3208fbecdb2d582c535dc
https://github.com/qemu/qemu/commit/1297b285cc3ffbd06dc3208fbecdb2d582c535dc
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M rust/hw/char/pl011/meson.build
M rust/meson.build
M rust/qemu-api-macros/meson.build
M rust/qemu-api/meson.build
Log Message:
-----------
rust: make declaration of dependent crates more consistent
Crates like "bilge" and "libc" can be shared by more than one directory,
so declare them directly in rust/meson.build. While at it, make their
variable names end with "_rs" and always add a subproject() statement
(as that pinpoints the error better if the subproject is missing and
cannot be downloaded).
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 397db937e85d7b9f5a6f0b30764786cef09d1ff3
https://github.com/qemu/qemu/commit/397db937e85d7b9f5a6f0b30764786cef09d1ff3
Author: Babu Moger <babu.mo...@amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Fix the cache properties.
Also add the missing RAS and SVM features bits on AMD
EPYC CPU models. The SVM feature bits are used in nested guests.
succor : Software uncorrectable error containment and recovery
capability.
overflow-recov : MCA overflow recovery support.
lbrv : LBR virtualization
tsc-scale : MSR based TSC rate control
vmcb-clean : VMCB clean bits
flushbyasid : Flush by ASID
pause-filter : Pause intercept filter
pfthreshold : PAUSE filter threshold
v-vmsave-vmload : Virtualized VMLOAD and VMSAVE
vgif : Virtualized GIF
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Reviewed-by: Maksim Davydov <davydov-...@yandex-team.ru>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link:
https://lore.kernel.org/r/515941861700d7066186c9600bc5d96a1741ef0c.1746734284.git.babu.mo...@amd.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 83d940e9700527ff080416ce2fa52ee1f4771d72
https://github.com/qemu/qemu/commit/83d940e9700527ff080416ce2fa52ee1f4771d72
Author: Babu Moger <babu.mo...@amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature
bits
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Fix these cache properties.
Also add the missing RAS and SVM features bits on AMD EPYC-Rome. The SVM
feature bits are used in nested guests.
succor : Software uncorrectable error containment and recovery
capability.
overflow-recov : MCA overflow recovery support.
lbrv : LBR virtualization
tsc-scale : MSR based TSC rate control
vmcb-clean : VMCB clean bits
flushbyasid : Flush by ASID
pause-filter : Pause intercept filter
pfthreshold : PAUSE filter threshold
v-vmsave-vmload : Virtualized VMLOAD and VMSAVE
vgif : Virtualized GIF
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Reviewed-by: Maksim Davydov <davydov-...@yandex-team.ru>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link:
https://lore.kernel.org/r/8265af72057b84c99ac3a02a5487e32759cc69b1.1746734284.git.babu.mo...@amd.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: fc014d9ba5b26b27401e0e88a4e1ef827c68fe64
https://github.com/qemu/qemu/commit/fc014d9ba5b26b27401e0e88a4e1ef827c68fe64
Author: Babu Moger <babu.mo...@amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature
bits
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Fix these cache properties.
Also add the missing RAS and SVM features bits on AMD EPYC-Milan model.
The SVM feature bits are used in nested guests.
succor : Software uncorrectable error containment and recovery
capability.
overflow-recov : MCA overflow recovery support.
lbrv : LBR virtualization
tsc-scale : MSR based TSC rate control
vmcb-clean : VMCB clean bits
flushbyasid : Flush by ASID
pause-filter : Pause intercept filter
pfthreshold : PAUSE filter threshold
v-vmsave-vmload : Virtualized VMLOAD and VMSAVE
vgif : Virtualized GIF
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Reviewed-by: Maksim Davydov <davydov-...@yandex-team.ru>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link:
https://lore.kernel.org/r/c619c0e09a9d5d496819ed48d69181d65f416891.1746734284.git.babu.mo...@amd.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: dfd5b456108a75588ab094358ba5754787146d3d
https://github.com/qemu/qemu/commit/dfd5b456108a75588ab094358ba5754787146d3d
Author: Babu Moger <babu.mo...@amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX
Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the indicates
support for IC prefetch.
CPUID_Fn80000021_EAX
Bit Feature description
20 Indicates support for IC prefetch.
1 FsGsKernelGsBaseNonSerializing.
WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing.
Link:
https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Reviewed-by: Maksim Davydov <davydov-...@yandex-team.ru>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link:
https://lore.kernel.org/r/a5f6283a59579b09ac345b3f21ecb3b3b2d92451.1746734284.git.babu.mo...@amd.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: abc92cc8488b5dbcc403b5be24d8092180605101
https://github.com/qemu/qemu/commit/abc92cc8488b5dbcc403b5be24d8092180605101
Author: Babu Moger <babu.mo...@amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM
feature bits
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Fix these cache properties.
Also add the missing RAS and SVM features bits on AMD EPYC-Genoa model.
The SVM feature bits are used in nested guests.
perfmon-v2 : Allow guests to make use of the PerfMonV2 features.
succor : Software uncorrectable error containment and recovery
capability.
overflow-recov : MCA overflow recovery support.
lbrv : LBR virtualization
tsc-scale : MSR based TSC rate control
vmcb-clean : VMCB clean bits
flushbyasid : Flush by ASID
pause-filter : Pause intercept filter
pfthreshold : PAUSE filter threshold
v-vmsave-vmload: Virtualized VMLOAD and VMSAVE
vgif : Virtualized GIF
fs-gs-base-ns : WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
The feature details are available in APM listed below [1].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Reviewed-by: Maksim Davydov <davydov-...@yandex-team.ru>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link:
https://lore.kernel.org/r/afe3f05d4116124fd5795f28fc23d7b396140313.1746734284.git.babu.mo...@amd.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 3771a4daa273ba17cb27309984413790d1df5651
https://github.com/qemu/qemu/commit/3771a4daa273ba17cb27309984413790d1df5651
Author: Babu Moger <babu.mo...@amd.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Add support for EPYC-Turin model
Add the support for AMD EPYC zen 5 processors (EPYC-Turin).
Add the following new feature bits on top of the feature bits from
the previous generation EPYC models.
movdiri : Move Doubleword as Direct Store Instruction
movdir64b : Move 64 Bytes as Direct Store Instruction
avx512-vp2intersect : AVX512 Vector Pair Intersection to a Pair
of Mask Register
avx-vnni : AVX VNNI Instruction
prefetchi : Indicates support for IC prefetch
sbpb : Selective Branch Predictor Barrier
ibpb-brtype : IBPB includes branch type prediction flushing
srso-user-kernel-no : Not vulnerable to SRSO at the user-kernel boundary
Link:
https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
Link:
https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
Signed-off-by: Babu Moger <babu.mo...@amd.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Link:
https://lore.kernel.org/r/b4fa7708a0e1453d2e9b8ec3dc881feb92eeca0b.1746734284.git.babu.mo...@amd.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 9bd24d8d2756a0771b6677b02c7f9b603ef6afe9
https://github.com/qemu/qemu/commit/9bd24d8d2756a0771b6677b02c7f9b603ef6afe9
Author: Fiona Ebner <f.eb...@proxmox.com>
Date: 2025-05-28 (Wed, 28 May 2025)
Changed paths:
M target/i386/tcg/helper-tcg.h
Log Message:
-----------
target/i386/tcg/helper-tcg: fix file references in comments
Commit 32cad1ffb8 ("include: Rename sysemu/ -> system/") renamed
target/i386/tcg/sysemu => target/i386/tcg/system.
Signed-off-by: Fiona Ebner <f.eb...@proxmox.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link: https://lore.kernel.org/r/20250526114447.1243840-1-f.eb...@proxmox.com
Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Commit: 638422f5bcdf2c7bdb401b987b134322c5d6bd4d
https://github.com/qemu/qemu/commit/638422f5bcdf2c7bdb401b987b134322c5d6bd4d
Author: Hao Wu <wuhao...@google.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M hw/arm/npcm8xx.c
M include/hw/arm/npcm8xx.h
Log Message:
-----------
hw/arm: Add GMAC devices to NPCM8XX SoC
The GMAC was originally created for the 8xx machine. During upstreaming
both the GMAC and the 8XX we removed it so they would not depend on each
other for the process, that connection should be added back in.
Signed-off-by: Hao Wu <wuhao...@google.com>
Signed-off-by: Nabih Estefan <nabiheste...@google.com>
Message-id: 20250508220718.735415-2-nabiheste...@google.com
Reviewed-by: Tyrone Ting <kft...@nuvoton.com>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e7083b02f5628f0ec63d29f2208ca5d3e963e9a8
https://github.com/qemu/qemu/commit/e7083b02f5628f0ec63d29f2208ca5d3e963e9a8
Author: Nabih Estefan <nabiheste...@google.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M tests/qtest/meson.build
M tests/qtest/npcm_gmac-test.c
Log Message:
-----------
tests/qtest: Migrate GMAC test from 7xx to 8xx
For upstreaming we migrated this test to 7xx (since that was already
upstream) move it back to 8xx where it can check the 4 GMACs since that
is the board this test was originally created for.
Signed-off-by: Nabih Estefan <nabiheste...@google.com>
Message-id: 20250508220718.735415-3-nabiheste...@google.com
Reviewed-by: Tyrone Ting <kft...@nuvoton.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e6bc01777e5a4b6ecf3414b21a2d7b4846bf4817
https://github.com/qemu/qemu/commit/e6bc01777e5a4b6ecf3414b21a2d7b4846bf4817
Author: Guenter Roeck <li...@roeck-us.net>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M hw/arm/npcm8xx.c
Log Message:
-----------
hw/arm: Add missing psci_conduit to NPCM8XX SoC boot info
Without psci_conduit, the Linux kernel crashes almost immediately.
psci: probing for conduit method from DT.
Internal error: Oops - Undefined instruction: 0000000002000000 [#1] PREEMPT
SMP
Fixes: ae0c4d1a1290 ("hw/arm: Add NPCM8XX SoC")
Cc: qemu-sta...@nongnu.org
Cc: Hao Wu <wuhao...@google.com>
Cc: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Message-id: 20250315142050.3642741-1-li...@roeck-us.net
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 0a233da8a02a6126140b9dbd3af29e6763a390b1
https://github.com/qemu/qemu/commit/0a233da8a02a6126140b9dbd3af29e6763a390b1
Author: Souleymane Conte <conte.souleym...@gmail.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M MAINTAINERS
M docs/interop/bitmaps.rst
M docs/interop/index.rst
A docs/interop/qcow2.rst
R docs/interop/qcow2.txt
M docs/qcow2-cache.txt
Log Message:
-----------
docs/interop: convert text files to restructuredText
buglink: https://gitlab.com/qemu-project/qemu/-/issues/527
Signed-off-by: Souleymane Conte <conte.souleym...@gmail.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Eric Blake <ebl...@redhat.com>
Message-id: 20250522092622.40869-1-conte.souleym...@gmail.com
[PMM: switched a few more bits of formatting to monospaced;
updated references to qcow2.txt in MAINTAINERS, qcow2-cache.txt
and bitmaps.rst]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 4f8599f20c4a54cefc626b50dc7392dd82b422f9
https://github.com/qemu/qemu/commit/4f8599f20c4a54cefc626b50dc7392dd82b422f9
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M target/arm/meson.build
Log Message:
-----------
target/arm/tcg-stubs: compile file once (system)
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250513173928.77376-2-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: f1bcfa81d84c2a7401f6dcbf8fc1c7b26ec18213
https://github.com/qemu/qemu/commit/f1bcfa81d84c2a7401f6dcbf8fc1c7b26ec18213
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M MAINTAINERS
A target/arm/hvf-stub.c
M target/arm/hvf_arm.h
M target/arm/meson.build
Log Message:
-----------
target/arm/hvf_arm: Avoid using poisoned CONFIG_HVF definition
In order to allow non-target specific code to include
"hvf_arm.h", define the stubs in hvf-stub.c.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250513173928.77376-3-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 54d1046f939c2c508a6b73531af83345306ecaa9
https://github.com/qemu/qemu/commit/54d1046f939c2c508a6b73531af83345306ecaa9
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M target/arm/meson.build
M target/arm/tcg/meson.build
Log Message:
-----------
target/arm: Only link with zlib when TCG is enabled
Since commit 538b764d341 ("target/arm: Move minor arithmetic
helpers out of helper.c") we only use the zlib helpers under
TCG.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250513173928.77376-4-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 982a42c773efc7767e33d618f0fe4fcaef716a57
https://github.com/qemu/qemu/commit/982a42c773efc7767e33d618f0fe4fcaef716a57
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M target/arm/cpregs.h
Log Message:
-----------
target/arm/cpregs: Include missing 'target/arm/cpu.h' header
CPReadFn type definitions use the CPUARMState type, itself
declared in "cpu.h". Include this file in order to avoid when
refactoring headers:
../target/arm/cpregs.h:241:27: error: unknown type name 'CPUARMState'
typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
^
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250513173928.77376-5-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: c28900fbcdc36175a1fc81015e952133007ae864
https://github.com/qemu/qemu/commit/c28900fbcdc36175a1fc81015e952133007ae864
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Include missing 'system/memory.h' header
default_reset_secondary() uses address_space_stl_notdirty(),
itself declared in "system/memory.h". Include this header in
order to avoid when refactoring headers:
../hw/arm/boot.c:281:5: error: implicit declaration of function
'address_space_stl_notdirty' is invalid in C99
[-Werror,-Wimplicit-function-declaration]
address_space_stl_notdirty(as, info->smp_bootreg_addr,
^
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250513173928.77376-6-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: fe5aa1cfe22c71c80e544cf97741036cba0556d7
https://github.com/qemu/qemu/commit/fe5aa1cfe22c71c80e544cf97741036cba0556d7
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M target/arm/cpu-features.h
Log Message:
-----------
target/arm/cpu-features: Include missing 'cpu.h' header
"target/arm/cpu-features.h" dereferences the ARMISARegisters
structure, which is defined in "cpu.h". Include the latter to
avoid when refactoring unrelated headers:
In file included from target/arm/internals.h:33:
target/arm/cpu-features.h:45:54: error: unknown type name 'ARMISARegisters'
45 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters
*id)
| ^
target/arm/cpu-features.h:47:12: error: use of undeclared identifier
'R_ID_ISAR0_DIVIDE_SHIFT'
47 | return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
| ^
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250513173928.77376-7-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e0f224ec077d90c10288a4f73d01a264b0364e46
https://github.com/qemu/qemu/commit/e0f224ec077d90c10288a4f73d01a264b0364e46
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M target/arm/arm-qmp-cmds.c
Log Message:
-----------
target/arm/qmp: Include missing 'cpu.h' header
arm-qmp-cmds.c uses ARM_MAX_VQ, which is defined in "cpu.h".
Include the latter to avoid when refactoring unrelated headers:
target/arm/arm-qmp-cmds.c:83:19: error: use of undeclared identifier
'ARM_MAX_VQ'
83 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
| ^
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250513173928.77376-8-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 3d28b2ce00e8b5e74e1f5cbba13cf306b8360762
https://github.com/qemu/qemu/commit/3d28b2ce00e8b5e74e1f5cbba13cf306b8360762
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M target/arm/kvm_arm.h
Log Message:
-----------
target/arm/kvm: Include missing 'cpu-qom.h' header
ARMCPU typedef is declared in "cpu-qom.h". Include it in
order to avoid when refactoring unrelated headers:
target/arm/kvm_arm.h:54:29: error: unknown type name 'ARMCPU'
54 | bool write_list_to_kvmstate(ARMCPU *cpu, int level);
| ^
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250513173928.77376-9-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: c42300ef71ba103a9bf67ca64cb94d5d9b633175
https://github.com/qemu/qemu/commit/c42300ef71ba103a9bf67ca64cb94d5d9b633175
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M target/arm/hvf_arm.h
Log Message:
-----------
target/arm/hvf: Include missing 'cpu-qom.h' header
ARMCPU typedef is declared in "cpu-qom.h". Include it in
order to avoid when refactoring unrelated headers:
target/arm/hvf_arm.h:23:41: error: unknown type name 'ARMCPU'
23 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu);
| ^
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250513173928.77376-10-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 96778e69a2e391e5dc99d2318e7830695c607795
https://github.com/qemu/qemu/commit/96778e69a2e391e5dc99d2318e7830695c607795
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M MAINTAINERS
M tests/functional/meson.build
A tests/functional/test_arm_stellaris.py
Log Message:
-----------
tests/functional: Add a test for the Stellaris arm machines
The 2023 edition of the QEMU advent calendar featured an image
that we can use to test whether the lm3s6965evb machine is basically
still working.
And for the lm3s811evb there is a small test kernel on github
which can be used to check its UART.
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-id: 20250519170242.520805-1-th...@redhat.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e86c1f967a323165d13bcadfad4b92d0d34cdb08
https://github.com/qemu/qemu/commit/e86c1f967a323165d13bcadfad4b92d0d34cdb08
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M hw/arm/Kconfig
M hw/block/Kconfig
M hw/block/meson.build
R hw/block/nand.c
M include/hw/block/flash.h
Log Message:
-----------
hw/block: Drop unused nand.c
The nand.c device (TYPE_NAND) is an emulation of a NAND flash memory
chip which was used by the old OMAP boards. No current QEMU board
uses it, and although techically "-device nand,chip-id=0x6b" doesn't
error out, it's not possible to usefully use it from the command
line because the only interface it has is via calling C functions
like nand_setpins() and nand_setio().
The "config OMAP" stanza (used only by the SX1 board) is the only
thing that does "select NAND" to compile in this code, but the SX1
board doesn't actually use the NAND device.
Remove the NAND device code entirely; this is effectively leftover
cleanup from when we dropped the PXA boards and the OMAP boards
other than the sx1.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250522142859.3122389-1-peter.mayd...@linaro.org
Commit: e2e360db7a55afd62e77577a965f6aa224132cef
https://github.com/qemu/qemu/commit/e2e360db7a55afd62e77577a965f6aa224132cef
Author: Nir Soffer <nir...@gmail.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M include/io/channel-socket.h
M io/channel-socket.c
Log Message:
-----------
io: Add helper for setting socket send buffer size
Testing reading and writing from qemu-nbd using a unix domain socket
shows that the platform default send buffer size is too low, leading to
poor performance and hight cpu usage.
Add a helper for setting socket send buffer size to be used in NBD code.
It can also be used in other contexts.
We don't need a helper for receive buffer size since it is not used with
unix domain sockets. This is documented for Linux, and not documented
for macOS.
Failing to set the socket buffer size is not a fatal error, but the
caller may want to warn about the failure.
Signed-off-by: Nir Soffer <nir...@gmail.com>
Message-ID: <20250517201154.88456-2-nir...@gmail.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Eric Blake <ebl...@redhat.com>
Commit: e9f4550b74a8a9774979a51caa4b1aaff9e1d055
https://github.com/qemu/qemu/commit/e9f4550b74a8a9774979a51caa4b1aaff9e1d055
Author: Nir Soffer <nir...@gmail.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M nbd/client-connection.c
M nbd/common.c
M nbd/nbd-internal.h
M nbd/server.c
Log Message:
-----------
nbd: Set unix socket send buffer on macOS
On macOS we need to increase unix socket buffers size on the client and
server to get good performance. We set socket buffers on macOS after
connecting or accepting a client connection.
Testing shows that setting socket receive buffer size (SO_RCVBUF) has no
effect on performance, so we set only the send buffer size (SO_SNDBUF).
It seems to work like Linux but not documented.
Testing shows that optimal buffer size is 512k to 4 MiB, depending on
the test case. The difference is very small, so I chose 2 MiB.
I tested reading from qemu-nbd and writing to qemu-nbd with qemu-img and
computing a blkhash with nbdcopy and blksum.
To focus on NBD communication and get less noisy results, I tested
reading and writing to null-co driver. I added a read-pattern option to
the null-co driver to return data full of 0xff:
NULL="json:{'driver': 'raw', 'file': {'driver': 'null-co', 'size': '10g',
'read-pattern': 255}}"
For testing buffer size I added an environment variable for setting the
socket buffer size.
Read from qemu-nbd via qemu-img convert. In this test buffer size of 2m
is optimal (12.6 times faster).
qemu-nbd -r -t -e 0 -f raw -k /tmp/nbd.sock "$NULL" &
qemu-img convert -f raw -O raw -W -n "nbd+unix:///?socket=/tmp/nbd.sock"
"$NULL"
| buffer size | time | user | system |
|-------------|---------|---------|---------|
| default | 13.361 | 2.653 | 5.702 |
| 65536 | 2.283 | 0.204 | 1.318 |
| 131072 | 1.673 | 0.062 | 1.008 |
| 262144 | 1.592 | 0.053 | 0.952 |
| 524288 | 1.496 | 0.049 | 0.887 |
| 1048576 | 1.234 | 0.047 | 0.738 |
| 2097152 | 1.060 | 0.080 | 0.602 |
| 4194304 | 1.061 | 0.076 | 0.604 |
Write to qemu-nbd with qemu-img convert. In this test buffer size of 2m
is optimal (9.2 times faster).
qemu-nbd -t -e 0 -f raw -k /tmp/nbd.sock "$NULL" &
qemu-img convert -f raw -O raw -W -n "$NULL"
"nbd+unix:///?socket=/tmp/nbd.sock"
| buffer size | time | user | system |
|-------------|---------|---------|---------|
| default | 8.063 | 2.522 | 4.184 |
| 65536 | 1.472 | 0.430 | 0.867 |
| 131072 | 1.071 | 0.297 | 0.654 |
| 262144 | 1.012 | 0.239 | 0.587 |
| 524288 | 0.970 | 0.201 | 0.514 |
| 1048576 | 0.895 | 0.184 | 0.454 |
| 2097152 | 0.877 | 0.174 | 0.440 |
| 4194304 | 0.944 | 0.231 | 0.535 |
Compute a blkhash with nbdcopy, using 4 NBD connections and 256k request
size. In this test buffer size of 4m is optimal (5.1 times faster).
qemu-nbd -r -t -e 0 -f raw -k /tmp/nbd.sock "$NULL" &
nbdcopy --blkhash "nbd+unix:///?socket=/tmp/nbd.sock" null:
| buffer size | time | user | system |
|-------------|---------|---------|---------|
| default | 8.624 | 5.727 | 6.507 |
| 65536 | 2.563 | 4.760 | 2.498 |
| 131072 | 1.903 | 4.559 | 2.093 |
| 262144 | 1.759 | 4.513 | 1.935 |
| 524288 | 1.729 | 4.489 | 1.924 |
| 1048576 | 1.696 | 4.479 | 1.884 |
| 2097152 | 1.710 | 4.480 | 1.763 |
| 4194304 | 1.687 | 4.479 | 1.712 |
Compute a blkhash with blksum, using 1 NBD connection and 256k read
size. In this test buffer size of 512k is optimal (10.3 times faster).
qemu-nbd -r -t -e 0 -f raw -k /tmp/nbd.sock "$NULL" &
blksum "nbd+unix:///?socket=/tmp/nbd.sock"
| buffer size | time | user | system |
|-------------|---------|---------|---------|
| default | 13.085 | 5.664 | 6.461 |
| 65536 | 3.299 | 5.106 | 2.515 |
| 131072 | 2.396 | 4.989 | 2.069 |
| 262144 | 1.607 | 4.724 | 1.555 |
| 524288 | 1.271 | 4.528 | 1.224 |
| 1048576 | 1.294 | 4.565 | 1.333 |
| 2097152 | 1.299 | 4.569 | 1.344 |
| 4194304 | 1.291 | 4.559 | 1.327 |
Signed-off-by: Nir Soffer <nir...@gmail.com>
Message-ID: <20250517201154.88456-3-nir...@gmail.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Eric Blake <ebl...@redhat.com>
Commit: 479ec8106185d0e88d65539df5e940c781a82c53
https://github.com/qemu/qemu/commit/479ec8106185d0e88d65539df5e940c781a82c53
Author: Nir Soffer <nir...@gmail.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M nbd/common.c
Log Message:
-----------
nbd: Set unix socket send buffer on Linux
Like macOS we have similar issue on Linux. For TCP socket the send
buffer size is 2626560 bytes (~2.5 MiB) and we get good performance.
However for unix socket the default and maximum buffer size is 212992
bytes (208 KiB) and we see poor performance when using one NBD
connection, up to 4 times slower than macOS on the same machine.
Tracing shows that for every 2 MiB payload (qemu uses 2 MiB io size), we
do 1 recvmsg call with TCP socket, and 10 recvmsg calls with unix
socket.
Fixing this issue requires changing the maximum send buffer size (the
receive buffer size is ignored). This can be done using:
$ cat /etc/sysctl.d/net-mem-max.conf
net.core.wmem_max = 2097152
$ sudo sysctl -p /etc/sysctl.d/net-mem-max.conf
With this we can set the socket buffer size to 2 MiB. With the defaults
the value requested by qemu is clipped to the maximum size and has no
effect.
I tested on 2 machines:
- Fedora 42 VM on MacBook Pro M2 Max
- Dell PowerEdge R640 (Intel(R) Xeon(R) Gold 6230 CPU @ 2.10GHz)
On the older Dell machine we see very little improvement, up to 1.03
higher throughput. On the M2 machine we see up to 2.67 times higher
throughput. The following results are from the M2 machine.
Reading from qemu-nbd with qemu-img convert. In this test buffer size of
4m is optimal (2.28 times faster).
| buffer size | time | user | system |
|-------------|---------|---------|---------|
| default | 4.292 | 0.243 | 1.604 |
| 524288 | 2.167 | 0.058 | 1.288 |
| 1048576 | 2.041 | 0.060 | 1.238 |
| 2097152 | 1.884 | 0.060 | 1.191 |
| 4194304 | 1.881 | 0.054 | 1.196 |
Writing to qemu-nbd with qemu-img convert. In this test buffer size of
1m is optimal (2.67 times faster).
| buffer size | time | user | system |
|-------------|---------|---------|---------|
| default | 3.113 | 0.334 | 1.094 |
| 524288 | 1.173 | 0.179 | 0.654 |
| 1048576 | 1.164 | 0.164 | 0.670 |
| 2097152 | 1.227 | 0.197 | 0.663 |
| 4194304 | 1.227 | 0.198 | 0.666 |
Computing a blkhash with nbdcopy. In this test buffer size of 512k is
optimal (1.19 times faster).
| buffer size | time | user | system |
|-------------|---------|---------|---------|
| default | 2.140 | 4.483 | 2.681 |
| 524288 | 1.794 | 4.467 | 2.572 |
| 1048576 | 1.807 | 4.447 | 2.644 |
| 2097152 | 1.822 | 4.461 | 2.698 |
| 4194304 | 1.827 | 4.465 | 2.700 |
Computing a blkhash with blksum. In this test buffer size of 4m is
optimal (2.65 times faster).
| buffer size | time | user | system |
|-------------|---------|---------|---------|
| default | 3.582 | 4.595 | 2.392 |
| 524288 | 1.499 | 4.384 | 1.482 |
| 1048576 | 1.377 | 4.381 | 1.345 |
| 2097152 | 1.388 | 4.389 | 1.354 |
| 4194304 | 1.352 | 4.395 | 1.302 |
Signed-off-by: Nir Soffer <nir...@gmail.com>
Message-ID: <20250517201154.88456-4-nir...@gmail.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Eric Blake <ebl...@redhat.com>
Commit: d2b3e32bf7395c710ba44585520d837f6330fa70
https://github.com/qemu/qemu/commit/d2b3e32bf7395c710ba44585520d837f6330fa70
Author: Eric Blake <ebl...@redhat.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M tests/qemu-iotests/125
M tests/qemu-iotests/308
Log Message:
-----------
iotests: Use disk_usage in more places
Commit be9bac07 added a utility disk_usage function, but there are
a couple of other tests that could also use it.
Signed-off-by: Eric Blake <ebl...@redhat.com>
Message-ID: <20250523163041.2548675-6-ebl...@redhat.com>
Reviewed-by: Fiona Ebner <f.eb...@proxmox.com>
Tested-by: Fiona Ebner <f.eb...@proxmox.com>
Commit: ed1c336119c084159575ae9d4fd9171bd500f7e4
https://github.com/qemu/qemu/commit/ed1c336119c084159575ae9d4fd9171bd500f7e4
Author: Eric Blake <ebl...@redhat.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M tests/qemu-iotests/tests/mirror-sparse
Log Message:
-----------
iotests: Improve mirror-sparse on ext4 and xfs
Fiona reported that an ext4 filesystem on top of LVM can sometimes
report over-allocation to du (based on the heuristics the filesystem
is making while observing the contents being mirrored); even though
the contents and actual size matched, about 50% of the time the size
reported by disk_usage was too large by 4k, failing the test. In
auditing other iotests, this is a common problem we've had to deal
with.
Meanwhile, Markus reported that an xfs filesystem reports disk usage
at a default granularity of 1M (so the sparse file occupies 3M, since
it has just over 2M data).
Reported-by: Fiona Ebner <f.eb...@proxmox.com>
Reported-by: Markus Armbruster <arm...@redhat.com>
Fixes: c0ddcb2c ("tests: Add iotest mirror-sparse for recent patches")
Signed-off-by: Eric Blake <ebl...@redhat.com>
Reviewed-by: Fiona Ebner <f.eb...@proxmox.com>
Tested-by: Fiona Ebner <f.eb...@proxmox.com>
Message-ID: <20250523163041.2548675-7-ebl...@redhat.com>
[eblake: Also fix xfs issue]
Signed-off-by: Eric Blake <ebl...@redhat.com>
Commit: c49dda7254d43d9e1d4da59c55f02055ba7c4c1b
https://github.com/qemu/qemu/commit/c49dda7254d43d9e1d4da59c55f02055ba7c4c1b
Author: Eric Blake <ebl...@redhat.com>
Date: 2025-05-29 (Thu, 29 May 2025)
Changed paths:
M tests/qemu-iotests/106
M tests/qemu-iotests/175
M tests/qemu-iotests/221
M tests/qemu-iotests/253
M tests/qemu-iotests/308
M tests/qemu-iotests/common.rc
M tests/qemu-iotests/tests/mirror-sparse
M tests/qemu-iotests/tests/write-zeroes-unmap
Log Message:
-----------
iotests: Filter out ZFS in several tests
Fiona reported that ZFS makes sparse file testing awkward, since:
- it has asynchronous allocation (not even 'fsync $file' makes du see
the desired size; it takes the slower 'fsync -f $file' which is not
appropriate for the tests)
- for tests of fully allocated files, ZFS with compression enabled
still reports smaller disk usage
Add a new _require_disk_usage that quickly probes whether an attempt
to create a sparse 5M file shows as less than 1M usage, while the same
file with -o preallocation=full shows as more than 4M usage without
sync, which should filter out ZFS behavior. Then use it in various
affected tests.
This does not add the new filter on all tests that Fiona is seeing ZFS
failures on, but only those where I could quickly spot that there is
at least one place where the test depends on the output of 'du -b' or
'stat -c %b'.
Reported-by: Fiona Ebner <f.eb...@proxmox.com>
Signed-off-by: Eric Blake <ebl...@redhat.com>
Message-ID: <20250523163041.2548675-8-ebl...@redhat.com>
Reviewed-by: Fiona Ebner <f.eb...@proxmox.com>
Tested-by: Fiona Ebner <f.eb...@proxmox.com>
Commit: e1c9c801023d556d317256a414562634b1fe8b13
https://github.com/qemu/qemu/commit/e1c9c801023d556d317256a414562634b1fe8b13
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M tests/functional/test_sparc64_tuxrun.py
Log Message:
-----------
tests/functional/test_sparc64_tuxrun: Explicitly set the 'sun4u' machine
Use self.set_machine() to set the machine instead of relying on the
default machine of the binary. This way the test can be skipped in
case the machine has not been compiled into the QEMU binary.
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250521145112.142222-1-th...@redhat.com>
Commit: 644ded5c814055feb4d3a546628ccd28102f7acb
https://github.com/qemu/qemu/commit/644ded5c814055feb4d3a546628ccd28102f7acb
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M tests/functional/test_mips_malta.py
Log Message:
-----------
tests/functional/test_mips_malta: Re-enable the check for the PCI host bridge
The problem with the PCI bridge has been fixed in commit e5894fd6f411c1
("hw/pci-host/gt64120: Fix endianness handling"), so we can enable the
corresponding test again.
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250522080208.205489-1-th...@redhat.com>
Commit: 9f7cf938efc6016f7ce323b064c2f3f46360c751
https://github.com/qemu/qemu/commit/9f7cf938efc6016f7ce323b064c2f3f46360c751
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M tests/functional/test_mem_addr_space.py
Log Message:
-----------
tests/functional/test_mem_addr_space: Use set_machine() to select the machine
By using self.set_machine() the tests get properly skipped in case
the machine has not been compiled into the QEMU binary, e.g. when
"configure" has been run with "--without-default-devices".
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250521143732.140711-1-th...@redhat.com>
Commit: 141ec228deb7f94fb713c4d7ce0276e088e59f15
https://github.com/qemu/qemu/commit/141ec228deb7f94fb713c4d7ce0276e088e59f15
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/microblaze/petalogix_s3adsp1800_mmu.c
Log Message:
-----------
hw/microblaze: Add endianness property to the petalogix_s3adsp1800 machine
Since the microblaze target can now handle both endianness, big and
little, we should provide a config knob for the user to select the
desired endianness.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250515132019.569365-2-th...@redhat.com>
Commit: 6c5477558490cf76dc6d521fe906a2bfbc96ee27
https://github.com/qemu/qemu/commit/6c5477558490cf76dc6d521fe906a2bfbc96ee27
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M tests/functional/test_microblaze_s3adsp1800.py
M tests/functional/test_microblazeel_s3adsp1800.py
Log Message:
-----------
tests/functional: Test both microblaze s3adsp1800 endianness variants
Now that the endianness of the petalogix-s3adsp1800 can be configured,
we should test that the cross-endianness also works as expected, thus
test the big endian variant on the little endian target and vice versa.
(based on an original idea from Philippe Mathieu-Daudé)
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250515132019.569365-3-th...@redhat.com>
Commit: 0e259fa5a13a3d0ff65aa4199b1e03832e51e1b2
https://github.com/qemu/qemu/commit/0e259fa5a13a3d0ff65aa4199b1e03832e51e1b2
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/microblaze/petalogix_ml605_mmu.c
M hw/microblaze/xlnx-zynqmp-pmu.c
Log Message:
-----------
hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu
Both machines were added with little-endian in mind only (the
"endianness" CPU property was hard-wired to "true", see commits
133d23b3ad1 and a88bbb006a52), so the variants that showed up
on the big endian target likely never worked. We deprecated these
non-working machine variants two releases ago, and so far nobody
complained, so it should be fine now to disable them. Hard-wire
the machines to little endian now.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250515132019.569365-4-th...@redhat.com>
Commit: 225e9e230efd5ae509b12fd191a8de6287f934ef
https://github.com/qemu/qemu/commit/225e9e230efd5ae509b12fd191a8de6287f934ef
Author: Thomas Huth <th...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M docs/about/deprecated.rst
Log Message:
-----------
docs: Deprecate the qemu-system-microblazeel binary
The (former big-endian only) binary qemu-system-microblaze can
handle both endiannesses nowadays, so we don't need the separate
qemu-system-microblazeel binary for little endian anymore. Let's
deprecate it to avoid unnecessary compilation and test time in
the future.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250515132019.569365-5-th...@redhat.com>
Commit: 07a2adeebbe522b6e1c5706db2bdba0b05d0b2ae
https://github.com/qemu/qemu/commit/07a2adeebbe522b6e1c5706db2bdba0b05d0b2ae
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M tests/qtest/test-x86-cpuid-compat.c
Log Message:
-----------
hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the qtest in test-x86-cpuid-compat.c file.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-2-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 8b1c560937467d0d96c1d0948e99f86ce188c0bc
https://github.com/qemu/qemu/commit/8b1c560937467d0d96c1d0948e99f86ce188c0bc
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/i386/pc: Remove PCMachineClass::broken_reserved_end field
The PCMachineClass::broken_reserved_end field was only used
by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed.
Remove it and simplify pc_memory_init().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-3-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 4c82e7b34b1bf35d97e026196f5bf10ea916512c
https://github.com/qemu/qemu/commit/4c82e7b34b1bf35d97e026196f5bf10ea916512c
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/i386/pc: Remove pc_compat_2_4[] array
The pc_compat_2_4[] array was only used by the pc-q35-2.4
and pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-4-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 60ce3f67bea0a782a58cf4f71840e8d20ef8ddfc
https://github.com/qemu/qemu/commit/60ce3f67bea0a782a58cf4f71840e8d20ef8ddfc
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/core/machine.c
M include/hw/boards.h
Log Message:
-----------
hw/core/machine: Remove hw_compat_2_4[] array
The hw_compat_2_4[] array was only used by the pc-q35-2.4 and
pc-i440fx-2.4 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-6-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 0bf8727696267a79658998d844a96e35e0353602
https://github.com/qemu/qemu/commit/0bf8727696267a79658998d844a96e35e0353602
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/net/e1000.c
Log Message:
-----------
hw/net/e1000: Remove unused E1000_FLAG_MAC flag
E1000_FLAG_MAC was only used by the hw_compat_2_4[] array,
via the 'extra_mac_registers=off' property. We removed all
machines using that array, lets remove all the code around
E1000_FLAG_MAC, including the MAC_ACCESS_FLAG_NEEDED enum,
similarly to commit fa4ec9ffda7 ("e1000: remove old
compatibility code").
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-ID: <20250512083948.39294-7-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: fce42ccb51f115156d41eb3c8bd04bddf4a0ca8b
https://github.com/qemu/qemu/commit/fce42ccb51f115156d41eb3c8bd04bddf4a0ca8b
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/virtio/virtio-pci.c
M include/hw/virtio/virtio-pci.h
Log Message:
-----------
hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition
VIRTIO_PCI_FLAG_MIGRATE_EXTRA was only used by the
hw_compat_2_4[] array, via the 'migrate-extra=true'
property. We removed all machines using that array,
lets remove all the code around VIRTIO_PCI_FLAG_MIGRATE_EXTRA.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-ID: <20250512083948.39294-8-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 47d9e81f0ab44b59e99f4e87fe5409851e670de6
https://github.com/qemu/qemu/commit/47d9e81f0ab44b59e99f4e87fe5409851e670de6
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/virtio/virtio-pci.c
M include/hw/virtio/virtio-pci.h
Log Message:
-----------
hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition
VIRTIO_PCI_FLAG_DISABLE_PCIE was only used by the hw_compat_2_4[]
array, via the 'x-disable-pcie=false' property. We removed all
machines using that array, lets remove all the code around
VIRTIO_PCI_FLAG_DISABLE_PCIE (see commit 9a4c0e220d8 for similar
VIRTIO_PCI_FLAG_* enum removal).
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-9-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: ff63280a81144500726f1899b0ae374e692e1f39
https://github.com/qemu/qemu/commit/ff63280a81144500726f1899b0ae374e692e1f39
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M include/hw/i386/pc.h
Log Message:
-----------
hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines
These machines has been supported for a period of more than 6 years.
According to our versioned machine support policy (see commit
ce80c4fa6ff "docs: document special exception for machine type
deprecation & removal") they can now be removed.
Remove the now unused empty pc_compat_2_5[] array.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-10-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 42cbccfcb0635257721aa6a0e55cb80e85756ecf
https://github.com/qemu/qemu/commit/42cbccfcb0635257721aa6a0e55cb80e85756ecf
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/i386/x86.c
M include/hw/i386/x86.h
M target/i386/machine.c
Log Message:
-----------
hw/i386/x86: Remove X86MachineClass::save_tsc_khz field
The X86MachineClass::save_tsc_khz boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it and simplify tsc_khz_needed().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-11-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 6160ce208419e6e218db644433528aaa5d4f5024
https://github.com/qemu/qemu/commit/6160ce208419e6e218db644433528aaa5d4f5024
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/core/loader.c
M hw/i386/pc.c
M hw/nvram/fw_cfg.c
M include/hw/boards.h
M include/hw/loader.h
M include/hw/nvram/fw_cfg.h
M system/vl.c
Log Message:
-----------
hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE
The MachineClass::legacy_fw_cfg_order boolean was only used
by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got
removed. Remove it along with:
- FW_CFG_ORDER_OVERRIDE_* definitions
- fw_cfg_set_order_override()
- fw_cfg_reset_order_override()
- fw_cfg_order[]
- rom_set_order_override()
- rom_reset_order_override()
Simplify CLI and pc_vga_init() / pc_nic_init().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-12-phi...@linaro.org>
[thuth: Fix error from check_patch.pl wrt to an empty "for" loop]
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 667e170d2cf033033dfd6656f871c41871107ee0
https://github.com/qemu/qemu/commit/667e170d2cf033033dfd6656f871c41871107ee0
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/core/machine.c
M include/hw/boards.h
Log Message:
-----------
hw/core/machine: Remove hw_compat_2_5[] array
The hw_compat_2_5[] array was only used by the pc-q35-2.5 and
pc-i440fx-2.5 machines, which got removed. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-13-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 16c04166ae71c78ec36a9e2914c46c2289a58503
https://github.com/qemu/qemu/commit/16c04166ae71c78ec36a9e2914c46c2289a58503
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/scsi/vmw_pvscsi.c
Log Message:
-----------
hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition
PVSCSI_COMPAT_OLD_PCI_CONFIGURATION was only used by the
hw_compat_2_5[] array, via the 'x-old-pci-configuration=on'
property. We removed all machines using that array, lets remove
all the code around PVSCSI_COMPAT_OLD_PCI_CONFIGURATION.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-15-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 404b27b739aa6f2c53fbed58101719564f614aac
https://github.com/qemu/qemu/commit/404b27b739aa6f2c53fbed58101719564f614aac
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/scsi/vmw_pvscsi.c
Log Message:
-----------
hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition
PVSCSI_COMPAT_DISABLE_PCIE_BIT was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around PVSCSI_COMPAT_DISABLE_PCIE_BIT, including the now
unused PVSCSIState::compat_flags field.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-16-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 3763d16370f1505faada6909bd92ebe3a242b1bd
https://github.com/qemu/qemu/commit/3763d16370f1505faada6909bd92ebe3a242b1bd
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/scsi/vmw_pvscsi.c
Log Message:
-----------
hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit
Simplify replacing pvscsi_realize() by pvscsi_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-17-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 2531dfde0ac447b0d70a83c8a02f72e584b9c534
https://github.com/qemu/qemu/commit/2531dfde0ac447b0d70a83c8a02f72e584b9c534
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/net/vmxnet3.c
Log Message:
-----------
hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition
VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS was only used by the
hw_compat_2_5[] array, via the 'x-old-msi-offsets=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-18-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 2db72323f2370ca69ba331f17c9a6bbd1f3bb118
https://github.com/qemu/qemu/commit/2db72323f2370ca69ba331f17c9a6bbd1f3bb118
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/net/vmxnet3.c
Log Message:
-----------
hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition
VMXNET3_COMPAT_FLAG_DISABLE_PCIE was only used by the
hw_compat_2_5[] array, via the 'x-disable-pcie=on' property.
We removed all machines using that array, lets remove all the
code around VMXNET3_COMPAT_FLAG_DISABLE_PCIE.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-19-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: c4eb3f10a3573392c297f2124a81af9041300ddd
https://github.com/qemu/qemu/commit/c4eb3f10a3573392c297f2124a81af9041300ddd
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M hw/net/vmxnet3.c
Log Message:
-----------
hw/net/vmxnet3: Merge DeviceRealize in InstanceInit
Simplify merging vmxnet3_realize() within vmxnet3_instance_init(),
removing the need for device_class_set_parent_realize().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-ID: <20250512083948.39294-20-phi...@linaro.org>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 5c54a367265ec19ed94a535cd15d178c16b8cae0
https://github.com/qemu/qemu/commit/5c54a367265ec19ed94a535cd15d178c16b8cae0
Author: Matheus Tavares Bernardino <matheus.bernard...@oss.qualcomm.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M tests/unit/test-util-sockets.c
Log Message:
-----------
tests/unit/test-util-sockets: fix mem-leak on error object
The test fails with --enable-asan as the error struct is never freed.
In the case where the test expects a success but it fails, let's also
report the error for debugging (it will be freed internally).
Fixes 316e8ee8d6 ("util/qemu-sockets: Refactor inet_parse() to use QemuOpts")
Signed-off-by: Matheus Tavares Bernardino <matheus.bernard...@oss.qualcomm.com>
Reviewed-by: Juraj Marcin <jmar...@redhat.com>
Message-ID:
<518d94c7db20060b2a086cf55ee9bffab992a907.1748280011.git.matheus.bernard...@oss.qualcomm.com>
Signed-off-by: Thomas Huth <th...@redhat.com>
Commit: 72c58ff8958f6e00ce361d1d568dc21e41c85f45
https://github.com/qemu/qemu/commit/72c58ff8958f6e00ce361d1d568dc21e41c85f45
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M include/io/channel-socket.h
M io/channel-socket.c
M nbd/client-connection.c
M nbd/common.c
M nbd/nbd-internal.h
M nbd/server.c
M tests/qemu-iotests/106
M tests/qemu-iotests/125
M tests/qemu-iotests/175
M tests/qemu-iotests/221
M tests/qemu-iotests/253
M tests/qemu-iotests/308
M tests/qemu-iotests/common.rc
M tests/qemu-iotests/tests/mirror-sparse
M tests/qemu-iotests/tests/write-zeroes-unmap
Log Message:
-----------
Merge tag 'pull-nbd-2025-05-29' of https://repo.or.cz/qemu/ericb into staging
NBD patches for 2025-05-29
- Nir Soffer: Allow for larger Unix socket buffers in NBD
- Eric Blake: clean up mirror-sparse iotest issues
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 29 May 2025 18:01:33 EDT
# gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A
# gpg: Good signature from "Eric Blake <ebl...@redhat.com>" [full]
# gpg: aka "Eric Blake (Free Software Programmer)
<e...@byu.net>" [full]
# gpg: aka "[jpeg image of size 6874]" [full]
# Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A
* tag 'pull-nbd-2025-05-29' of https://repo.or.cz/qemu/ericb:
iotests: Filter out ZFS in several tests
iotests: Improve mirror-sparse on ext4 and xfs
iotests: Use disk_usage in more places
nbd: Set unix socket send buffer on Linux
nbd: Set unix socket send buffer on macOS
io: Add helper for setting socket send buffer size
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 98721058d6d50ef218e0c26e4f67c8ef96965859
https://github.com/qemu/qemu/commit/98721058d6d50ef218e0c26e4f67c8ef96965859
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M accel/kvm/kvm-all.c
M accel/tcg/meson.build
M configs/devices/i386-softmmu/default.mak
M docs/system/confidential-guest-support.rst
A docs/system/i386/tdx.rst
M docs/system/target-i386.rst
M gdbstub/meson.build
M hw/arm/meson.build
M hw/core/meson.build
M hw/i386/Kconfig
M hw/i386/kvm/apic.c
M hw/i386/meson.build
M hw/i386/pc.c
M hw/i386/pc_sysfw.c
A hw/i386/tdvf-hob.c
A hw/i386/tdvf-hob.h
A hw/i386/tdvf.c
M hw/i386/x86-common.c
M hw/net/rocker/rocker.h
M hw/net/rocker/rocker_hw.h
M hw/net/rocker/rocker_of_dpa.c
M hw/timer/hpet.c
A include/hw/i386/tdvf.h
A include/standard-headers/uefi/uefi.h
M include/system/kvm.h
M meson.build
M plugins/meson.build
M qapi/qom.json
M qapi/run-state.json
M rust/hw/char/pl011/meson.build
M rust/hw/char/pl011/src/device.rs
A rust/hw/timer/hpet/src/device.rs
M rust/hw/timer/hpet/src/fw_cfg.rs
R rust/hw/timer/hpet/src/hpet.rs
M rust/hw/timer/hpet/src/lib.rs
M rust/meson.build
M rust/qemu-api-macros/meson.build
M rust/qemu-api/meson.build
M rust/qemu-api/src/bitops.rs
M rust/qemu-api/src/qom.rs
M rust/qemu-api/src/timer.rs
M rust/qemu-api/src/vmstate.rs
M rust/qemu-api/tests/vmstate_tests.rs
M system/meson.build
M system/runstate.c
M target/arm/kvm.c
M target/arm/meson.build
M target/i386/confidential-guest.h
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/emulate/x86_flags.c
M target/i386/host-cpu.c
M target/i386/host-cpu.h
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/kvm/meson.build
A target/i386/kvm/tdx-stub.c
A target/i386/kvm/tdx.c
A target/i386/kvm/tdx.h
M target/i386/sev.c
M target/i386/tcg/helper-tcg.h
M target/loongarch/kvm/kvm.c
M target/mips/kvm.c
M target/ppc/kvm.c
M target/riscv/kvm/kvm-cpu.c
M target/s390x/kvm/kvm.c
M tcg/meson.build
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386/kvm: Intel TDX support
* target/i386/emulate: more lflags cleanups
* meson: remove need for explicit listing of dependencies in hw_common_arch and
target_common_arch
* rust: small fixes
* hpet: Reorganize register decoding to be more similar to Rust code
* target/i386: fixes for AMD models
* target/i386: new EPYC-Turin CPU model
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# gpg: Signature made Thu 29 May 2025 03:05:00 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonz...@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonz...@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonz...@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits)
target/i386/tcg/helper-tcg: fix file references in comments
target/i386: Add support for EPYC-Turin model
target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM
feature bits
target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX
target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature
bits
target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature
bits
target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits
rust: make declaration of dependent crates more consistent
docs: Add TDX documentation
i386/tdx: Validate phys_bits against host value
i386/tdx: Make invtsc default on
i386/tdx: Don't treat SYSCALL as unavailable
i386/tdx: Fetch and validate CPUID of TD guest
target/i386: Print CPUID subleaf info for unsupported feature
i386: Remove unused parameter "uint32_t bit" in feature_word_description()
i386/cgs: Introduce x86_confidential_guest_check_features()
i386/tdx: Define supported KVM features for TDX
i386/tdx: Add XFD to supported bit of TDX
i386/tdx: Add supported CPUID bits relates to XFAM
i386/tdx: Add supported CPUID bits related to TD Attributes
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 107215089da92427c4c1644d84f5437b7b6e5e9c
https://github.com/qemu/qemu/commit/107215089da92427c4c1644d84f5437b7b6e5e9c
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/core/loader.c
M hw/core/machine.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/i386/x86.c
M hw/microblaze/petalogix_ml605_mmu.c
M hw/microblaze/petalogix_s3adsp1800_mmu.c
M hw/microblaze/xlnx-zynqmp-pmu.c
M hw/net/e1000.c
M hw/net/vmxnet3.c
M hw/nvram/fw_cfg.c
M hw/scsi/vmw_pvscsi.c
M hw/virtio/virtio-pci.c
M include/hw/boards.h
M include/hw/i386/pc.h
M include/hw/i386/x86.h
M include/hw/loader.h
M include/hw/nvram/fw_cfg.h
M include/hw/virtio/virtio-pci.h
M system/vl.c
M target/i386/machine.c
M tests/functional/test_mem_addr_space.py
M tests/functional/test_microblaze_s3adsp1800.py
M tests/functional/test_microblazeel_s3adsp1800.py
M tests/functional/test_mips_malta.py
M tests/functional/test_sparc64_tuxrun.py
M tests/qtest/test-x86-cpuid-compat.c
M tests/unit/test-util-sockets.c
Log Message:
-----------
Merge tag 'pull-request-2025-05-30' of https://gitlab.com/thuth/qemu into
staging
* Functional tests improvements
* Endianness improvements/clean-ups for the Microblaze machines
* Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and related code
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# gpg: Signature made Fri 30 May 2025 07:45:20 EDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "th...@redhat.com"
# gpg: Good signature from "Thomas Huth <th.h...@gmx.de>" [full]
# gpg: aka "Thomas Huth <th...@redhat.com>" [full]
# gpg: aka "Thomas Huth <h...@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.h...@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2025-05-30' of https://gitlab.com/thuth/qemu: (25 commits)
tests/unit/test-util-sockets: fix mem-leak on error object
hw/net/vmxnet3: Merge DeviceRealize in InstanceInit
hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition
hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition
hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit
hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition
hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition
hw/core/machine: Remove hw_compat_2_5[] array
hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE
hw/i386/x86: Remove X86MachineClass::save_tsc_khz field
hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines
hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition
hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition
hw/net/e1000: Remove unused E1000_FLAG_MAC flag
hw/core/machine: Remove hw_compat_2_4[] array
hw/i386/pc: Remove pc_compat_2_4[] array
hw/i386/pc: Remove PCMachineClass::broken_reserved_end field
hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines
docs: Deprecate the qemu-system-microblazeel binary
hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 3e82ddaa8db260a232dbbbf488d8ac7851d124c5
https://github.com/qemu/qemu/commit/3e82ddaa8db260a232dbbbf488d8ac7851d124c5
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-05-30 (Fri, 30 May 2025)
Changed paths:
M MAINTAINERS
M docs/interop/bitmaps.rst
M docs/interop/index.rst
A docs/interop/qcow2.rst
R docs/interop/qcow2.txt
M docs/qcow2-cache.txt
M hw/arm/Kconfig
M hw/arm/boot.c
M hw/arm/npcm8xx.c
M hw/block/Kconfig
M hw/block/meson.build
R hw/block/nand.c
M include/hw/arm/npcm8xx.h
M include/hw/block/flash.h
M target/arm/arm-qmp-cmds.c
M target/arm/cpregs.h
M target/arm/cpu-features.h
A target/arm/hvf-stub.c
M target/arm/hvf_arm.h
M target/arm/kvm_arm.h
M target/arm/meson.build
M target/arm/tcg/meson.build
M tests/functional/meson.build
A tests/functional/test_arm_stellaris.py
M tests/qtest/meson.build
M tests/qtest/npcm_gmac-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20250530-2' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm: Add GMAC devices to NPCM8XX SoC
* hw/arm: Add missing psci_conduit to NPCM8XX SoC boot info
* docs/interop: convert text files to restructuredText
* target/arm: Some minor refactorings
* tests/functional: Add a test for the Stellaris arm machines
* hw/block: Drop unused nand.c
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# gpg: Signature made Fri 30 May 2025 08:47:50 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.mayd...@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmayd...@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <pe...@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250530-2' of
https://git.linaro.org/people/pmaydell/qemu-arm:
hw/block: Drop unused nand.c
tests/functional: Add a test for the Stellaris arm machines
target/arm/hvf: Include missing 'cpu-qom.h' header
target/arm/kvm: Include missing 'cpu-qom.h' header
target/arm/qmp: Include missing 'cpu.h' header
target/arm/cpu-features: Include missing 'cpu.h' header
hw/arm/boot: Include missing 'system/memory.h' header
target/arm/cpregs: Include missing 'target/arm/cpu.h' header
target/arm: Only link with zlib when TCG is enabled
target/arm/hvf_arm: Avoid using poisoned CONFIG_HVF definition
target/arm/tcg-stubs: compile file once (system)
docs/interop: convert text files to restructuredText
hw/arm: Add missing psci_conduit to NPCM8XX SoC boot info
tests/qtest: Migrate GMAC test from 7xx to 8xx
hw/arm: Add GMAC devices to NPCM8XX SoC
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Compare: https://github.com/qemu/qemu/compare/12c16cb58d6c...3e82ddaa8db2
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