Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 776bd01809fe0f524a578257ff82787d067dbe93
https://github.com/qemu/qemu/commit/776bd01809fe0f524a578257ff82787d067dbe93
Author: Kostiantyn Kostiuk <kkost...@redhat.com>
Date: 2025-06-30 (Mon, 30 Jun 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Update Kostiantyn Kostiuk transliteration
Reviewed-by: Yan Vugenfirer <yvuge...@redhat.com>
Message-ID: <20250620102140.38556-1-kkost...@redhat.com>
Signed-off-by: Kostiantyn Kostiuk <kkost...@redhat.com>
Commit: 012bb70cd16512dbcc1ba423c3f7f260e177afe7
https://github.com/qemu/qemu/commit/012bb70cd16512dbcc1ba423c3f7f260e177afe7
Author: Kostiantyn Kostiuk <kkost...@redhat.com>
Date: 2025-06-30 (Mon, 30 Jun 2025)
Changed paths:
M qga/vss-win32/install.cpp
Log Message:
-----------
qga-vss: Exit with non-zero code when register fail
QGA installer uses rundll32 to run the DLLCOMRegister function
from qga-vss.dll and perform VSS provider registration.
rundll32 ignores the return value of the function and always
exits with a zero exit code. This causes a situation where
the installer does not know the status of VSS provider registration.
This commit forces to change exit code when the VSS provider
registration fails.
https://learn.microsoft.com/en-us/windows-server/administration/windows-commands/rundll32
Reviewed-by: Yan Vugenfirer <yvuge...@redhat.com>
Tested-by: Dehan Meng <dem...@redhat.com>
Message-ID: <20250620083132.28347-1-kkost...@redhat.com>
Signed-off-by: Kostiantyn Kostiuk <kkost...@redhat.com>
Commit: 1c90e89e64beb2bd72f8e437c56274c885df7b3f
https://github.com/qemu/qemu/commit/1c90e89e64beb2bd72f8e437c56274c885df7b3f
Author: Elizabeth Ashurov <eashu...@redhat.com>
Date: 2025-06-30 (Mon, 30 Jun 2025)
Changed paths:
M qga/vss-win32/install.cpp
Log Message:
-----------
qga/vss-win32: Add VSS provider unregistration retry
This commit improves the QGA VSS provider installation flow by attempting to
unregister the VSS provider if it's already
found during installation. This allows for a retry of installation even if a
previous unregistration failed or was not performed.
This will prevent inconsistencies between QGA and QGA-VSS versions.
Before this commit, QGA can use QGA-VSS from the previous installation.
Signed-off-by: Elizabeth Ashurov <eashu...@redhat.com>
Reviewed-by: Kostiantyn Kostiuk <kkost...@redhat.com>
Message-ID: <20250618091806.170110-1-eashu...@redhat.com>
Signed-off-by: Kostiantyn Kostiuk <kkost...@redhat.com>
Commit: a89d18919e4b9a3f8bc67c43e4577ae76ff9ee41
https://github.com/qemu/qemu/commit/a89d18919e4b9a3f8bc67c43e4577ae76ff9ee41
Author: Mads Ynddal <m...@ynddal.dk>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: add myself as reviewer for Apple Silicon HVF
I've both publicly and private been digging around the Apple Silicon HVF code,
and use it daily as part of my job. I feel I have a solid understanding of it,
so I thought I'd step up and assist.
I've added myself as reviewer to the common "HVF" as well, to be informed of
changes that might affect the Apple Silicon HVF code, which will be my primary
focus.
Signed-off-by: Mads Ynddal <m...@ynddal.dk>
Message-id: 20250617093001.70080-1-m...@ynddal.dk
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 9a3bf0e0ab628de7051b41a88c4628aa9e4d311b
https://github.com/qemu/qemu/commit/9a3bf0e0ab628de7051b41a88c4628aa9e4d311b
Author: Solomon Tan <r...@wjsota.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Make RETA[AB] UNDEF when pauth is not implemented
According to the Arm A-profile A64 Instruction Set Architecture,
RETA[AB] should be decoded as UNDEF if the pauth feature is not
implemented.
We got this right in the initial implementation, but accidentally
dropped the feature-check when we converted these insns to
decodetree.
Cc: qemu-sta...@nongnu.org
Fixes: 0ebbe9021254f ("target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to
decodetree")
Signed-off-by: Solomon Tan <r...@wjsota.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250616171549.59190-1-r...@wjsota.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: a2e3508ac0f2aeb27f859362bf8e6dcac96c88e7
https://github.com/qemu/qemu/commit/a2e3508ac0f2aeb27f859362bf8e6dcac96c88e7
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
A target/arm/cpu-sysregs.h
A target/arm/cpu-sysregs.h.inc
M target/arm/cpu.h
M target/arm/cpu64.c
Log Message:
-----------
arm/cpu: Add sysreg definitions in cpu-sysregs.h
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named fields in isar struct to an array cell.
[CH: reworked to use different structures]
[CH: moved accessors from the patches first using them to here,
dropped interaction with writable registers, which will happen
later]
[CH: use DEF magic suggested by rth]
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-2-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 804cfc7eedb7457b137282a528d8c3465760c2e6
https://github.com/qemu/qemu/commit/804cfc7eedb7457b137282a528d8c3465760c2e6
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/kvm.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays
Also add kvm accessors for storing host features into idregs.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-3-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 03380dd993de1a31c596b417f6e8a9de7dd8c370
https://github.com/qemu/qemu/commit/03380dd993de1a31c596b417f6e8a9de7dd8c370
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/kvm.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store aa64isar1/2 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-4-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d1a3cc9634548b8fe1398c6eb624aa2c7e9e265b
https://github.com/qemu/qemu/commit/d1a3cc9634548b8fe1398c6eb624aa2c7e9e265b
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/kvm.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store aa64pfr0/1 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-5-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: f1fd81291c91b6d6954ad67729a3061ec84e643e
https://github.com/qemu/qemu/commit/f1fd81291c91b6d6954ad67729a3061ec84e643e
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/kvm.c
M target/arm/ptw.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store aa64mmfr0-3 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-6-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: def3f1c1026af66d5672f10b3e6cbb87e4e20f73
https://github.com/qemu/qemu/commit/def3f1c1026af66d5672f10b3e6cbb87e4e20f73
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/internals.h
M target/arm/kvm.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store aa64dfr0/1 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-7-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 29279773649a4757b2d7d9eddf98685068e11154
https://github.com/qemu/qemu/commit/29279773649a4757b2d7d9eddf98685068e11154
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/kvm.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store aa64smfr0 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-8-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: c0c2344c4354180edf2476ae5764548a36fa9b67
https://github.com/qemu/qemu/commit/c0c2344c4354180edf2476ae5764548a36fa9b67
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/kvm.c
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store id_isar0-7 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-9-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 30ca689900c8c47bc4ca46be00ec9a7f1a78ccda
https://github.com/qemu/qemu/commit/30ca689900c8c47bc4ca46be00ec9a7f1a78ccda
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/kvm.c
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store id_pfr0/1/2 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-10-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 33801d9bd0947042f223966bbb04f7528e1443f2
https://github.com/qemu/qemu/commit/33801d9bd0947042f223966bbb04f7528e1443f2
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/kvm.c
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store id_dfr0/1 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-11-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 987fa88a11cefe0058326c49dd190ab329635fe0
https://github.com/qemu/qemu/commit/987fa88a11cefe0058326c49dd190ab329635fe0
Author: Eric Auger <eric.au...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu-features.h
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/kvm.c
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
arm/cpu: Store id_mmfr0-5 into the idregs array
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-12-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 8776a0c289f86348ec11e1edb3150ef32d78100a
https://github.com/qemu/qemu/commit/8776a0c289f86348ec11e1edb3150ef32d78100a
Author: Cornelia Huck <coh...@redhat.com>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/kvm.c
Log Message:
-----------
arm/kvm: use fd instead of fdarray[2]
We have fd, so might as well neaten things up.
Suggested-by: Eric Auger <eric.au...@redhat.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250617153931.1330449-15-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 374d766da75ab89749f59813f7ae55d913c37b58
https://github.com/qemu/qemu/commit/374d766da75ab89749f59813f7ae55d913c37b58
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt-acpi-build.c
M include/hw/intc/arm_gicv3_its_common.h
Log Message:
-----------
hw/intc/gicv3_its: Do not check its_class_name()
Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"), the single
implementation of its_class_name() no longer returns NULL (it now always
returns a valid char pointer). Hence, update the prototype docstring and
remove the tautological checks that use the its_class_name() returned
value.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Message-id: 20250628195722.977078-2-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 43eb1805437e1c904fcb5d8ce93096301128a4d0
https://github.com/qemu/qemu/commit/43eb1805437e1c904fcb5d8ce93096301128a4d0
Author: Gustavo Romero <gustavo.rom...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Simplify logic for setting instance's 'tcg_its' variable
Because 'tcg_its' in the machine instance is set based on the machine
class’s negated variable 'no_tcg_its', 'tcg_its' is the opposite of
'no_tcg_its' and hence the code in question can be simplified as:
tcg_its = !no_tcg_its.
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Message-id: 20250628195722.977078-3-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 029cd5d6d1b6fea5d3280c7093e2adbd7d9e32f4
https://github.com/qemu/qemu/commit/029cd5d6d1b6fea5d3280c7093e2adbd7d9e32f4
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Simplify create_its()
No need to strstr() check the class name when we can use
kvm_irqchip_in_kernel() to check if the ITS from the host can be used.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Reviewed-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-id: 20250628195722.977078-4-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 67473d32f020a3c62e24790ab93eb6086a8c8283
https://github.com/qemu/qemu/commit/67473d32f020a3c62e24790ab93eb6086a8c8283
Author: Gustavo Romero <gustavo.rom...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: Improve comment in build_iort
When building the Root Complex table, the comment about the code that
maps the RC node to SMMU node is misleading because it reads
"RC -> SMMUv3 -> ITS", but the code is only mapping the RCs IDs to the
SMMUv3 node. The step of mapping from the SMMUv3 IDs to the ITS Group
node is actually defined in another table (in the SMMUv3 node). So
change the comment to read "RC -> SMMUv3" instead.
Signed-off-by Gustavo Romero <gustavo.rom...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Message-id: 20250628195722.977078-5-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 1c41eaa5fe03cbe9f60edb8f0414c1ad6d7fd786
https://github.com/qemu/qemu/commit/1c41eaa5fe03cbe9f60edb8f0414c1ad6d7fd786
Author: Gustavo Romero <gustavo.rom...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: Factor out create_its_idmaps
Factor out a new function, create_its_idmaps(), from the current
build_iort code. Add proper comments to it clarifying how the ID ranges
that go directly to the ITS Group node are computed based on the ones
that are directed to the SMMU node.
Suggested-by: Eric Auger <eric.au...@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-id: 20250628195722.977078-6-gustavo.rom...@linaro.org
[PMM: drop hardcoded tabs]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: f63c6c23fba52b1496420e31299de42fd342a2c6
https://github.com/qemu/qemu/commit/f63c6c23fba52b1496420e31299de42fd342a2c6
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
M tests/qtest/bios-tables-test.c
Log Message:
-----------
qtest/bios-tables-test: Add test for when ITS is off on aarch64
Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of
hardware introduced in GICv3 and, being optional, it can be disabled
in QEMU aarch64 VMs that support it using machine option "its=off",
like, for instance: "-M virt,its=off".
In ACPI, the ITS is advertised, if present, in the MADT (aka APIC)
table, while the ID mappings from the Root Complex (RC) and from the
SMMU nodes to the ITS Group nodes are described in the IORT table.
This new test verifies that when the "its=off" option is passed to the
machine the ITS-related data is correctly pruned from the ACPI tables.
The new blobs for this test will be added in a following commit.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Message-id: 20250628195722.977078-7-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 50b5fd232ebc1901b2e040a8394f50a63e3f24ec
https://github.com/qemu/qemu/commit/50b5fd232ebc1901b2e040a8394f50a63e3f24ec
Author: Gustavo Romero <gustavo.rom...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
A tests/data/acpi/aarch64/virt/APIC.its_off
A tests/data/acpi/aarch64/virt/IORT.its_off
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
qtest/bios-tables-test: Add blobs for its=off test on aarch64
Add blobs for test_acpi_aarch64_virt_tcg_its_off(), which introduces a
new variant, .its_off, that requires variations of the MADT and IORT
tables.
MADT (aka APIC) diff:
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 000000B8
+[008h 0008 1] Revision : 04
+[009h 0009 1] Checksum : C1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : 00000000
+[028h 0040 4] Flags (decoded below) : 00000000
+ PC-AT Compatibility : 0
+
+[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt
Distributor]
+[02Dh 0045 1] Length : 18
+[02Eh 0046 2] Reserved : 0000
+[030h 0048 4] Local GIC Hardware ID : 00000000
+[034h 0052 8] Base Address : 0000000008000000
+[03Ch 0060 4] Interrupt Base : 00000000
+[040h 0064 1] Version : 03
+[041h 0065 3] Reserved : 000000
+
+[044h 0068 1] Subtable Type : 0B [Generic Interrupt
Controller]
+[045h 0069 1] Length : 50
+[046h 0070 2] Reserved : 0000
+[048h 0072 4] CPU Interface Number : 00000000
+[04Ch 0076 4] Processor UID : 00000000
+[050h 0080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[054h 0084 4] Parking Protocol Version : 00000000
+[058h 0088 4] Performance Interrupt : 00000017
+[05Ch 0092 8] Parked Address : 0000000000000000
+[064h 0100 8] Base Address : 0000000000000000
+[06Ch 0108 8] Virtual GIC Base Address : 0000000000000000
+[074h 0116 8] Hypervisor GIC Base Address : 0000000000000000
+[07Ch 0124 4] Virtual GIC Interrupt : 00000000
+[080h 0128 8] Redistributor Base Address : 0000000000000000
+[088h 0136 8] ARM MPIDR : 0000000000000000
+[090h 0144 1] Efficiency Class : 00
+[091h 0145 1] Reserved : 00
+[092h 0146 2] SPE Overflow Interrupt : 0000
+
+[094h 0148 1] Subtable Type : 0E [Generic Interrupt
Redistributor]
+[095h 0149 1] Length : 10
+[096h 0150 2] Reserved : 0000
+[098h 0152 8] Base Address : 00000000080A0000
+[0A0h 0160 4] Length : 00F60000
+
+[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt
Translator]
+[0A5h 0165 1] Length : 14
+[0A6h 0166 2] Reserved : 0000
+[0A8h 0168 4] Translation ID : 00000000
+[0ACh 0172 8] Base Address : 0000000008080000
+[0B4h 0180 4] Reserved : 00000000
IORT diff:
+[000h 0000 4] Signature : "IORT" [IO Remapping Table]
+[004h 0004 4] Table Length : 000000EC
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 57
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Node Count : 00000003
+[028h 0040 4] Node Offset : 00000030
+[02Ch 0044 4] Reserved : 00000000
+
+[030h 0048 1] Type : 00
+[031h 0049 2] Length : 0018
+[033h 0051 1] Revision : 01
+[034h 0052 4] Reserved : 00000000
+[038h 0056 4] Mapping Count : 00000000
+[03Ch 0060 4] Mapping Offset : 00000000
+
+[040h 0064 4] ItsCount : 00000001
+[044h 0068 4] Identifiers : 00000000
+
+[048h 0072 1] Type : 04
+[049h 0073 2] Length : 0058
+[04Bh 0075 1] Revision : 04
+[04Ch 0076 4] Reserved : 00000001
+[050h 0080 4] Mapping Count : 00000001
+[054h 0084 4] Mapping Offset : 00000044
+
+[058h 0088 8] Base Address : 0000000009050000
+[060h 0096 4] Flags (decoded below) : 00000001
+ COHACC Override : 1
+ HTTU Override : 0
+ Proximity Domain Valid : 0
+[064h 0100 4] Reserved : 00000000
+[068h 0104 8] VATOS Address : 0000000000000000
+[070h 0112 4] Model : 00000000
+[074h 0116 4] Event GSIV : 0000006A
+[078h 0120 4] PRI GSIV : 0000006B
+[07Ch 0124 4] GERR GSIV : 0000006D
+[080h 0128 4] Sync GSIV : 0000006C
+[084h 0132 4] Proximity Domain : 00000000
+[088h 0136 4] Device ID Mapping Index : 00000000
+
+[08Ch 0140 4] Input base : 00000000
+[090h 0144 4] ID Count : 0000FFFF
+[094h 0148 4] Output Base : 00000000
+[098h 0152 4] Output Reference : 00000030
+[09Ch 0156 4] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+[0A0h 0160 1] Type : 02
+[0A1h 0161 2] Length : 004C
+[0A3h 0163 1] Revision : 03
+[0A4h 0164 4] Reserved : 00000002
+[0A8h 0168 4] Mapping Count : 00000002
+[0ACh 0172 4] Mapping Offset : 00000024
+
+[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties]
+[0B0h 0176 4] Cache Coherency : 00000001
+[0B4h 0180 1] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0B5h 0181 2] Reserved : 0000
+[0B7h 0183 1] Memory Flags (decoded below) : 03
+ Coherency : 1
+ Device Attribute : 1
+[0B8h 0184 4] ATS Attribute : 00000000
+[0BCh 0188 4] PCI Segment Number : 00000000
+[0C0h 0192 1] Memory Size Limit : 40
+[0C1h 0193 3] Reserved : 000000
+
+[0C4h 0196 4] Input base : 00000000
+[0C8h 0200 4] ID Count : 000000FF
+[0CCh 0204 4] Output Base : 00000000
+[0D0h 0208 4] Output Reference : 00000048
+[0D4h 0212 4] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+[0D8h 0216 4] Input base : 00000100
+[0DCh 0220 4] ID Count : 0000FEFF
+[0E0h 0224 4] Output Base : 00000100
+[0E4h 0228 4] Output Reference : 00000030
+[0E8h 0232 4] Flags (decoded below) : 00000000
+ Single Mapping : 0
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Message-id: 20250628195722.977078-8-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d6afe18b7242111a71916a962fbd1876a77dc755
https://github.com/qemu/qemu/commit/d6afe18b7242111a71916a962fbd1876a77dc755
Author: Gustavo Romero <gustavo.rom...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt-acpi-build.c
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables when its=off
Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct
in the MADT table are always generated, even if GIC ITS is not available
on the machine.
This commit fixes it by not generating the ITS Group nodes, not mapping
any other node to them, and not advertising the GIC ITS in the MADT
table, when GIC ITS is not available on the machine.
Since the fix changes the MADT and IORT tables, add the blobs for the
"its=off" test to the allow list and update them in the next commit.
This commit also renames the smmu_idmaps and its_idmaps variables in
build_iort() to rc_smmu_idmaps and rc_its_idmaps, respectively, to make
it clearer which nodes are involved in the mappings associated with
these variables.
Reported-by: Udo Steinberg <u...@hypervisor.org>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-id: 20250628195722.977078-9-gustavo.rom...@linaro.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2886
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Co-authored-by: Philippe Mathieu-Daudé <phi...@linaro.org>
[PMM: wrapped an overlong comment]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 96791e69e644669bbc969424f0f31f0b6f522403
https://github.com/qemu/qemu/commit/96791e69e644669bbc969424f0f31f0b6f522403
Author: Gustavo Romero <gustavo.rom...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M tests/data/acpi/aarch64/virt/APIC.its_off
M tests/data/acpi/aarch64/virt/IORT.its_off
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
qtest/bios-tables-test: Update blobs for its=off test on aarch64
Update blobs for the its=off test on aarch64 after fix.
Basically, all structs related to ITS are gone in MADT and IORT
tables after the fix (previously ITS was not properly disabled
when "its=off" option was passed to the machine).
MADT diff:
[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
-[004h 0004 4] Table Length : 000000B8
+[004h 0004 4] Table Length : 000000A4
[008h 0008 1] Revision : 04
-[009h 0009 1] Checksum : C1
+[009h 0009 1] Checksum : 08
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : 00000000
[028h 0040 4] Flags (decoded below) : 00000000
PC-AT Compatibility : 0
[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt
Distributor]
[02Dh 0045 1] Length : 18
[02Eh 0046 2] Reserved : 0000
[030h 0048 4] Local GIC Hardware ID : 00000000
[034h 0052 8] Base Address : 0000000008000000
[03Ch 0060 4] Interrupt Base : 00000000
@@ -48,37 +48,29 @@
[064h 0100 8] Base Address : 0000000000000000
[06Ch 0108 8] Virtual GIC Base Address : 0000000000000000
[074h 0116 8] Hypervisor GIC Base Address : 0000000000000000
[07Ch 0124 4] Virtual GIC Interrupt : 00000000
[080h 0128 8] Redistributor Base Address : 0000000000000000
[088h 0136 8] ARM MPIDR : 0000000000000000
[090h 0144 1] Efficiency Class : 00
[091h 0145 1] Reserved : 00
[092h 0146 2] SPE Overflow Interrupt : 0000
[094h 0148 1] Subtable Type : 0E [Generic Interrupt
Redistributor]
[095h 0149 1] Length : 10
[096h 0150 2] Reserved : 0000
[098h 0152 8] Base Address : 00000000080A0000
[0A0h 0160 4] Length : 00F60000
-[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt
Translator]
-[0A5h 0165 1] Length : 14
-[0A6h 0166 2] Reserved : 0000
-[0A8h 0168 4] Translation ID : 00000000
-[0ACh 0172 8] Base Address : 0000000008080000
-[0B4h 0180 4] Reserved : 00000000
IORT diff:
[000h 0000 4] Signature : "IORT" [IO Remapping Table]
-[004h 0004 4] Table Length : 000000EC
+[004h 0004 4] Table Length : 000000AC
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : 57
+[009h 0009 1] Checksum : 97
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
-[024h 0036 4] Node Count : 00000003
+[024h 0036 4] Node Count : 00000002
[028h 0040 4] Node Offset : 00000030
[02Ch 0044 4] Reserved : 00000000
-[030h 0048 1] Type : 00
-[031h 0049 2] Length : 0018
-[033h 0051 1] Revision : 01
+[030h 0048 1] Type : 04
+[031h 0049 2] Length : 0044
+[033h 0051 1] Revision : 04
[034h 0052 4] Reserved : 00000000
[038h 0056 4] Mapping Count : 00000000
[03Ch 0060 4] Mapping Offset : 00000000
-[040h 0064 4] ItsCount : 00000001
-[044h 0068 4] Identifiers : 00000000
-
-[048h 0072 1] Type : 04
-[049h 0073 2] Length : 0058
-[04Bh 0075 1] Revision : 04
-[04Ch 0076 4] Reserved : 00000001
-[050h 0080 4] Mapping Count : 00000001
-[054h 0084 4] Mapping Offset : 00000044
-
-[058h 0088 8] Base Address : 0000000009050000
-[060h 0096 4] Flags (decoded below) : 00000001
+[040h 0064 8] Base Address : 0000000009050000
+[048h 0072 4] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
-[064h 0100 4] Reserved : 00000000
-[068h 0104 8] VATOS Address : 0000000000000000
-[070h 0112 4] Model : 00000000
-[074h 0116 4] Event GSIV : 0000006A
-[078h 0120 4] PRI GSIV : 0000006B
-[07Ch 0124 4] GERR GSIV : 0000006D
-[080h 0128 4] Sync GSIV : 0000006C
-[084h 0132 4] Proximity Domain : 00000000
-[088h 0136 4] Device ID Mapping Index : 00000000
-
-[08Ch 0140 4] Input base : 00000000
-[090h 0144 4] ID Count : 0000FFFF
-[094h 0148 4] Output Base : 00000000
-[098h 0152 4] Output Reference : 00000030
-[09Ch 0156 4] Flags (decoded below) : 00000000
- Single Mapping : 0
-
-[0A0h 0160 1] Type : 02
-[0A1h 0161 2] Length : 004C
-[0A3h 0163 1] Revision : 03
-[0A4h 0164 4] Reserved : 00000002
-[0A8h 0168 4] Mapping Count : 00000002
-[0ACh 0172 4] Mapping Offset : 00000024
-
-[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties]
-[0B0h 0176 4] Cache Coherency : 00000001
-[0B4h 0180 1] Hints (decoded below) : 00
+[04Ch 0076 4] Reserved : 00000000
+[050h 0080 8] VATOS Address : 0000000000000000
+[058h 0088 4] Model : 00000000
+[05Ch 0092 4] Event GSIV : 0000006A
+[060h 0096 4] PRI GSIV : 0000006B
+[064h 0100 4] GERR GSIV : 0000006D
+[068h 0104 4] Sync GSIV : 0000006C
+[06Ch 0108 4] Proximity Domain : 00000000
+[070h 0112 4] Device ID Mapping Index : 00000000
+
+[074h 0116 1] Type : 02
+[075h 0117 2] Length : 0038
+[077h 0119 1] Revision : 03
+[078h 0120 4] Reserved : 00000001
+[07Ch 0124 4] Mapping Count : 00000001
+[080h 0128 4] Mapping Offset : 00000024
+
+[084h 0132 8] Memory Properties : [IORT Memory Access Properties]
+[084h 0132 4] Cache Coherency : 00000001
+[088h 0136 1] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
-[0B5h 0181 2] Reserved : 0000
-[0B7h 0183 1] Memory Flags (decoded below) : 03
+[089h 0137 2] Reserved : 0000
+[08Bh 0139 1] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
-[0B8h 0184 4] ATS Attribute : 00000000
-[0BCh 0188 4] PCI Segment Number : 00000000
-[0C0h 0192 1] Memory Size Limit : 40
-[0C1h 0193 3] Reserved : 000000
-
-[0C4h 0196 4] Input base : 00000000
-[0C8h 0200 4] ID Count : 000000FF
-[0CCh 0204 4] Output Base : 00000000
-[0D0h 0208 4] Output Reference : 00000048
-[0D4h 0212 4] Flags (decoded below) : 00000000
- Single Mapping : 0
-
-[0D8h 0216 4] Input base : 00000100
-[0DCh 0220 4] ID Count : 0000FEFF
-[0E0h 0224 4] Output Base : 00000100
-[0E4h 0228 4] Output Reference : 00000030
-[0E8h 0232 4] Flags (decoded below) : 00000000
+[08Ch 0140 4] ATS Attribute : 00000000
+[090h 0144 4] PCI Segment Number : 00000000
+[094h 0148 1] Memory Size Limit : 40
+[095h 0149 3] Reserved : 000000
+
+[098h 0152 4] Input base : 00000000
+[09Ch 0156 4] ID Count : 000000FF
+[0A0h 0160 4] Output Base : 00000000
+[0A4h 0164 4] Output Reference : 00000030
+[0A8h 0168 4] Flags (decoded below) : 00000000
Single Mapping : 0
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Message-id: 20250628195722.977078-10-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: a5b94f6c7b3a6ae583ba07098bff810049262413
https://github.com/qemu/qemu/commit/a5b94f6c7b3a6ae583ba07098bff810049262413
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/internals.h
Log Message:
-----------
target/arm: Remove arm_handle_psci_call() stub
Since commit 0c1aaa66c24 ("target/arm: wrap psci call with
tcg_enabled") the arm_handle_psci_call() call is elided
when TCG is disabled.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-2-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 4a94d8047d9dca2d7e73bbc863fabbea2df1bab6
https://github.com/qemu/qemu/commit/4a94d8047d9dca2d7e73bbc863fabbea2df1bab6
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
Log Message:
-----------
target/arm: Reduce arm_cpu_post_init() declaration scope
arm_cpu_post_init() is only used within the same file unit.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-3-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: a74b63b3a4451bec2f0d77fc101cf066d1e0fdb1
https://github.com/qemu/qemu/commit/a74b63b3a4451bec2f0d77fc101cf066d1e0fdb1
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Unify gen_exception_internal()
Same code, use the generic variant.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-4-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 30484a6635161e8bd62014542c5fd15bbf14834f
https://github.com/qemu/qemu/commit/30484a6635161e8bd62014542c5fd15bbf14834f
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
target/arm/hvf: Directly re-lock BQL after hv_vcpu_run()
Keep bql_unlock() / bql_lock() close.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Acked-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250623121845.7214-6-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 4dcba9072be2c1e32f3fb676e97b098d5a9b66ad
https://github.com/qemu/qemu/commit/4dcba9072be2c1e32f3fb676e97b098d5a9b66ad
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/hvf/hvf.c
M target/arm/hvf/trace-events
Log Message:
-----------
target/arm/hvf: Trace hv_vcpu_run() failures
Allow distinguishing HV_ILLEGAL_GUEST_STATE in trace events.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-7-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d17d5cc0d68cc1dbce4a9086ce1cb8c3aebb085c
https://github.com/qemu/qemu/commit/d17d5cc0d68cc1dbce4a9086ce1cb8c3aebb085c
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M accel/hvf/hvf-accel-ops.c
A accel/hvf/trace-events
A accel/hvf/trace.h
M meson.build
Log Message:
-----------
accel/hvf: Trace VM memory mapping
Trace memory mapped / unmapped in the guest.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-8-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 9097c0cd611d0f1924041c85b9aeab41ecbd1a9a
https://github.com/qemu/qemu/commit/9097c0cd611d0f1924041c85b9aeab41ecbd1a9a
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/hvf/hvf.c
M target/arm/hvf/trace-events
Log Message:
-----------
target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event
Tracing $PC for unknown HVC instructions to not have to
look at the disassembled flow of instructions.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-9-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: a412575837b6a46584fba891e3706e87bd09a3e6
https://github.com/qemu/qemu/commit/a412575837b6a46584fba891e3706e87bd09a3e6
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/hvf/hvf.c
M target/arm/kvm.c
Log Message:
-----------
target/arm: Correct KVM & HVF dtb_compatible value
Linux kernel knows how to parse "arm,armv8", not "arm,arm-v8".
See arch/arm64/boot/dts/foundation-v8.dts:
https://github.com/torvalds/linux/commit/90556ca1ebdd
Cc: qemu-sta...@nongnu.org
Fixes: 26861c7ce06 ("target-arm: Add minimal KVM AArch64 support")
Fixes: 585df85efea ("hvf: arm: Implement -cpu host")
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-10-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 38d4089c048a055f36d21ef009b09612e60ac226
https://github.com/qemu/qemu/commit/38d4089c048a055f36d21ef009b09612e60ac226
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
target/arm/hvf: Pass @target_el argument to hvf_raise_exception()
In preparation of raising exceptions at EL2, add the 'target_el'
argument to hvf_raise_exception().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-12-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 532884658d606160ff3ad73c73c05fddf3504d9b
https://github.com/qemu/qemu/commit/532884658d606160ff3ad73c73c05fddf3504d9b
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Restrict system register properties to system binary
Do not expose the following system-specific properties on user-mode
binaries:
- psci-conduit
- cntfrq (ARM_FEATURE_GENERIC_TIMER)
- rvbar (ARM_FEATURE_V8)
- has-mpu (ARM_FEATURE_PMSA)
- pmsav7-dregion (ARM_FEATURE_PMSA)
- reset-cbar (ARM_FEATURE_CBAR)
- reset-hivecs (ARM_FEATURE_M)
- init-nsvtor (ARM_FEATURE_M)
- init-svtor (ARM_FEATURE_M_SECURITY)
- idau (ARM_FEATURE_M_SECURITY)
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-13-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 1370fd56ec771f16197f255c25c910e9386ac587
https://github.com/qemu/qemu/commit/1370fd56ec771f16197f255c25c910e9386ac587
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Make EL3-guest accel check an accept-list
Currently only the TCG and qtest accelerators can handle an EL3
guest. Instead of making the condition check be "fail if KVM or HVF"
(an exclude-list), make it a be "allow if TCG or qtest" (an
accept-list).
This is better for if/when we add new accelerators, as it makes the
default be that we forbid an EL3 guest. This is the most likely to
be correct and also "fails safe"; if the new accelerator really can
support EL3 guests then the implementor will see that they need to
add it to the accept-list.
Reported-by: Alex Bennée <alex.ben...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-19-phi...@linaro.org
[PMM: rewrote commit message]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 164258da4a24464a502b6ece6fce9fc6ca1c0207
https://github.com/qemu/qemu/commit/164258da4a24464a502b6ece6fce9fc6ca1c0207
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Make EL2 accelerator check an accept-list
Currently only the TCG and qtest accelerators can handle an EL2
guest. Instead of making the condition check be "fail if KVM or HVF"
(an exclude-list), make it a be "allow if TCG or qtest" (an
accept-list).
This is better for if/when we add new accelerators, as it makes the
default be that we forbid an EL2 guest. This is the most likely to
be correct and also "fails safe"; if the new accelerator really can
support EL2 guests then the implementor will see that they need to
add it to the accept-list.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20250623121845.7214-20-phi...@linaro.org
[PMM: rewrote commit message]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: c6a613094e48fc83ee5c65464dccd90fae637516
https://github.com/qemu/qemu/commit/c6a613094e48fc83ee5c65464dccd90fae637516
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized()
QDev uses _post_init() during instance creation, before being
realized. Since here both vCPUs and GIC are REALIZED, rename
as virt_post_cpus_gic_realized() for clarity.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-21-phi...@linaro.org
[PMM: also fixed up comment]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 4e24ea43a126822d0c3d28d57b500ac9bbce5735
https://github.com/qemu/qemu/commit/4e24ea43a126822d0c3d28d57b500ac9bbce5735
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition
Define RAMLIMIT_BYTES using the TiB definition and display
the error parsed with size_to_str():
$ qemu-system-aarch64-unsigned -M sbsa-ref -m 9T
qemu-system-aarch64-unsigned: sbsa-ref: cannot model more than 8 TiB of RAM
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-22-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 9bc4c2a6118ab1713155dedd14ccdae8dde71de1
https://github.com/qemu/qemu/commit/9bc4c2a6118ab1713155dedd14ccdae8dde71de1
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M tests/functional/test_aarch64_sbsaref.py
M tests/functional/test_aarch64_sbsaref_alpine.py
M tests/functional/test_aarch64_sbsaref_freebsd.py
Log Message:
-----------
tests/functional: Set sbsa-ref machine type in each test function
fetch_firmware() is only about fetching firmware.
Set the machine type and its default console in
test_sbsaref_edk2_firmware().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@oss.qualcomm.com>
Message-id: 20250623121845.7214-23-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 72846594b089f03bed1bb46958c910afcb859d49
https://github.com/qemu/qemu/commit/72846594b089f03bed1bb46958c910afcb859d49
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M tests/functional/test_aarch64_xen.py
Log Message:
-----------
tests/functional: Restrict nested Aarch64 Xen test to TCG
Currently QEMU only support accelerating EL0 and EL1, so features
requiring EL2 (like virtualization) or EL3 must be emulated with TCG.
On macOS this test fails:
qemu-system-aarch64: mach-virt: HVF does not support providing Virtualization
extensions to the guest CPU
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250623121845.7214-24-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: f4b5fbeff6be3797881e69cbf42cc689a4e316c4
https://github.com/qemu/qemu/commit/f4b5fbeff6be3797881e69cbf42cc689a4e316c4
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M tests/functional/test_aarch64_imx8mp_evk.py
Log Message:
-----------
tests/functional: Require TCG to run Aarch64 imx8mp-evk test
The imx8mp-evk machine can only run with the TCG accelerator.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Message-id: 20250623121845.7214-25-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 767df742fbc9e6cc06e9309685407beb2565c272
https://github.com/qemu/qemu/commit/767df742fbc9e6cc06e9309685407beb2565c272
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M python/qemu/utils/__init__.py
M python/qemu/utils/accel.py
M tests/functional/qemu_test/testcase.py
Log Message:
-----------
tests/functional: Add hvf_available() helper
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Message-id: 20250623121845.7214-26-phi...@linaro.org
[PMM: tweaks to satisfy the python linter CI job]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 9b4c8dd505b1630e3fdaca071886d1cd41019156
https://github.com/qemu/qemu/commit/9b4c8dd505b1630e3fdaca071886d1cd41019156
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M tests/functional/test_aarch64_smmu.py
Log Message:
-----------
tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20250623121845.7214-27-phi...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 7bc86ccbb59f2022014e132327a33b94a7ed00fe
https://github.com/qemu/qemu/commit/7bc86ccbb59f2022014e132327a33b94a7ed00fe
Author: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M tests/functional/meson.build
A tests/functional/test_aarch64_device_passthrough.py
Log Message:
-----------
tests/functional: test device passthrough on aarch64
This test allows to document and exercise device passthrough, using a
nested virtual machine setup. Two disks are generated and passed to the
VM, and their content is compared to original images.
Guest and nested guests commands are executed through two scripts, and
init used in both system is configured to trigger a kernel panic in case
any command fails. This is more reliable and readable than executing all
commands through prompt injection and trying to guess what failed.
Initially, this test was supposed to test smmuv3 nested emulation
(combining both stages of translation), but I could not find any setup
(kernel + vmm) able to do the passthrough correctly, despite several
tries.
Signed-off-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250627200222.5172-1-pierrick.bouv...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: f7c8df571859223c00d1ed1249d7a22f0e30f9d6
https://github.com/qemu/qemu/commit/f7c8df571859223c00d1ed1249d7a22f0e30f9d6
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-02 (Wed, 02 Jul 2025)
Changed paths:
M MAINTAINERS
M qga/vss-win32/install.cpp
Log Message:
-----------
Merge tag 'qga-pull-2025-07-01' of https://github.com/kostyanf14/qemu into
staging
qga-pull-2025-07-01
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# gpg: Signature made Tue 01 Jul 2025 08:23:04 EDT
# gpg: using RSA key C2C2C109EA43C63C1423EB84EF5D5E8161BA84E7
# gpg: Good signature from "Kostiantyn Kostiuk (Upstream PR sign)
<kkost...@redhat.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: C2C2 C109 EA43 C63C 1423 EB84 EF5D 5E81 61BA 84E7
* tag 'qga-pull-2025-07-01' of https://github.com/kostyanf14/qemu:
qga/vss-win32: Add VSS provider unregistration retry
qga-vss: Exit with non-zero code when register fail
MAINTAINERS: Update Kostiantyn Kostiuk transliteration
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 7698afc42b5af9e55f12ab2236618e38e5a1c23f
https://github.com/qemu/qemu/commit/7698afc42b5af9e55f12ab2236618e38e5a1c23f
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-02 (Wed, 02 Jul 2025)
Changed paths:
M MAINTAINERS
M accel/hvf/hvf-accel-ops.c
A accel/hvf/trace-events
A accel/hvf/trace.h
M hw/arm/sbsa-ref.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/intc/armv7m_nvic.c
M include/hw/intc/arm_gicv3_its_common.h
M meson.build
M python/qemu/utils/__init__.py
M python/qemu/utils/accel.py
M target/arm/cpu-features.h
A target/arm/cpu-sysregs.h
A target/arm/cpu-sysregs.h.inc
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/hvf/trace-events
M target/arm/internals.h
M target/arm/kvm.c
M target/arm/ptw.c
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
A tests/data/acpi/aarch64/virt/APIC.its_off
A tests/data/acpi/aarch64/virt/IORT.its_off
M tests/functional/meson.build
M tests/functional/qemu_test/testcase.py
A tests/functional/test_aarch64_device_passthrough.py
M tests/functional/test_aarch64_imx8mp_evk.py
M tests/functional/test_aarch64_sbsaref.py
M tests/functional/test_aarch64_sbsaref_alpine.py
M tests/functional/test_aarch64_sbsaref_freebsd.py
M tests/functional/test_aarch64_smmu.py
M tests/functional/test_aarch64_xen.py
M tests/qtest/bios-tables-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20250701-1' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* MAINTAINERS update for arm hvf
* target/arm: Make RETA[AB] UNDEF when pauth is not implemented
* target/arm: Refactoring of ID register value storage
* target/arm: Various refactoring/cleanup patches
* virt: Don't show an ITS in ACPI tables when no ITS is present
* tests/functional: test device passthrough on aarch64
* tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator
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# gpg: Signature made Tue 01 Jul 2025 12:59:30 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.mayd...@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmayd...@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <pe...@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250701-1' of https://gitlab.com/pm215/qemu: (43
commits)
tests/functional: test device passthrough on aarch64
tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator
tests/functional: Add hvf_available() helper
tests/functional: Require TCG to run Aarch64 imx8mp-evk test
tests/functional: Restrict nested Aarch64 Xen test to TCG
tests/functional: Set sbsa-ref machine type in each test function
hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition
hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized()
hw/arm/virt: Make EL2 accelerator check an accept-list
hw/arm/virt: Make EL3-guest accel check an accept-list
target/arm: Restrict system register properties to system binary
target/arm/hvf: Pass @target_el argument to hvf_raise_exception()
target/arm: Correct KVM & HVF dtb_compatible value
target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event
accel/hvf: Trace VM memory mapping
target/arm/hvf: Trace hv_vcpu_run() failures
target/arm/hvf: Directly re-lock BQL after hv_vcpu_run()
target/arm: Unify gen_exception_internal()
target/arm: Reduce arm_cpu_post_init() declaration scope
target/arm: Remove arm_handle_psci_call() stub
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Compare: https://github.com/qemu/qemu/compare/6138e72b7e33...7698afc42b5a
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