Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 51ac481bff88723ef4c101925082fab03bba200a
https://github.com/qemu/qemu/commit/51ac481bff88723ef4c101925082fab03bba200a
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/misc/aspeed_sdmc.c
Log Message:
-----------
hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700
On AST2700 SoC, QEMU now sets BIT6 in VGA0 SCRATCH register to indicate
that DDR training has completed, thus skipping the dram_init().
To align with the recent U-Boot changes, where the Main Control Register's
BIT16 is checked to skip the dram_init() process, this patch sets BIT16 in
the SDMC Main Control Register at reset time.
This allows both the main U-Boot stage to correctly detect and bypass DRAM
initialization when running under QEMU.
Reference:
- QEMU:
https://github.com/qemu/qemu/commit/2d082fea485ee455a70ed3e963cdf9a70f34858a
- U-Boot:
https://github.com/AspeedTech-BMC/u-boot/commit/94e5435504fb0d8888f5c1bfd3fa284cdd6aaf9b
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250618080006.846355-2-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: a6ca5dfccc2b584d2f7bf31fb488fc178e967972
https://github.com/qemu/qemu/commit/a6ca5dfccc2b584d2f7bf31fb488fc178e967972
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/misc/aspeed_scu.c
Log Message:
-----------
hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700
According to the datasheet:
BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter.
BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished.
Firmware polls BIT[6] to determine when measurement is complete.
The flag can be cleared by writing BIT[1] to 0.
To simulate this hardware behavior in QEMU:
If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid
firmware hanging during polling.
If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match
hardware semantics.
The initial value of this register is initialized to 0x80, reflecting the
default value confirmed from an EVB register dump.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250618080006.846355-3-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 126c56b067d6a68840542f8dc7afdec9b69caa83
https://github.com/qemu/qemu/commit/126c56b067d6a68840542f8dc7afdec9b69caa83
Author: Patrick Williams <patr...@stwcx.xyz>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: bletchley: update hw strap values
Update the Bletchley hardware strap register values
per actual hardware:
```
root@bmc:~# devmem 0x1e6e2500
0x00002000
root@bmc:~# devmem 0x1e6e2510
0x00000801
```
Signed-off-by: Patrick Williams <patr...@stwcx.xyz>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250619035850.2682690-1-patr...@stwcx.xyz
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 8e076a3f1b1ed0fc009ee25796e45c44b4cf74f9
https://github.com/qemu/qemu/commit/8e076a3f1b1ed0fc009ee25796e45c44b4cf74f9
Author: Patrick Williams <patr...@stwcx.xyz>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/arm/Kconfig
M hw/arm/aspeed.c
M tests/functional/meson.build
A tests/functional/test_arm_aspeed_catalina.py
Log Message:
-----------
hw/arm/aspeed: add Catalina machine type
Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of
6.16-rc2. The i2c model is as complete as the current QEMU models
support, but in some cases I substituted devices that are close enough
for present functionality. Strap registers are were verified with
hardware.
This has been tested with an openbmc image built from [2].
Add a functional test in line with Bletchley, pointing at an image
obtained from the OpenBMC Jenkins server.
[1]:
https://github.com/torvalds/linux/blob/v6.16-rc2/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts
[2]:
https://github.com/openbmc/openbmc/commit/5bc73ec261f981d5e586bda5ac78eb0cbd5f92b0
Signed-off-by: Patrick Williams <patr...@stwcx.xyz>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250619151458.2831859-1-patr...@stwcx.xyz
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 10d1b6231b7fdbeb9c601af35f73c6353cbfe6c8
https://github.com/qemu/qemu/commit/10d1b6231b7fdbeb9c601af35f73c6353cbfe6c8
Author: Tan Siewert <t...@siewert.io>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/misc/aspeed_scu.c
Log Message:
-----------
hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly
The AST2600 SCU has two protection key registers (0x00 and 0x10) that
both need to be unlocked. (Un-)locking 0x00 modifies both protection key
registers, while modifying 0x10 only modifies itself.
This commit updates the SCU write logic to reject writes unless both
protection key registers are unlocked, matching the behaviour of
real hardware.
Signed-off-by: Tan Siewert <t...@siewert.io>
Reviewed-by: Jamin Lin <jamin_...@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20250619085329.42125-1-...@siewert.io
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 116bf243d9137a9101aa1a403b402b78313615bc
https://github.com/qemu/qemu/commit/116bf243d9137a9101aa1a403b402b78313615bc
Author: Tan Siewert <t...@siewert.io>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
A tests/qtest/aspeed_scu-test.c
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest: Add test for ASPEED SCU
This adds basic tests for the ASPEED System Control Unit (SCU) and its
protection mechanism on the AST2500 and AST2600 platforms.
The tests verify:
- That SCU protection registers can be unlocked and locked again
- That modifying the primary protection register on AST2600 also
affects the secondary one
- That writes to protected SCU registers are blocked unless
protection registers are unlocked explicitly
These tests ensure proper emulation of hardware locking behaviour
and help catch regressions in SCU access logic.
Signed-off-by: Tan Siewert <t...@siewert.io>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250630112646.74944-1-...@siewert.io
[ clg: Reordered file list in meson.build ]
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: e8c1128bf982f2e5f7c9ca6c1de632feec3d9e94
https://github.com/qemu/qemu/commit/e8c1128bf982f2e5f7c9ca6c1de632feec3d9e94
Author: Zhenzhong Duan <zhenzhong.d...@intel.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/cpr-legacy.c
Log Message:
-----------
vfio/container: Fix potential SIGSEGV when recover from unmap-all-vaddr
failure
CPR overrides then restores dma_map in both outgoing and incoming QEMU, for
different reasons. But it only sets saved_dma_map in the target.
Fix it by always setting saved_dma_map.
Fixes: eba1f657cbb1 ("vfio/container: recover from unmap-all-vaddr failure")
Suggested-by: Steven Sistare <steven.sist...@oracle.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Reviewed-by: Steve Sistare <steven.sist...@oracle.com>
Link:
https://lore.kernel.org/qemu-devel/20250627063332.5173-2-zhenzhong.d...@intel.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 924c3ccb310e615bd350d4c77b269b19d95bf5e4
https://github.com/qemu/qemu/commit/924c3ccb310e615bd350d4c77b269b19d95bf5e4
Author: Zhenzhong Duan <zhenzhong.d...@intel.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/cpr-legacy.c
M include/hw/vfio/vfio-cpr.h
Log Message:
-----------
vfio/container: Fix vfio_container_post_load()
When there are multiple VFIO containers, vioc->dma_map is restored
multiple times, this made only first container work and remaining
containers using vioc->dma_map restored by first container.
Fix it by save and restore vioc->dma_map locally. saved_dma_map in
VFIOContainerCPR becomes useless and is removed.
Fixes: 7e9f21411302 ("vfio/container: restore DMA vaddr")
Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Reviewed-by: Steve Sistare <steven.sist...@oracle.com>
Link:
https://lore.kernel.org/qemu-devel/20250627063332.5173-3-zhenzhong.d...@intel.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: f7c5dff26e0128246f5c220b38da51e56a756dbb
https://github.com/qemu/qemu/commit/f7c5dff26e0128246f5c220b38da51e56a756dbb
Author: Mark Cave-Ayland <mark.caveayl...@nutanix.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio-user/container.c
Log Message:
-----------
vfio-user: do not register vfio-user container with cpr
As the full cpr implementation is yet to be merged upstream, do not register
the vfio-user container with cpr. Full vfio-user support for cpr can be
merged later as a follow-up series.
Signed-off-by: Mark Cave-Ayland <mark.caveayl...@nutanix.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Message-ID: <20250702120043.267634-1-mark.caveayl...@nutanix.com>
[ clg: Removed now useless "hw/vfio/vfio-cpr.h" include ]
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 34ea448263a8dad7443bfeaf5eca75e49abc5865
https://github.com/qemu/qemu/commit/34ea448263a8dad7443bfeaf5eca75e49abc5865
Author: Xiaoyao Li <xiaoyao...@intel.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/i386/Kconfig
Log Message:
-----------
i386/tdx: Build TDX only for 64-bit target
Build errors related to TDX were reported when QEMU built on 32-bit
host[1][2].
Since TDX cannot work on 32-bit host and it's also not worth supporting
TDX with 32-bit QEMU, limit TDX to 64-bit target only.
[1] https://lore.kernel.org/qemu-devel/20250602173101.1052983-1-...@redhat.com/
[2]
https://lore.kernel.org/qemu-devel/b8171c39-6a92-4078-a59a-a63d7452e...@kaod.org/
Suggested-by: Cédric Le Goater <c...@redhat.com>
Signed-off-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Tested-by: Cédric Le Goater <c...@redhat.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250625073310.2796298-1-xiaoyao...@intel.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 4ba5cdfdf70843d7a74a7cb9704688c4c6957dd6
https://github.com/qemu/qemu/commit/4ba5cdfdf70843d7a74a7cb9704688c4c6957dd6
Author: Cédric Le Goater <c...@redhat.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M .b4-config
Log Message:
-----------
b4: Drop linktrailermask
When grabbing a patch series, the link trailer is replaced with a
Message-ID, which is not useful compared to an URL. Fix that by
dropping the linktrailermask config.
Cc: Philippe Mathieu-Daudé <phi...@linaro.org>
Cc: Jiaxun Yang <jiaxun.y...@flygoat.com>
Fixes: 838cf72b5d2c ("Add a b4 configuration file")
Link: https://lore.kernel.org/qemu-devel/20250630172301.519848-1-...@redhat.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 3f2a36d0ef6339ce78e107959da81f76283582f7
https://github.com/qemu/qemu/commit/3f2a36d0ef6339ce78e107959da81f76283582f7
Author: Cédric Le Goater <c...@redhat.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M Makefile
Log Message:
-----------
Makefile: prune quilt source files for cscope
Both quilt, to apply patches, and cscope, to navigate in the code, are
useful tools. Make sure source files that quilt saves when applying
patches are not taken into account when building the cscope database.
Link: https://lore.kernel.org/qemu-devel/20250630172048.519182-1-...@redhat.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 30edcb4d4e7a265c2912ca6978b150c7c75b654f
https://github.com/qemu/qemu/commit/30edcb4d4e7a265c2912ca6978b150c7c75b654f
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/cpr.c
M hw/vfio/pci.c
M hw/vfio/pci.h
M include/hw/vfio/vfio-cpr.h
Log Message:
-----------
vfio-pci: preserve MSI
Save the MSI message area as part of vfio-pci vmstate, and preserve the
interrupt and notifier eventfd's. migrate_incoming loads the MSI data,
then the vfio-pci post_load handler finds the eventfds in CPR state,
rebuilds vector data structures, and attaches the interrupts to the new
KVM instance.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-2-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 87aeaead5c75448d6e36bf6f9114862c8d523871
https://github.com/qemu/qemu/commit/87aeaead5c75448d6e36bf6f9114862c8d523871
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/cpr.c
M hw/vfio/pci.c
Log Message:
-----------
vfio-pci: preserve INTx
Preserve vfio INTx state across cpr-transfer. Preserve VFIOINTx fields as
follows:
pin : Recover this from the vfio config in kernel space
interrupt : Preserve its eventfd descriptor across exec.
unmask : Ditto
route.irq : This could perhaps be recovered in vfio_pci_post_load by
calling pci_device_route_intx_to_irq(pin), whose implementation reads
config space for a bridge device such as ich9. However, there is no
guarantee that the bridge vmstate is read before vfio vmstate. Rather
than fiddling with MigrationPriority for vmstate handlers, explicitly
save route.irq in vfio vmstate.
pending : save in vfio vmstate.
mmap_timeout, mmap_timer : Re-initialize
bool kvm_accel : Re-initialize
In vfio_realize, defer calling vfio_intx_enable until the vmstate
is available, in vfio_pci_post_load. Modify vfio_intx_enable and
vfio_intx_kvm_enable to skip vfio initialization, but still perform
kvm initialization.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-3-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 7ed0919119b0e7a6b7db1dcaca3a2cb30c771dd1
https://github.com/qemu/qemu/commit/7ed0919119b0e7a6b7db1dcaca3a2cb30c771dd1
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M accel/kvm/kvm-all.c
M hw/vfio/cpr-legacy.c
M hw/vfio/cpr.c
M hw/vfio/helpers.c
M include/hw/vfio/vfio-cpr.h
M include/hw/vfio/vfio-device.h
M include/system/kvm.h
Log Message:
-----------
migration: close kvm after cpr
cpr-transfer breaks vfio network connectivity to and from the guest, and
the host system log shows:
irq bypass consumer (token 00000000a03c32e5) registration fails: -16
which is EBUSY. This occurs because KVM descriptors are still open in
the old QEMU process. Close them.
Cc: Paolo Bonzini <pbonz...@redhat.com>
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-4-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: ccfc6715cf54caafba4c2516af394b4ed979c615
https://github.com/qemu/qemu/commit/ccfc6715cf54caafba4c2516af394b4ed979c615
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M include/migration/cpr.h
M migration/cpr.c
Log Message:
-----------
migration: cpr_get_fd_param helper
Add the helper function cpr_get_fd_param, to use when preserving
a file descriptor that is opened externally and passed to QEMU.
cpr_get_fd_param returns a descriptor number either from a QEMU
command-line parameter, from a getfd command, or from CPR state.
When a descriptor is passed to new QEMU via SCM_RIGHTS, its number
changes. Hence, during CPR, the command-line parameter is ignored
in new QEMU, and over-ridden by the value found in CPR state.
Similarly, if the descriptor was originally specified by a getfd
command in old QEMU, the fd number is not known outside of QEMU,
and it changes when sent to new QEMU via SCM_RIGHTS. Hence the
user cannot send getfd to new QEMU, but when the user sends a
hotplug command that references the fd, cpr_get_fd_param finds
its value in CPR state.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-5-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: e563dc88c21915e111ecef0756cc291e9e473c35
https://github.com/qemu/qemu/commit/e563dc88c21915e111ecef0756cc291e9e473c35
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M backends/iommufd.c
M backends/trace-events
M include/system/iommufd.h
Log Message:
-----------
backends/iommufd: iommufd_backend_map_file_dma
Define iommufd_backend_map_file_dma to implement IOMMU_IOAS_MAP_FILE.
This will be called as a substitute for iommufd_backend_map_dma, so
the error conditions for BARs are copied as-is from that function.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-6-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: ab48cedc648a60a3e51db73acf12148d90f19c4c
https://github.com/qemu/qemu/commit/ab48cedc648a60a3e51db73acf12148d90f19c4c
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M backends/iommufd.c
M backends/trace-events
M include/system/iommufd.h
Log Message:
-----------
backends/iommufd: change process ioctl
Define the change process ioctl
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-7-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: d7ae4a740c8e49962ccfbbf41da0b3b8314518ce
https://github.com/qemu/qemu/commit/d7ae4a740c8e49962ccfbbf41da0b3b8314518ce
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M include/exec/cpu-common.h
M system/physmem.c
Log Message:
-----------
physmem: qemu_ram_get_fd_offset
Define qemu_ram_get_fd_offset, so CPR can map a memory region using
IOMMU_IOAS_MAP_FILE in a subsequent patch.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Peter Xu <pet...@redhat.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-8-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: fb32965b6dd8a001815593642a5146fbd2e85651
https://github.com/qemu/qemu/commit/fb32965b6dd8a001815593642a5146fbd2e85651
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/container-base.c
M hw/vfio/iommufd.c
M include/hw/vfio/vfio-container-base.h
Log Message:
-----------
vfio/iommufd: use IOMMU_IOAS_MAP_FILE
Use IOMMU_IOAS_MAP_FILE when the mapped region is backed by a file.
Such a mapping can be preserved without modification during CPR,
because it depends on the file's address space, which does not change,
rather than on the process's address space, which does change.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-9-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: b9b389b9e0f08b207786d501b790dab9cb2c09de
https://github.com/qemu/qemu/commit/b9b389b9e0f08b207786d501b790dab9cb2c09de
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/device.c
Log Message:
-----------
vfio/iommufd: invariant device name
cpr-transfer will use the device name as a key to find the value
of the device descriptor in new QEMU. However, if the descriptor
number is specified by a command-line fd parameter, then
vfio_device_get_name creates a name that includes the fd number.
This causes a chicken-and-egg problem: new QEMU must know the fd
number to construct a name to find the fd number.
To fix, create an invariant name based on the id command-line parameter,
if id is defined. The user will need to provide such an id to use CPR.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-10-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 184053f04f6ad6b2950d4712063ffed43bb2720f
https://github.com/qemu/qemu/commit/184053f04f6ad6b2950d4712063ffed43bb2720f
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/ap.c
M hw/vfio/ccw.c
M hw/vfio/device.c
M hw/vfio/pci.c
M hw/vfio/platform.c
M include/hw/vfio/vfio-device.h
Log Message:
-----------
vfio/iommufd: add vfio_device_free_name
Define vfio_device_free_name to free the name created by
vfio_device_get_name. A subsequent patch will do more there.
No functional change.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-11-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: a434fd8f6462c1541927d22e07c58425d6cbd84b
https://github.com/qemu/qemu/commit/a434fd8f6462c1541927d22e07c58425d6cbd84b
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/device.c
M include/hw/vfio/vfio-cpr.h
Log Message:
-----------
vfio/iommufd: device name blocker
If an invariant device name cannot be created, block CPR.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-12-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 06c6a65852af0b7648cdb6ff6cf2e66929a7b5f5
https://github.com/qemu/qemu/commit/06c6a65852af0b7648cdb6ff6cf2e66929a7b5f5
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M backends/iommufd.c
A hw/vfio/cpr-iommufd.c
M hw/vfio/iommufd.c
M hw/vfio/meson.build
M include/hw/vfio/vfio-cpr.h
M include/system/iommufd.h
Log Message:
-----------
vfio/iommufd: register container for cpr
Register a vfio iommufd container and device for CPR, replacing the generic
CPR register call with a more specific iommufd register call. Add a
blocker if the kernel does not support IOMMU_IOAS_CHANGE_PROCESS.
This is mostly boiler plate. The fields to to saved and restored are added
in subsequent patches.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-13-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: a6f2f9c42f3a5418fc7000b1fd331b086b6133d9
https://github.com/qemu/qemu/commit/a6f2f9c42f3a5418fc7000b1fd331b086b6133d9
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/cpr-iommufd.c
A hw/vfio/iommufd-stubs.c
M hw/vfio/meson.build
M include/hw/vfio/vfio-cpr.h
M include/migration/cpr.h
M migration/cpr.c
Log Message:
-----------
migration: vfio cpr state hook
Define a list of vfio devices in CPR state, in a subsection so that
older QEMU can be live updated to this version. However, new QEMU
will not be live updateable to old QEMU. This is acceptable because
CPR is not yet commonly used, and updates to older versions are unusual.
The contents of each device object will be defined by the vfio subsystem
in a subsequent patch.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-14-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: f2f3e4667e4d6026f39ab17f355f79b2f8431e19
https://github.com/qemu/qemu/commit/f2f3e4667e4d6026f39ab17f355f79b2f8431e19
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/cpr-iommufd.c
M hw/vfio/iommufd.c
M hw/vfio/trace-events
M include/hw/vfio/vfio-cpr.h
Log Message:
-----------
vfio/iommufd: cpr state
VFIO iommufd devices will need access to ioas_id, devid, and hwpt_id in
new QEMU at realize time, so add them to CPR state. Define CprVFIODevice
as the object which holds the state and is serialized to the vmstate file.
Define accessors to copy state between VFIODevice and CprVFIODevice.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-15-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 2a3f0a59bd6479f75fa5335f82b85b4f9cd7ed4e
https://github.com/qemu/qemu/commit/2a3f0a59bd6479f75fa5335f82b85b4f9cd7ed4e
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M backends/iommufd.c
M hw/vfio/cpr-iommufd.c
M hw/vfio/device.c
Log Message:
-----------
vfio/iommufd: preserve descriptors
Save the iommu and vfio device fd in CPR state when it is created.
After CPR, the fd number is found in CPR state and reused.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-16-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 4296ee07455e48c169eb110fbca6ef724c119381
https://github.com/qemu/qemu/commit/4296ee07455e48c169eb110fbca6ef724c119381
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/iommufd.c
Log Message:
-----------
vfio/iommufd: reconstruct device
Reconstruct userland device state after CPR. During vfio_realize, skip all
ioctls that configure the device, as it was already configured in old QEMU.
Skip bind, and use the devid from CPR state.
Skip allocation of, and attachment to, ioas_id. Recover ioas_id from CPR
state, and use it to find a matching container, if any, before creating a
new one.
This reconstruction is not complete. hwpt_id is handled in a subsequent
patch.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-17-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 010643eeb1521c0240c83ee8678544de0cd30b78
https://github.com/qemu/qemu/commit/010643eeb1521c0240c83ee8678544de0cd30b78
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/iommufd.c
Log Message:
-----------
vfio/iommufd: reconstruct hwpt
Skip allocation of, and attachment to, hwpt_id. Recover it from CPR state.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-18-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 5c066c4be2328c46f03e9166ea720b13bf68ea5d
https://github.com/qemu/qemu/commit/5c066c4be2328c46f03e9166ea720b13bf68ea5d
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/cpr-iommufd.c
Log Message:
-----------
vfio/iommufd: change process
Finish CPR by change the owning process of the iommufd device in
post load.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-19-git-send-email-steven.sist...@oracle.com
[ clg: Fixed missing "qemu/error-report.h" include ]
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 6ff4cccd13155e718e630fe16a72d3cc9decde3b
https://github.com/qemu/qemu/commit/6ff4cccd13155e718e630fe16a72d3cc9decde3b
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M backends/iommufd.c
Log Message:
-----------
iommufd: preserve DMA mappings
During cpr-transfer load in new QEMU, the vfio_memory_listener causes
spurious calls to map and unmap DMA regions, as devices are created and
the address space is built. This memory was already already mapped by the
device in old QEMU, so suppress the map and unmap callbacks during incoming
CPR.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-20-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 99cedd5d552130b9b27743c40ca9012e1f4f0371
https://github.com/qemu/qemu/commit/99cedd5d552130b9b27743c40ca9012e1f4f0371
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/vfio/cpr.c
M include/hw/vfio/vfio-cpr.h
Log Message:
-----------
vfio/container: delete old cpr register
vfio_cpr_[un]register_container is no longer used since they were
subsumed by container type-specific registration. Delete them.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-21-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 7437caad2052d920452ff7b9b7bc84f5e8e55c90
https://github.com/qemu/qemu/commit/7437caad2052d920452ff7b9b7bc84f5e8e55c90
Author: Steve Sistare <steven.sist...@oracle.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M docs/devel/migration/CPR.rst
M qapi/migration.json
Log Message:
-----------
vfio: doc changes for cpr
Update documentation to say that cpr-transfer supports vfio and iommufd.
Signed-off-by: Steve Sistare <steven.sist...@oracle.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/1751493538-202042-22-git-send-email-steven.sist...@oracle.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 6888a4a9c8601005a2329fee6487c3c0df1348c0
https://github.com/qemu/qemu/commit/6888a4a9c8601005a2329fee6487c3c0df1348c0
Author: Jamin Lin <jamin_...@aspeedtech.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M docs/about/deprecated.rst
Log Message:
-----------
aspeed: Deprecate the ast2700a0-evb machine
The ast2700a0-evb machine represents the first revision of the AST2700 and
serves as the initial engineering sample rather than a production version.
A newer revision, A1, is now supported, and the ast2700a1-evb should replace
the older A0 version.
Signed-off-by: Jamin Lin <jamin_...@aspeedtech.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250703052400.2927831-1-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 92096685a00414a813aa4735db1706e4e5c6917d
https://github.com/qemu/qemu/commit/92096685a00414a813aa4735db1706e4e5c6917d
Author: Ed Tanous <etan...@nvidia.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/arm/aspeed.c
M include/hw/arm/aspeed.h
Log Message:
-----------
hw/arm/aspeed: Add second SPI chip to Aspeed model
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous <etan...@nvidia.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etan...@nvidia.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: ad8e0e8a0088b8e30582c65b739a7ee8bb0d71ee
https://github.com/qemu/qemu/commit/ad8e0e8a0088b8e30582c65b739a7ee8bb0d71ee
Author: Ed Tanous <etan...@nvidia.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: add support for gb200-bmc
This patch updates the docs for support of gb200-bmc.
Signed-off-by: Ed Tanous <etan...@nvidia.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250703144249.3348879-3-etan...@nvidia.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: becfaa10a2b554ac619fdd9ae0aa9cacdba73d67
https://github.com/qemu/qemu/commit/becfaa10a2b554ac619fdd9ae0aa9cacdba73d67
Author: Ed Tanous <etan...@nvidia.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_eeprom.c
M hw/arm/aspeed_eeprom.h
Log Message:
-----------
hw/arm/aspeed: Add GB200 BMC target
GB200nvl72 is a system for for accelerated compute. This is a model for
the BMC target within the system.
This is based on the device tree aspeed-bmc-nvidia-gb200nvl-bmc.dts
from:
[1]
https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
Signed-off-by: Ed Tanous <etan...@nvidia.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250703144249.3348879-4-etan...@nvidia.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 3a34dad2c0d25cebafed40696bbbdeb7ff4b9c7d
https://github.com/qemu/qemu/commit/3a34dad2c0d25cebafed40696bbbdeb7ff4b9c7d
Author: Ed Tanous <etan...@nvidia.com>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M tests/functional/aspeed.py
M tests/functional/meson.build
A tests/functional/test_arm_aspeed_gb200nvl_bmc.py
Log Message:
-----------
tests/functional: Add gb200 tests
To support the newly added gb200 machine, add appropriate tests and
extend do_test_arm_aspeed_openbmc() to support the hostname of this
new system: "gb200nvl-obmc".
Signed-off-by: Ed Tanous <etan...@nvidia.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250703144249.3348879-5-etan...@nvidia.com
[ clg: Adjust commit log to document do_test_arm_aspeed_openbmc() change ]
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: d30245d3f54187d5ef4fbc9013386b98b22da2b5
https://github.com/qemu/qemu/commit/d30245d3f54187d5ef4fbc9013386b98b22da2b5
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/tcg/tcg-accel-ops.c
M system/cpus.c
Log Message:
-----------
system/cpus: Assert interrupt handling is done with BQL locked
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-5-phi...@linaro.org>
Commit: f3fc87a14b601e7af727f556cf5a50df44d69839
https://github.com/qemu/qemu/commit/f3fc87a14b601e7af727f556cf5a50df44d69839
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/stubs/kvm-stub.c
Log Message:
-----------
accel/kvm: Remove kvm_init_cpu_signals() stub
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_init_cpu_signals() stub is not necessary.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-Id: <20250703173248.44995-6-phi...@linaro.org>
Commit: 06810394fdc013037811e317501902ed6ab9c276
https://github.com/qemu/qemu/commit/06810394fdc013037811e317501902ed6ab9c276
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/kvm/kvm-all.c
M include/system/kvm.h
Log Message:
-----------
accel/kvm: Reduce kvm_create_vcpu() declaration scope
kvm_create_vcpu() is only used within the same file unit.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-7-phi...@linaro.org>
Commit: a8e49597d486123a62375eda6dbc939fffbfd31d
https://github.com/qemu/qemu/commit/a8e49597d486123a62375eda6dbc939fffbfd31d
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/tcg/monitor.c
M hmp-commands-info.hx
M qapi/machine.json
M tests/qtest/qmp-cmd-test.c
Log Message:
-----------
accel/tcg: Remove 'info opcount' and @x-query-opcount
Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER",
released with QEMU v8.1.0) we get pointless output:
(qemu) info opcount
[TCG profiler not compiled]
Remove that unstable and unuseful command.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Acked-by: Dr. David Alan Gilbert <d...@treblig.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Markus Armbruster <arm...@redhat.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-8-phi...@linaro.org>
Commit: f1e59f012de35310314a2a12ea9cb5f72019c976
https://github.com/qemu/qemu/commit/f1e59f012de35310314a2a12ea9cb5f72019c976
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/tcg/monitor.c
Log Message:
-----------
accel/tcg: Remove profiler leftover
TCG profiler was removed in commit 1b65b4f54c7.
Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER")
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-9-phi...@linaro.org>
Commit: 04fbbeb7655372f500a7e1d610202a08a50cc364
https://github.com/qemu/qemu/commit/04fbbeb7655372f500a7e1d610202a08a50cc364
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/tcg/monitor.c
Log Message:
-----------
accel/tcg: Factor tcg_dump_flush_info() out
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-10-phi...@linaro.org>
Commit: a472390e800825f8544b7aa7a3503b6a4ae4bec2
https://github.com/qemu/qemu/commit/a472390e800825f8544b7aa7a3503b6a4ae4bec2
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/tcg/internal-common.h
M accel/tcg/monitor.c
Log Message:
-----------
accel/tcg: Factor tcg_dump_stats() out for re-use
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-11-phi...@linaro.org>
Commit: 0175310c385628de25a09905cb4bb35c2cd47d5f
https://github.com/qemu/qemu/commit/0175310c385628de25a09905cb4bb35c2cd47d5f
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M include/system/hvf.h
M include/system/hvf_int.h
Log Message:
-----------
accel/hvf: Restrict internal declarations
Common code only needs to know whether HVF is enabled and
the QOM type. Move the rest to "hvf_int.h", removing the
need for COMPILING_PER_TARGET #ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-15-phi...@linaro.org>
Commit: c4b231cbd3198a05bcaaef5c0a6ee3ecebd12e21
https://github.com/qemu/qemu/commit/c4b231cbd3198a05bcaaef5c0a6ee3ecebd12e21
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/hvf/hvf-accel-ops.c
M accel/hvf/hvf-all.c
Log Message:
-----------
accel/hvf: Move per-cpu method declarations to hvf-accel-ops.c
hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL),
while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS).
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-16-phi...@linaro.org>
Commit: 5da232017a46a14f86cdbe70396b8051aacfed99
https://github.com/qemu/qemu/commit/5da232017a46a14f86cdbe70396b8051aacfed99
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/hvf/hvf-accel-ops.c
M accel/hvf/hvf-all.c
Log Message:
-----------
accel/hvf: Move generic method declarations to hvf-all.c
hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL),
while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS).
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-17-phi...@linaro.org>
Commit: 332ad068a025056e2ffd0dc7605897254eb20e15
https://github.com/qemu/qemu/commit/332ad068a025056e2ffd0dc7605897254eb20e15
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M include/hw/core/cpu.h
Log Message:
-----------
cpus: Document CPUState::vcpu_dirty field
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-Id: <20250703173248.44995-18-phi...@linaro.org>
Commit: 93bbbcb8d6eb9325530da8c3c313220d45f27252
https://github.com/qemu/qemu/commit/93bbbcb8d6eb9325530da8c3c313220d45f27252
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/hvf/hvf-accel-ops.c
M include/system/hvf_int.h
M target/arm/hvf/hvf.c
M target/i386/hvf/hvf.c
M target/i386/hvf/x86hvf.c
Log Message:
-----------
accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-19-phi...@linaro.org>
Commit: 2098164a6bebe97b736cb1d657c2d750daf8eb76
https://github.com/qemu/qemu/commit/2098164a6bebe97b736cb1d657c2d750daf8eb76
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/i386/nvmm/nvmm-all.c
Log Message:
-----------
accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty field
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-20-phi...@linaro.org>
Commit: 29741712054aa8bd333d54dd88121ea3609ab386
https://github.com/qemu/qemu/commit/29741712054aa8bd333d54dd88121ea3609ab386
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/i386/whpx/whpx-all.c
Log Message:
-----------
accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-21-phi...@linaro.org>
Commit: 476e7379652d357f1053d340968e7f8d5c5b5281
https://github.com/qemu/qemu/commit/476e7379652d357f1053d340968e7f8d5c5b5281
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/stubs/kvm-stub.c
Log Message:
-----------
accel/kvm: Remove kvm_cpu_synchronize_state() stub
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_cpu_synchronize_state() stub is not
necessary.
Fixes: e0715f6abce ("kvm: remove kvm specific functions from global includes")
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-22-phi...@linaro.org>
Commit: 1f8b0b64736e978120753e63c51921573962a54c
https://github.com/qemu/qemu/commit/1f8b0b64736e978120753e63c51921573962a54c
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M include/system/accel-ops.h
M include/system/hw_accel.h
Log Message:
-----------
accel/system: Document cpu_synchronize_state()
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-23-phi...@linaro.org>
Commit: 60c9cec12c99e47fb2c82ad5dca36c9441b623dc
https://github.com/qemu/qemu/commit/60c9cec12c99e47fb2c82ad5dca36c9441b623dc
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M include/system/accel-ops.h
M include/system/hw_accel.h
Log Message:
-----------
accel/system: Document cpu_synchronize_state_post_init/reset()
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-24-phi...@linaro.org>
Commit: b6637bd5561d1d03f3a3d4335102cbf57fad5ad0
https://github.com/qemu/qemu/commit/b6637bd5561d1d03f3a3d4335102cbf57fad5ad0
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M MAINTAINERS
M accel/stubs/meson.build
A accel/stubs/nvmm-stub.c
M include/system/nvmm.h
M target/i386/nvmm/nvmm-all.c
Log Message:
-----------
accel/nvmm: Expose nvmm_enabled() to common code
Currently nvmm_enabled() is restricted to target-specific code.
By defining CONFIG_NVMM_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Message-Id: <20250703173248.44995-25-phi...@linaro.org>
Commit: d5a407a5763c4f5182124bb08c9157c0c667662f
https://github.com/qemu/qemu/commit/d5a407a5763c4f5182124bb08c9157c0c667662f
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M MAINTAINERS
M accel/stubs/meson.build
A accel/stubs/whpx-stub.c
M include/system/whpx.h
M target/i386/whpx/whpx-all.c
Log Message:
-----------
accel/whpx: Expose whpx_enabled() to common code
Currently whpx_enabled() is restricted to target-specific code.
By defining CONFIG_WHPX_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-26-phi...@linaro.org>
Commit: e8388158e62184cb567b7b97ab9e6738dec45348
https://github.com/qemu/qemu/commit/e8388158e62184cb567b7b97ab9e6738dec45348
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M MAINTAINERS
M accel/dummy-cpus.c
A accel/dummy-cpus.h
M accel/qtest/qtest.c
M accel/xen/xen-all.c
M include/system/cpus.h
Log Message:
-----------
accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'
'dummy' helpers are specific to accelerator implementations,
no need to expose them via "system/cpus.h".
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-Id: <20250703173248.44995-27-phi...@linaro.org>
Commit: b9b8ce038497a18f4525e9b229f9090b1cec3b05
https://github.com/qemu/qemu/commit/b9b8ce038497a18f4525e9b229f9090b1cec3b05
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/hvf/hvf-accel-ops.c
M accel/kvm/kvm-accel-ops.c
M accel/qtest/qtest.c
M accel/xen/xen-all.c
M include/system/accel-ops.h
M system/cpus.c
M target/i386/nvmm/nvmm-accel-ops.c
M target/i386/whpx/whpx-accel-ops.c
Log Message:
-----------
accel: Expose and register generic_handle_interrupt()
In order to dispatch over AccelOpsClass::handle_interrupt(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::handle_interrupt() mandatory.
Expose generic_handle_interrupt() prototype and register it
for each accelerator.
Suggested-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Reviewed-by: Zhao Liu <zhao1....@intel.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Xiaoyao Li <xiaoyao...@intel.com>
Message-Id: <20250703173248.44995-29-phi...@linaro.org>
Commit: 38623a9f63395cecdd4138a305e1187e10964990
https://github.com/qemu/qemu/commit/38623a9f63395cecdd4138a305e1187e10964990
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/accel-system.c
M accel/tcg/tcg-accel-ops.c
M include/qemu/accel.h
M include/system/accel-ops.h
Log Message:
-----------
accel: Keep reference to AccelOpsClass in AccelClass
Allow dereferencing AccelOpsClass outside of accel/accel-system.c.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Message-Id: <20250703173248.44995-30-phi...@linaro.org>
Commit: 51e189619992a08d529bf580f6bcf074f5a7af0d
https://github.com/qemu/qemu/commit/51e189619992a08d529bf580f6bcf074f5a7af0d
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/accel-system.c
M accel/hvf/hvf-all.c
M accel/kvm/kvm-all.c
M accel/qtest/qtest.c
M accel/tcg/tcg-all.c
M accel/xen/xen-all.c
M bsd-user/main.c
M include/qemu/accel.h
M linux-user/main.c
M target/i386/nvmm/nvmm-all.c
M target/i386/whpx/whpx-all.c
Log Message:
-----------
accel: Propagate AccelState to AccelClass::init_machine()
In order to avoid init_machine() to call current_accel(),
pass AccelState along.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Message-Id: <20250703173248.44995-31-phi...@linaro.org>
Commit: 0fdcfc3baf9af2f2e1903eebf23edc9dd8b0aec2
https://github.com/qemu/qemu/commit/0fdcfc3baf9af2f2e1903eebf23edc9dd8b0aec2
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/tcg/tcg-all.c
Log Message:
-----------
accel/tcg: Prefer local AccelState over global current_accel()
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-33-phi...@linaro.org>
Commit: f0db25adcfa930a97b5192a6f59fd08c369c32e6
https://github.com/qemu/qemu/commit/f0db25adcfa930a97b5192a6f59fd08c369c32e6
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
accel/kvm: Prefer local AccelState over global MachineState::accel
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-32-phi...@linaro.org>
Commit: 583d1c8f1652777e7d60f09eb58c1f6378d897f1
https://github.com/qemu/qemu/commit/583d1c8f1652777e7d60f09eb58c1f6378d897f1
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-35-phi...@linaro.org>
Commit: 8dd5e6befc86161598eace2bfeb090c2cfb179fd
https://github.com/qemu/qemu/commit/8dd5e6befc86161598eace2bfeb090c2cfb179fd
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/kvm/kvm-all.c
M include/qemu/accel.h
M system/memory.c
Log Message:
-----------
accel: Directly pass AccelState argument to AccelClass::has_memory()
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-Id: <20250703173248.44995-34-phi...@linaro.org>
Commit: 1e9fb43d30c0526e164bebaab387b615edfa79ad
https://github.com/qemu/qemu/commit/1e9fb43d30c0526e164bebaab387b615edfa79ad
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/accel-system.c
M accel/xen/xen-all.c
M include/qemu/accel.h
Log Message:
-----------
accel: Remove unused MachineState argument of AccelClass::setup_post()
This method only accesses xen_domid/xen_domid_restrict, which are both
related to the 'accelerator', not the machine. Besides, xen_domid aims
to be in Xen AccelState and xen_domid_restrict a xen_domid_restrict
QOM property.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-36-phi...@linaro.org>
Commit: 842e7eecd4446957c5edf0c65e5e41fadea2f015
https://github.com/qemu/qemu/commit/842e7eecd4446957c5edf0c65e5e41fadea2f015
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M accel/accel-common.c
M accel/hvf/hvf-all.c
M accel/kvm/kvm-all.c
M accel/tcg/tcg-all.c
M include/qemu/accel.h
Log Message:
-----------
accel: Pass AccelState argument to gdbstub_supported_sstep_flags()
In order to have AccelClass methods instrospect their state,
we need to pass AccelState by argument.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-37-phi...@linaro.org>
Commit: 0fd1d74080215571f2c8e2b85bfefb3c65238cfe
https://github.com/qemu/qemu/commit/0fd1d74080215571f2c8e2b85bfefb3c65238cfe
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M monitor/hmp-cmds-target.c
Log Message:
-----------
monitor/hmp-cmds-target: add CPU_DUMP_VPU in hmp_info_registers()
Commit b84694defb added the CPU_DUMP_VPU to allow vector registers to be
logged by log_cpu_exec() in TCG. This flag was then used in commit
b227f6a8a7 to print RISC-V vector registers using this flag. Note that
this change was done in riscv_cpu_dump_state(), the cpu_dump_state()
callback for RISC-V, the same callback used in hmp_info_registers().
Back then we forgot to change hmp_info_registers(), and 'info registers'
isn't showing RISC-V vector registers as a result. No other target is
impacted since only RISC-V is using CPU_DUMP_VPU.
There's no reason to not show VPU regs in info_registers(), so add
CPU_DUMP_VPU to hmp_info_registers(). This will print vector registers
for all RISC-V machines and, as said above, has no impact in other
archs.
Cc: Dr. David Alan Gilbert <d...@treblig.org>
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20250623145306.991562-1-dbarb...@ventanamicro.com>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Commit: c8beb901be15c57d166574ecf660261f0f23209f
https://github.com/qemu/qemu/commit/c8beb901be15c57d166574ecf660261f0f23209f
Author: Philippe Mathieu-Daudé <phi...@linaro.org>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add me as reviewer of overall accelerators section
I'd like to be informed of overall changes of accelerators.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20250703173248.44995-40-phi...@linaro.org>
Commit: 6eba6fe967c3a2606ef5ec5ba9a283b21d09f85b
https://github.com/qemu/qemu/commit/6eba6fe967c3a2606ef5ec5ba9a283b21d09f85b
Author: Jim Shu <jim....@sifive.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/time_helper.c
Log Message:
-----------
target/riscv: Add the checking into stimecmp write function.
Preparation commit to let aclint timer to use stimecmp write function.
Aclint timer doesn't call sstc() predicate so we need to check inside
the stimecmp write function.
Signed-off-by: Jim Shu <jim....@sifive.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250519143518.11086-2-jim....@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: af27fc569af58e10d9e77afd10079809f05827bc
https://github.com/qemu/qemu/commit/af27fc569af58e10d9e77afd10079809f05827bc
Author: Jim Shu <jim....@sifive.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: riscv_aclint: Fix mtime write for sstc extension
When changing the mtime value, the period of [s|vs]timecmp timers
should also be updated, similar to the period of mtimecmp timer.
The period of the stimecmp timer is the time until the next S-mode
timer IRQ. The value is calculated as "stimecmp - time". [1]
It is equal to "stimecmp - mtime" since the time CSR is a read-only
shadow of the memory-mapped mtime register.
Thus, changing mtime value will update the period of stimecmp timer.
Similarly, the period of vstimecmp timer is calculated as "vstimecmp -
(mtime + htimedelta)" [2], so changing mtime value will update the
period of vstimecmp timer.
[1] RISC-V Priv spec ch 9.1.1. Supervisor Timer (stimecmp) Register
A supervisor timer interrupt becomes pending, as reflected in the STIP
bit in the mip and sip registers whenever time contains a value
greater than or equal to stimecmp.
[2] RISC-V Priv spec ch19.2.1. Virtual Supervisor Timer (vstimecmp) Register
A virtual supervisor timer interrupt becomes pending, as reflected in
the VSTIP bit in the hip register, whenever (time + htimedelta),
truncated to 64 bits, contains a value greater than or equal to
vstimecmp
Signed-off-by: Jim Shu <jim....@sifive.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250519143518.11086-3-jim....@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 3cb2edae740121cf5da3a9adb8190051e866eb01
https://github.com/qemu/qemu/commit/3cb2edae740121cf5da3a9adb8190051e866eb01
Author: Jim Shu <jim....@sifive.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix VSTIP bit in sstc extension.
VSTIP is only writable when both [mh]envcfg.STCE is enabled, or it will
revert it's defined behavior as if sstc extension is not implemented.
Signed-off-by: Jim Shu <jim....@sifive.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250519143518.11086-4-jim....@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: dff5f515409f1c9c10df00160524b21381cbef26
https://github.com/qemu/qemu/commit/dff5f515409f1c9c10df00160524b21381cbef26
Author: Jim Shu <jim....@sifive.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/csr.c
M target/riscv/time_helper.c
M target/riscv/time_helper.h
Log Message:
-----------
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR.
Signed-off-by: Jim Shu <jim....@sifive.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250519143518.11086-5-jim....@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 148499b343a9aac62c5f5d55617a1c317127e2e3
https://github.com/qemu/qemu/commit/148499b343a9aac62c5f5d55617a1c317127e2e3
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: fix zama16b order in isa_edata_arr[]
Put it after zalrsc and before zawrs.
Cc: qemu-triv...@nongnu.org
Fixes: a60ce58fd9 ("target/riscv: Support Zama16b extension")
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250522113344.823294-1-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: a429f9304d54e9a44773b753d0844204b4b3b22f
https://github.com/qemu/qemu/commit/a429f9304d54e9a44773b753d0844204b4b3b22f
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg: restrict satp_mode changes in cpu_set_profile
We're changing 'mmu' to true regardless of whether the profile is
being enabled or not, and at the same time we're changing satp_mode to
profile->enabled.
This will promote a situation where we'll set mmu=on without a virtual
memory mode, which is a mistake.
Only touch 'mmu' and satp_mode if the profile is being enabled.
Suggested-by: Andrew Jones <ajo...@ventanamicro.com>
Fixes: 55398025e7 ("target/riscv: add satp_mode profile support")
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Björn Töpel <bj...@rivosinc.com>
Tested-by: Björn Töpel <bj...@rivosinc.com>
Message-ID: <20250528184407.1451983-2-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: f655704c3dfefd57172e3347c22aca18283ee2b7
https://github.com/qemu/qemu/commit/f655704c3dfefd57172e3347c22aca18283ee2b7
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg: decouple profile enablement from user prop
We have code in riscv_cpu_add_profiles() to enable a profile right away
in case a CPU chose the profile during its cpu_init(). But we're using
the user callback option to do so, setting profile->user_set.
Create a new helper that does all the grunt work to enable/disable a
given profile. Use this new helper in the cases where we want a CPU to
be compatible to a certain profile, leaving the user callback to be used
exclusively by users.
Fixes: fba92a92e3 ("target/riscv: add 'rva22u64' CPU")
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Björn Töpel <bj...@rivosinc.com>
Tested-by: Björn Töpel <bj...@rivosinc.com>
Message-ID: <20250528184407.1451983-3-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: cab6b5d8c351863b21d05eb8c9bb7920ad883b05
https://github.com/qemu/qemu/commit/cab6b5d8c351863b21d05eb8c9bb7920ad883b05
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/riscv-qmp-cmds.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: add profile->present flag
Björn reported in [1] a case where a rv64 CPU is going through the
profile code path to enable satp mode. In this case,the amount of
extensions on top of the rv64 CPU made it compliant with the RVA22S64
profile during the validation of CPU 0. When the subsequent CPUs were
initialized the static profile object has the 'enable' flag set,
enabling the profile code path for those CPUs.
This happens because we are initializing and realizing each CPU before
going to the next, i.e. init and realize CPU0, then init and realize
CPU1 and so on. If we change any persistent state during the validation
of CPU N it will interfere with the init/realization of CPU N+1.
We're using the 'enabled' profile flag to do two distinct things: inform
cpu_init() that we want profile extensions to be enabled, and telling
QMP that a profile is currently enabled in the CPU. We want to be
flexible enough to recognize profile support for all CPUs that has the
extension prerequisites, but we do not want to force the profile code
path if a profile wasn't set too.
Add a new 'present' flag for profiles that will coexist with the 'enabled'
flag. Enabling a profile means "we want to switch on all its mandatory
extensions". A profile is 'present' if we asserted during validation
that the CPU has the needed prerequisites.
This means that the case reported by Björn now results in
RVA22S64.enabled=false and RVA22S64.present=true. QMP will recognize it
as a RVA22 compliant CPU and we won't force the CPU into the profile
path.
[1]
https://lore.kernel.org/qemu-riscv/87y0usiz22....@all.your.base.are.belong.to.us/
Reported-by: Björn Töpel <bj...@kernel.org>
Fixes: 2af005d610 ("target/riscv/tcg: validate profiles during finalize")
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Björn Töpel <bj...@rivosinc.com>
Tested-by: Björn Töpel <bj...@rivosinc.com>
Message-ID: <20250528184407.1451983-4-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 444cffd37b69b06f170aeaedadf1b52be96d4acd
https://github.com/qemu/qemu/commit/444cffd37b69b06f170aeaedadf1b52be96d4acd
Author: Jay Chang <jay.ch...@sifive.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Extend PMP region up to 64
According to the RISC-V Privileged Specification (version >1.12),
RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions
(pmpaddr0–pmpaddr63).
Signed-off-by: Jay Chang <jay.ch...@sifive.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Message-ID: <20250522081236.4050-2-jay.ch...@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 455c0fa9eef7f27e5b50ebd2b6fe3447c4f1ca51
https://github.com/qemu/qemu/commit/455c0fa9eef7f27e5b50ebd2b6fe3447c4f1ca51
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: remove capital 'Z' CPU properties
These properties were deprecated in QEMU 8.2, commit 8043effd9b.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250530134608.1806922-1-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: f31ba686a9387640a905ac70fe682c15c461a134
https://github.com/qemu/qemu/commit/f31ba686a9387640a905ac70fe682c15c461a134
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
target/riscv/cpu.c: add 'sdtrig' in riscv,isa
We have support for sdtrig for awhile but we are not advertising it. It
is enabled by default via the 'debug' flag. Use the same flag to also
advertise sdtrig.
Add an exception in disable_priv_spec_isa_exts() to avoid spamming
warnings for 'sdtrig' for vendor CPUs like sifive_u.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250604174329.1147549-2-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: bab2be19239bc8e586a868eafd1c78a2d55a1a58
https://github.com/qemu/qemu/commit/bab2be19239bc8e586a868eafd1c78a2d55a1a58
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
target/riscv/cpu.c: add 'ssstrict' to riscv, isa
'ssstrict' is a RVA23 profile-defined extension defined as follows:
"No non-conforming extensions are present. Attempts to execute
unimplemented opcodes or access unimplemented CSRs in the standard or
reserved encoding spaces raises an illegal instruction exception that
results in a contained trap to the supervisor-mode trap handler."
In short, we need to throw an exception when accessing unimplemented
CSRs or opcodes. We do that, so let's advertise it.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Message-ID: <20250529202315.1684198-3-dbarb...@ventanamicro.com>
Message-ID: <20250604174329.1147549-3-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 5ee4f21713d51fdf3d8756744ffe92365df8598b
https://github.com/qemu/qemu/commit/5ee4f21713d51fdf3d8756744ffe92365df8598b
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: do better with 'named features' doc
Most of the named features are added directly in isa_edata_arr[], some
of them are also added in riscv_cpu_named_features(). There is a reason
for that, and the existing docs can do better explaining it.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Message-ID: <20250529202315.1684198-4-dbarb...@ventanamicro.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250604174329.1147549-4-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: f9eaa1542be5f7273dec1111a1e17d8ff2a5bcba
https://github.com/qemu/qemu/commit/f9eaa1542be5f7273dec1111a1e17d8ff2a5bcba
Author: Jim Shu <jim....@sifive.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: support atomic instruction fetch (Ziccif)
Support 4-byte atomic instruction fetch when instruction is natural
aligned.
Current implementation is not atomic because it loads instruction twice
for first and last 2 bytes. We load 4 bytes at once to keep the
atomicity. This instruction preload method only applys when instruction
is 4-byte aligned. If instruction is unaligned, it could be across pages
so that preload will trigger additional page fault.
We encounter this issue when doing pressure test of enabling & disabling
Linux kernel ftrace. Ftrace with kernel preemption requires concurrent
modification and execution of instruction, so non-atomic instruction
fetch will cause the race condition. We may fetch the wrong instruction
which is the mixing of 2 instructions.
Also, RISC-V Profile wants to provide this feature by HW. RVA20U64
Ziccif protects the atomicity of instruction fetch when it is
natural aligned.
This commit depends on the atomic read support of translator_ld in
the commit 6a9dfe1984b0c593fb0ddb52d4e70832e6201dd6.
Signed-off-by: Jim Shu <jim....@sifive.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250508094838.19394-1-jim....@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: b0175841fa4f867b4b1219dba72c33392118dd43
https://github.com/qemu/qemu/commit/b0175841fa4f867b4b1219dba72c33392118dd43
Author: Meng Zhuo <mengz...@iscas.ac.cn>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: add max_satp_mode from host cpu
This patch adds max_satp_mode from host kvm cpu setting.
Tested on: Milkv Megrez (Eswin 7700x)
Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931
Signed-off-by: Meng Zhuo <mengz...@iscas.ac.cn>
Message-ID: <20250606034250.181707-1-mengz...@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: cd633bea8b0d30f3418b0dd372116bf3e028e42f
https://github.com/qemu/qemu/commit/cd633bea8b0d30f3418b0dd372116bf3e028e42f
Author: Jay Chang <jay.ch...@sifive.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/csr.c
M target/riscv/machine.c
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Make PMP region count configurable
Previously, the number of PMP regions was hardcoded to 16 in QEMU.
This patch replaces the fixed value with a new `pmp_regions` field,
allowing platforms to configure the number of PMP regions.
If no specific value is provided, the default number of PMP regions
remains 16 to preserve the existing behavior.
A new CPU parameter num-pmp-regions has been introduced to the QEMU
command line. For example:
-cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8
Signed-off-by: Jay Chang <jay.ch...@sifive.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250606072525.17313-3-jay.ch...@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 5000ba0cb1c513283f0a2f2f9742cfe8053dab8d
https://github.com/qemu/qemu/commit/5000ba0cb1c513283f0a2f2f9742cfe8053dab8d
Author: Nutty Liu <liujin...@lanxincomputing.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register
The original implementation incorrectly performed a bitwise AND
operation between the PPN of iova and PPN Mask, leading to an
incorrect PPN field in Translation-reponse register.
The PPN of iova should be set entirely in the PPN field of
Translation-reponse register.
Also remove the code that was used to clear S field since this
field is already zero.
Signed-off-by: Nutty Liu <liujin...@lanxincomputing.com>
Reviewed-by: Tomasz Jeznach <tjezn...@rivosinc.com>
Message-ID: <20250605124848.1248-1-liujin...@lanxincomputing.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 7ec39d0cc945dd81108e08ca37afcfb3c9e5e012
https://github.com/qemu/qemu/commit/7ec39d0cc945dd81108e08ca37afcfb3c9e5e012
Author: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
The SBI spec states, for console write byte:
"This is a blocking SBI call and it will only return after writing the
specified byte to the debug console. It will also return, with
SBI_ERR_FAILED, if there are I/O errors."
Being a blocker call will either succeed writing the byte or error out,
it's feasible to use the blocking qemu_chr_fe_write_all() instead of
qemu_chr_fe_write().
Last but not the least, we will duck possible changes in
qemu_chr_fe_write() where ret = 0 will have a 'zero byte written'
semantic [1] - something that we're not ready to deal in this current
state.
[1]
https://lore.kernel.org/qemu-devel/CAFEAcA_kEndvNtw4EHySXWwQPoGs029yAzZGGBcV=zghaj7...@mail.gmail.com/
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-ID: <20250605094456.1385105-2-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 2b027e73eefab0f9d3a0048564d1b653ba1d7703
https://github.com/qemu/qemu/commit/2b027e73eefab0f9d3a0048564d1b653ba1d7703
Author: Anton Blanchard <ant...@tenstorrent.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/fpu_helper.c
M target/riscv/internals.h
Log Message:
-----------
target/riscv: Fix fcvt.s.bf16 NaN box checking
fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16
quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN.
Signed-off-by: Anton Blanchard <ant...@tenstorrent.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250501114253.594887-1-ant...@tenstorrent.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 61240e3a06dc622d249b530557d5ce03c5854592
https://github.com/qemu/qemu/commit/61240e3a06dc622d249b530557d5ce03c5854592
Author: Florian Lugou <florian.lu...@provenrun.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/char/sifive_uart.c
Log Message:
-----------
hw/char: sifive_uart: Avoid infinite delay of async xmit function
The current handler for TXFIFO writes schedules an async callback to
pop characters from the queue. When software writes to TXFIFO faster
than the async callback delay (100ns), the timer may be pushed back
while the previous character has not be dequeued yet. This happens in
particular when using -icount with small shift values. This is
especially worrysome when software repetitively issues amoor.w
instructions (as suggested by SiFive specification) and the FIFO is
full, leading to the callback being infinitly pushed back.
This commit fixes the issue by never pushing back the timer, only
updating it if it is not already active.
Signed-off-by: Florian Lugou <florian.lu...@provenrun.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250605101255.797162-1-florian.lu...@provenrun.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 81a245091fff2651f14004d1820f7ee77dd4f0fc
https://github.com/qemu/qemu/commit/81a245091fff2651f14004d1820f7ee77dd4f0fc
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Fix clint base address type
The address is a hardware address, so use hwaddr for consistency with
the rest of the machine.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-2-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 16adb1f5d7ac548983f1b59d8e15f2eb5e51ae2c
https://github.com/qemu/qemu/commit/16adb1f5d7ac548983f1b59d8e15f2eb5e51ae2c
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for clint
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-3-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 349500bfb8523c94f88da4bfc41a22ccbba19055
https://github.com/qemu/qemu/commit/349500bfb8523c94f88da4bfc41a22ccbba19055
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for memory
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-4-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 4b7b4f9cb4fd4b569661e690c593780332d7291a
https://github.com/qemu/qemu/commit/4b7b4f9cb4fd4b569661e690c593780332d7291a
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for aplic
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-5-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: dd3d4fd9923082d8d2ad6ed71b4be05dad36b601
https://github.com/qemu/qemu/commit/dd3d4fd9923082d8d2ad6ed71b4be05dad36b601
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for aclint
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-6-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 507161b5f53ae37e2aeeb99e558485146546331e
https://github.com/qemu/qemu/commit/507161b5f53ae37e2aeeb99e558485146546331e
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for plic
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-7-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: ad41a7022bd10a2db922cd4e314af2b2f1b6caa0
https://github.com/qemu/qemu/commit/ad41a7022bd10a2db922cd4e314af2b2f1b6caa0
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for virtio
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-8-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 08454fc3f5e43338c2e13dc040a2ebe77834945f
https://github.com/qemu/qemu/commit/08454fc3f5e43338c2e13dc040a2ebe77834945f
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for reset
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-9-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 4f1572d6f191f4618b30be3fda7344461910a03f
https://github.com/qemu/qemu/commit/4f1572d6f191f4618b30be3fda7344461910a03f
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for uart
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-10-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: faa991f67888ae25744f535ad73043900729c024
https://github.com/qemu/qemu/commit/faa991f67888ae25744f535ad73043900729c024
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for rtc
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-11-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 0e7e0ee63939a09b098279a475698d73243ffc76
https://github.com/qemu/qemu/commit/0e7e0ee63939a09b098279a475698d73243ffc76
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for iommu
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-12-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 2454fc95ece3c73f649e21621775bcbe859d28ec
https://github.com/qemu/qemu/commit/2454fc95ece3c73f649e21621775bcbe859d28ec
Author: Joel Stanley <j...@jms.id.au>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Use setprop_sized_cells for pcie
The current device tree property uses two cells for the address (and for
the size), but assumes the they are less than 32 bits by hard coding the
high cell to zero.
Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper
and lower 32 bits across cells.
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Joel Stanley <j...@jms.id.au>
Message-ID: <20250604025450.85327-13-j...@jms.id.au>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 60aab7ad11e6cd8a82420ed6a18416853c0fb762
https://github.com/qemu/qemu/commit/60aab7ad11e6cd8a82420ed6a18416853c0fb762
Author: Huang Borong <3543977...@qq.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Add BOSC's Xiangshan Kunminghu CPU
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
high-performance RISC-V processor. More details can be found at:
https://github.com/OpenXiangShan/XiangShan
Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
categorized based on four RISC-V specifications: Volume I: Unprivileged
Architecture, Volume II: Privileged Architecture, AIA, and RVA23. The
extensions within each category are organized according to the chapter
order in the specifications.
Signed-off-by: Yu Hu <h...@bosc.ac.cn>
Signed-off-by: Ran Wang <wang...@bosc.ac.cn>
Signed-off-by: Borong Huang <3543977...@qq.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250425122212.364-1-wang...@bosc.ac.cn>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 29abd3d112c380b8019a77ebad65f61addfb812d
https://github.com/qemu/qemu/commit/29abd3d112c380b8019a77ebad65f61addfb812d
Author: Huang Borong <3543977...@qq.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M MAINTAINERS
M configs/devices/riscv64-softmmu/default.mak
A docs/system/riscv/xiangshan-kunminghu.rst
M docs/system/target-riscv.rst
M hw/riscv/Kconfig
M hw/riscv/meson.build
A hw/riscv/xiangshan_kmh.c
A include/hw/riscv/xiangshan_kmh.h
Log Message:
-----------
hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
This implementation provides emulation for the Xiangshan Kunminghu
FPGA prototype platform, including support for UART, CLINT, IMSIC,
and APLIC devices. More details can be found at
https://github.com/OpenXiangShan/XiangShan
Signed-off-by: qinshaoqing <qinshaoq...@bosc.ac.cn>
Signed-off-by: Yang Wang <wangy...@bosc.ac.cn>
Signed-off-by: Yu Hu <819258...@qq.com>
Signed-off-by: Ran Wang <wang...@bosc.ac.cn>
Signed-off-by: Borong Huang <3543977...@qq.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Message-ID: <20250617074222.17618-1-wang...@bosc.ac.cn>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: b5092b3db23391d6ee770123715b76b85169d977
https://github.com/qemu/qemu/commit/b5092b3db23391d6ee770123715b76b85169d977
Author: Max Chou <max.c...@sifive.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Fix missing exit TB flow for ldff_trans
According to the V spec, the vector fault-only-first load instructions
may change the VL CSR.
So the ldff_trans TCG translation function should generate the
lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to
make sure the vl_eq_vlmax TB flag is correct.
Signed-off-by: Max Chou <max.c...@sifive.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-ID: <20250627133013.443997-1-max.c...@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: bc2200134c1229a83bbcd8e75ab541ca110609f6
https://github.com/qemu/qemu/commit/bc2200134c1229a83bbcd8e75ab541ca110609f6
Author: liu.xuem...@zte.com.cn <liu.xuem...@zte.com.cn>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/intc/riscv_aplic.c
M hw/intc/riscv_imsic.c
Log Message:
-----------
migration: Fix migration failure when aia is configured as aplic-imsic
Address an error in migration when aia is configured as 'aplic-imsic' in
riscv kvm vm by adding riscv_aplic_state_needed() and
riscv_imsic_state_needed() to determine whether the corresponding sates are
needed.
Previously, the fields in the vmsds of 'riscv_aplic' and 'riscv_imsic' can
only be initialized under certain special conditions in commit 95a97b3fd2.
However, the corresponding ses of these vmsds are inserted into the
savevm_state.handlers unconditionally. This led to migration failure
characterized by uninitialized fields when save vm state:
qemu-system-riscv64: ../migration/vmstate.c:433: vmstate_save_state_v:
Assertion 'first_elem || !n_elems || !size' failed.
Fixes: 95a97b3fd2 ("target/riscv: update APLIC and IMSIC to support KVM AIA")
Signed-off-by: Xuemei Liu <liu.xuem...@zte.com.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20250616150034827wuhs_ffe3qm8cqfxt7...@zte.com.cn>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: b3452452e64be647fef98d2dce16c3f5c149235a
https://github.com/qemu/qemu/commit/b3452452e64be647fef98d2dce16c3f5c149235a
Author: Charalampos Mitrodimas <charmi...@posteo.net>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/csr.c
M target/riscv/internals.h
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Fix MEPC/SEPC bit masking for IALIGN
According to the RISC-V Privileged Architecture specification, the low
bit of MEPC/SEPC must always be zero. When IALIGN=32, the two low bits
must be zero.
This commit fixes the behavior of MEPC/SEPC CSR reads and writes, and
the implicit reads by MRET/SRET instructions to properly mask the
lowest bit(s) based on whether the C extension is enabled:
- When C extension is enabled (IALIGN=16): mask bit 0
- When C extension is disabled (IALIGN=32): mask bits [1:0]
Previously, when vectored mode bits from STVEC (which sets bit 0 for
vectored mode) were written to MEPC, the bits would not be cleared
correctly, causing incorrect behavior on MRET.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2855
Signed-off-by: Charalampos Mitrodimas <charmi...@posteo.net>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Message-ID: <20250703182157.281320-2-charmi...@posteo.net>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: a1f44e0c59081afceb5e2b389b6de96602f73977
https://github.com/qemu/qemu/commit/a1f44e0c59081afceb5e2b389b6de96602f73977
Author: Charalampos Mitrodimas <charmi...@posteo.net>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M tests/tcg/riscv64/Makefile.softmmu-target
A tests/tcg/riscv64/test-mepc-masking.S
Log Message:
-----------
tests/tcg/riscv64: Add test for MEPC bit masking
Add a regression test to verify that MEPC properly masks the lower
bits when an address with mode bits is written to it, as required by
the RISC-V Privileged Architecture specification.
The test sets STVEC to an address with bit 0 set (vectored mode),
triggers an illegal instruction exception, copies STVEC to MEPC in the
trap handler, and verifies that MEPC masks bits [1:0] correctly for
IALIGN=32.
Without the fix, MEPC retains the mode bits (returns non-zero/FAIL).
With the fix, MEPC clears bits [1:0] (returns 0/PASS).
Signed-off-by: Charalampos Mitrodimas <charmi...@posteo.net>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Message-ID: <20250703182157.281320-3-charmi...@posteo.net>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: 5625817e8b77715b18d0ce3bfcc59fb337e387d8
https://github.com/qemu/qemu/commit/5625817e8b77715b18d0ce3bfcc59fb337e387d8
Author: Vasilis Liaskovitis <vliaskovi...@suse.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Add a property to set vill bit on reserved usage of vsetvli
instruction
Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1
and rd arguments are x0.
In this case, if the new property is true, only the vill bit will be set.
See
https://github.com/riscv/riscv-isa-manual/blob/main/src/v-st-ext.adoc#avl-encoding
According to the spec, the above use cases are reserved, and
"Implementations may set vill in either case."
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2422
Signed-off-by: Vasilis Liaskovitis <vliaskovi...@suse.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Message-ID: <20250618213542.22873-1-vliaskovi...@suse.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: dc8bffc4eb0a93d3266cea1b17f8848dea5b915c
https://github.com/qemu/qemu/commit/dc8bffc4eb0a93d3266cea1b17f8848dea5b915c
Author: Alexandre Ghiti <alexgh...@rivosinc.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M hw/riscv/riscv-iommu-bits.h
M hw/riscv/riscv-iommu.c
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/cpu_helper.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target: riscv: Add Svrsw60t59b extension support
The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Reviewed-by: Deepak Gupta <de...@rivosinc.com>
Signed-off-by: Alexandre Ghiti <alexgh...@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Nutty Liu<liujin...@lanxincomputing.com>
Message-ID: <20250702-dev-alex-svrsw60b59b_v2-v2-1-504ddf0f8...@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Commit: a876b05d38c813501e60fb50c8a45b30a965e902
https://github.com/qemu/qemu/commit/a876b05d38c813501e60fb50c8a45b30a965e902
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/system/arm/aspeed.rst
M hw/arm/Kconfig
M hw/arm/aspeed.c
M hw/arm/aspeed_eeprom.c
M hw/arm/aspeed_eeprom.h
M hw/misc/aspeed_scu.c
M hw/misc/aspeed_sdmc.c
M include/hw/arm/aspeed.h
M tests/functional/aspeed.py
M tests/functional/meson.build
A tests/functional/test_arm_aspeed_catalina.py
A tests/functional/test_arm_aspeed_gb200nvl_bmc.py
A tests/qtest/aspeed_scu-test.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'pull-aspeed-20250704' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Improved AST2700 SoC modeling (SDMC, SCU)
* Fixed hardware strapping of 'bletchley-bmc' machine
* Added new Meta 'catalina-bmc' machine and functional test using OpenBMC
* Improved AST2600 SCU protection key modeling
* Introduced AST2600 SCU unit tests
* Deprecated 'ast2700a0-evb' machine
* Added new NVIDIA 'gb200-bmc' machine and functional test using OpenBMC
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmhnknUACgkQUaNDx8/7
# 7KFPDBAAiHW7cu64JszAPk3SBHR8b021JpOrnF9Xp/UHMjNt0Kuazm6jkc/FeOJf
# yOKGfvuZUiLLcTrN8iCrVjjxIMKlzQP4KQEFaAPyxvKZo6j4czFZQ7AHS3G28w8l
# qrF4UsOhgQ6TL6fXMyqzDSLDEf5o/1ZCn1t+wkuDeVR7YVoAFj/si/A+qmIGQODJ
# egVmBopUzGrnGCcZREcKfJKmx1JOfVGFpm5HHPlazCaNTyKynd4rm2qP2St1eDEQ
# vOvSBZXKUHmpV9ckdY+Hp0VHvO2oIifDTN+Zbd2XT9RxO36VMnQxiSxOZOj/aRWa
# dc87OprPKjjS7Tbg7SZF7ySgfOShXWtNOwLuyrlw6BFsaHtwU2VP/mYR/Tfz/1Lw
# 57ufAj04nh8bWp7LApXyui53/1X431oBFji6agWnonMut+e5Xv0JKdBeCu2y8Fj4
# wPpiNcaa8AgHUuJ8T/WXrogeAYXYPI7z1iCY5tX9xffvcL6B3cVLGlI+mXoCIK7O
# MTuS5d8CB0gQondLS0Y86ls5pM3RkW6izragH38ukuubKIRq1hjxFDBnF8AQJl7A
# pUWTTxhxNZaJie0F5grD7aCVPCSSr1ck1V3zbW/ffVX+7kEtCBW/Zk4qfw9/SGxd
# 2QKbstRPNgTl78EKquYwipFVNyHTP/W8iXfxwpFALKBJFkmzAjQ=
# =i7wx
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 04 Jul 2025 04:36:05 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <c...@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <c...@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20250704' of https://github.com/legoater/qemu:
tests/functional: Add gb200 tests
hw/arm/aspeed: Add GB200 BMC target
docs: add support for gb200-bmc
hw/arm/aspeed: Add second SPI chip to Aspeed model
aspeed: Deprecate the ast2700a0-evb machine
tests/qtest: Add test for ASPEED SCU
hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly
hw/arm/aspeed: add Catalina machine type
hw/arm/aspeed: bletchley: update hw strap values
hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700
hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 563ac3d18129a2770a285cc16c20ad50c8adc7c0
https://github.com/qemu/qemu/commit/563ac3d18129a2770a285cc16c20ad50c8adc7c0
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M .b4-config
M Makefile
M accel/kvm/kvm-all.c
M backends/iommufd.c
M backends/trace-events
M docs/devel/migration/CPR.rst
M hw/i386/Kconfig
M hw/vfio-user/container.c
M hw/vfio/ap.c
M hw/vfio/ccw.c
M hw/vfio/container-base.c
A hw/vfio/cpr-iommufd.c
M hw/vfio/cpr-legacy.c
M hw/vfio/cpr.c
M hw/vfio/device.c
M hw/vfio/helpers.c
A hw/vfio/iommufd-stubs.c
M hw/vfio/iommufd.c
M hw/vfio/meson.build
M hw/vfio/pci.c
M hw/vfio/pci.h
M hw/vfio/platform.c
M hw/vfio/trace-events
M include/exec/cpu-common.h
M include/hw/vfio/vfio-container-base.h
M include/hw/vfio/vfio-cpr.h
M include/hw/vfio/vfio-device.h
M include/migration/cpr.h
M include/system/iommufd.h
M include/system/kvm.h
M migration/cpr.c
M qapi/migration.json
M system/physmem.c
Log Message:
-----------
Merge tag 'pull-vfio-20250704' of https://github.com/legoater/qemu into
staging
vfio queue:
* Added small cleanups for b4 and scope
* Restricted TDX build to 64-bit target
* Fixed issues introduced in first part of VFIO live update support
* Added full VFIO live update support
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmhnlBMACgkQUaNDx8/7
# 7KFOxw//dIPpGcYIjEGpIkIh6NF3VK6xmDAG0aZEeM+5fCzdor2DPkD7ZPyqND3S
# /YkR8GSOHd+Qm5W+73LHOdV5RFMt4wagyHiAKUMpEFHY7ZLduxIXlACoUo+F5cnh
# SUnhC6KX7Gu1/Nndb4X4w6SNOyhoRKtQ2EqpRsrGdIaBkX8s6w2jF/INPTPdpg73
# lulJZCAFNzyIWytck9ohJf8To9IsvkCXTF6mcywURa9MBaAarRttXoFjuZsXb7zn
# NqGVtantNAaJmKu26X3ScUWn9P02WryhPB6KT7+B3G/b87Su1cnbAwYakNSFPJIx
# I/gaw0EPzHM+b6mavA4IdvKDJGR7GMvpJEGqUEpntc6FJ3+g1B7qsedgeBUc/RKB
# UaRmtYbvlMv5wSmaLcxsT3S3BnABbrd4EedZX5uOBFMrtnTiOqrMUEcoMaf5ogvN
# KlJkrjNQkfHxTbp5G+nXHuTzae3k2Ylm196b2yhgARfUL70jiak/B+ADeezVcVmW
# 6ZpotrAvMxu9RlFdxTSbL0/lR0rfKZTecqMOSFA+FlmjcTJ0QW1SbweMdsfgW/uU
# /2Hfmw6zUQ80/tMqYMztFWsiov7C8a8ZMmuZwDQp+AdCVGgFEigfNJVQYgujbqKz
# g9Ta9cNPyvF5hpnml5u8IzAzM95HrhIPFmmpUBZyWOCeL6chSHk=
# =Cu7b
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 04 Jul 2025 04:42:59 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <c...@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <c...@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-vfio-20250704' of https://github.com/legoater/qemu: (27 commits)
vfio: doc changes for cpr
vfio/container: delete old cpr register
iommufd: preserve DMA mappings
vfio/iommufd: change process
vfio/iommufd: reconstruct hwpt
vfio/iommufd: reconstruct device
vfio/iommufd: preserve descriptors
vfio/iommufd: cpr state
migration: vfio cpr state hook
vfio/iommufd: register container for cpr
vfio/iommufd: device name blocker
vfio/iommufd: add vfio_device_free_name
vfio/iommufd: invariant device name
vfio/iommufd: use IOMMU_IOAS_MAP_FILE
physmem: qemu_ram_get_fd_offset
backends/iommufd: change process ioctl
backends/iommufd: iommufd_backend_map_file_dma
migration: cpr_get_fd_param helper
migration: close kvm after cpr
vfio-pci: preserve INTx
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 989dd906ed5556563a57b32ae7abf9db5e1f38ba
https://github.com/qemu/qemu/commit/989dd906ed5556563a57b32ae7abf9db5e1f38ba
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M MAINTAINERS
M accel/accel-common.c
M accel/accel-system.c
M accel/dummy-cpus.c
A accel/dummy-cpus.h
M accel/hvf/hvf-accel-ops.c
M accel/hvf/hvf-all.c
M accel/kvm/kvm-accel-ops.c
M accel/kvm/kvm-all.c
M accel/qtest/qtest.c
M accel/stubs/kvm-stub.c
M accel/stubs/meson.build
A accel/stubs/nvmm-stub.c
A accel/stubs/whpx-stub.c
M accel/tcg/internal-common.h
M accel/tcg/monitor.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/tcg-all.c
M accel/xen/xen-all.c
M bsd-user/main.c
M hmp-commands-info.hx
M include/hw/core/cpu.h
M include/qemu/accel.h
M include/system/accel-ops.h
M include/system/cpus.h
M include/system/hvf.h
M include/system/hvf_int.h
M include/system/hw_accel.h
M include/system/kvm.h
M include/system/nvmm.h
M include/system/whpx.h
M linux-user/main.c
M monitor/hmp-cmds-target.c
M qapi/machine.json
M system/cpus.c
M system/memory.c
M target/arm/hvf/hvf.c
M target/i386/hvf/hvf.c
M target/i386/hvf/x86hvf.c
M target/i386/nvmm/nvmm-accel-ops.c
M target/i386/nvmm/nvmm-all.c
M target/i386/whpx/whpx-accel-ops.c
M target/i386/whpx/whpx-all.c
M tests/qtest/qmp-cmd-test.c
Log Message:
-----------
Merge tag 'accel-20250704' of https://github.com/philmd/qemu into staging
Accelerators patches
- Generic API consolidation, cleanups (dead code removal, documentation added)
- Remove monitor TCG 'info opcount' and @x-query-opcount
- Have HVF / NVMM / WHPX use generic CPUState::vcpu_dirty field
- Expose nvmm_enabled() and whpx_enabled() to common code
- Have hmp_info_registers() dump vector registers
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmhnql4ACgkQ4+MsLN6t
# wN6Lfg//R4h6dyAg02hyopwb/DSI97hAsD9kap15ro1qszYrIOkJcEPoE37HDi6d
# O0Ls+8NPpJcnMwdghHvVaRGoIH2OY5ogXKo6UK1BbOn8iAGxRrT/IPVCyFbPmQoe
# Bk78Z/wne/YgCXiW4HGHSJO5sL04AQqcFYnwjisHHf3Ox8RR85LbhWqthZluta4i
# a/Y8W5UO7jfwhAl1/Zb2cU+Rv75I6xcaLQAfmbt4j+wHP52I2cjLpIYo4sCn+ULJ
# AVX4q4MKrkDrr6CYPXxdGJzYEzVn9evynVcQoRzL6bLZFMpa284AzVd3kQg9NWAb
# p1hvKJTA57q4XDoD50qVGLhP207VVSUcdm0r2ZJA2jag5ddoT+x2talz8/f6In1b
# 7BrSM/pla8x9KvTne/ko0wSL0o2dOWyig8mBxARLZWPxk+LBVs1PBZfvn+3j1pYA
# rWV25Ht4QJlUYMbe3NvEIomsVThKg8Fh3b4mEuyPM+LZ1brgmhrzJG1SF+G4fH8A
# aig/RVqgNHtajSnG4A723k2/QzlvnAiT7E3dKB5FogjTcVzFRaWFKsUb4ORqsCAz
# c/AheCJY4PP3pAnb0ODISSVviXwAXqCLbtZhDGhHNYl3C69EyGPPMiVxCaIxKDxU
# bF7AIYhRTTMyNSbnkcRS3UDO/gZS7x5/K+/YAM9akQEYADIodYM=
# =Vb39
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 04 Jul 2025 06:18:06 EDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4...@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'accel-20250704' of https://github.com/philmd/qemu: (31 commits)
MAINTAINERS: Add me as reviewer of overall accelerators section
monitor/hmp-cmds-target: add CPU_DUMP_VPU in hmp_info_registers()
accel: Pass AccelState argument to gdbstub_supported_sstep_flags()
accel: Remove unused MachineState argument of AccelClass::setup_post()
accel: Directly pass AccelState argument to AccelClass::has_memory()
accel/kvm: Directly pass KVMState argument to do_kvm_create_vm()
accel/kvm: Prefer local AccelState over global MachineState::accel
accel/tcg: Prefer local AccelState over global current_accel()
accel: Propagate AccelState to AccelClass::init_machine()
accel: Keep reference to AccelOpsClass in AccelClass
accel: Expose and register generic_handle_interrupt()
accel/dummy: Extract 'dummy-cpus.h' header from 'system/cpus.h'
accel/whpx: Expose whpx_enabled() to common code
accel/nvmm: Expose nvmm_enabled() to common code
accel/system: Document cpu_synchronize_state_post_init/reset()
accel/system: Document cpu_synchronize_state()
accel/kvm: Remove kvm_cpu_synchronize_state() stub
accel/whpx: Replace @dirty field by generic CPUState::vcpu_dirty field
accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty field
accel/hvf: Replace @dirty field by generic CPUState::vcpu_dirty field
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: e240f6cc25917f3138d9e95e0343ae23b63a3f8c
https://github.com/qemu/qemu/commit/e240f6cc25917f3138d9e95e0343ae23b63a3f8c
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-04 (Fri, 04 Jul 2025)
Changed paths:
M MAINTAINERS
M configs/devices/riscv64-softmmu/default.mak
A docs/system/riscv/xiangshan-kunminghu.rst
M docs/system/target-riscv.rst
M hw/char/sifive_uart.c
M hw/intc/riscv_aclint.c
M hw/intc/riscv_aplic.c
M hw/intc/riscv_imsic.c
M hw/riscv/Kconfig
M hw/riscv/meson.build
M hw/riscv/riscv-iommu-bits.h
M hw/riscv/riscv-iommu.c
M hw/riscv/virt.c
A hw/riscv/xiangshan_kmh.c
A include/hw/riscv/xiangshan_kmh.h
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/internals.h
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/riscv-qmp-cmds.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/time_helper.c
M target/riscv/time_helper.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
M tests/data/acpi/riscv64/virt/RHCT
M tests/tcg/riscv64/Makefile.softmmu-target
A tests/tcg/riscv64/test-mepc-masking.S
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20250704' of
https://github.com/alistair23/qemu into staging
Second RISC-V PR for 10.1
* sstc extension fixes
* Fix zama16b order in isa_edata_arr
* Profile handling fixes
* Extend PMP region up to 64
* Remove capital 'Z' CPU properties
* Add missing named features
* Support atomic instruction fetch (Ziccif)
* Add max_satp_mode from host cpu
* Extend and configure PMP region count
* Fix PPN field of Translation-reponse register
* Use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
* Fix fcvt.s.bf16 NaN box checking
* Avoid infinite delay of async xmit function
* Device tree reg cleanups
* Add Kunminghu CPU and platform
* Fix missing exit TB flow for ldff_trans
* Fix migration failure when aia is configured as aplic-imsic
* Fix MEPC/SEPC bit masking for IALIGN
* Add a property to set vill bit on reserved usage of vsetvli instruction
* Add Svrsw60t59b extension support
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmhntt4ACgkQr3yVEwxT
# gBMaCQ/9E+LeRY59nz3K3XXUw6XLBfaDECXbKzIn0GM1yXeWTX4dB2h2hoGWdu3R
# CRPxWHECN7CeJhd2J23eLfOi+fTUeppJBeR7TcGyoXVC+y0knZv/clQ3OvMFYcgV
# xjzzu1yipQlXwY+kmDZ6qL5up/Q+faw7tRaePZaJheRGYpVRnjoKUZq5fe4Ug4RU
# Xg6Di86eYyk+Jo0g2exvtzy1rX2eBp7Hz200wWiH5Z1B+3NzgMUHrHuJfNAz8zAt
# n8uvruvaLGGtWcQJauRXlAELR6k9tmkfq1Mbqf3FK6muaQCtFD7PXXnjL/rU/z20
# hhxj0psOhBJLd0W5wQ3vLnDf6Wve9zmUdTR9kI0Kt3xUUdfeBuzKcU06F/G8wEsZ
# 2sIYQqt0mxoJboY2lpje7TO4H9gvAf76WBOV10FV2gWsqWu2rZQ6herdq3YZYkHX
# purUTgyjHn4jl2Y3Kzj0Gq1SHo0yaA/sD6xNR8X+JqljSruDxtOFU7wkKBbewoIg
# OSfwemjRUVsPQZ958042ntwJt81v1604Oky8JSFr5eCFx/aoLJ1vDYh7BKZAogNH
# uB/YigGq9+/MVzqJpZI+kZkd+1nzaizeL0FUPRTq0jFA2u+vc3J3svQ/jNXDH2c+
# 5nGuhbkvT0ptmVMBqFV2vjPh6+ScR8t03wHdQ4PmDoXC3o9zbbU=
# =CfRy
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 04 Jul 2025 07:11:26 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alist...@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20250704' of https://github.com/alistair23/qemu: (40
commits)
target: riscv: Add Svrsw60t59b extension support
target/riscv: Add a property to set vill bit on reserved usage of vsetvli
instruction
tests/tcg/riscv64: Add test for MEPC bit masking
target/riscv: Fix MEPC/SEPC bit masking for IALIGN
migration: Fix migration failure when aia is configured as aplic-imsic
target/riscv: rvv: Fix missing exit TB flow for ldff_trans
hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
target/riscv: Add BOSC's Xiangshan Kunminghu CPU
hw/riscv/virt: Use setprop_sized_cells for pcie
hw/riscv/virt: Use setprop_sized_cells for iommu
hw/riscv/virt: Use setprop_sized_cells for rtc
hw/riscv/virt: Use setprop_sized_cells for uart
hw/riscv/virt: Use setprop_sized_cells for reset
hw/riscv/virt: Use setprop_sized_cells for virtio
hw/riscv/virt: Use setprop_sized_cells for plic
hw/riscv/virt: Use setprop_sized_cells for aclint
hw/riscv/virt: Use setprop_sized_cells for aplic
hw/riscv/virt: Use setprop_sized_cells for memory
hw/riscv/virt: Use setprop_sized_cells for clint
hw/riscv/virt: Fix clint base address type
...
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Compare: https://github.com/qemu/qemu/compare/c77283dd5d79...e240f6cc2591
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications
