Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 2251f9ac9261cda05b6b19e9ba329b15d9d89bae
https://github.com/qemu/qemu/commit/2251f9ac9261cda05b6b19e9ba329b15d9d89bae
Author: Fabiano Rosas <faro...@suse.de>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M migration/migration-hmp-cmds.c
Log Message:
-----------
migration: HMP: Fix possible out-of-bounds access
Coverity has caught a bug in the formatting of time intervals for
postcopy latency distribution display in 'info migrate'.
While bounds checking the labels array, sizeof is incorrectly being
used. ARRAY_SIZE is the correct form of obtaining the size of an
array.
Fixes: 3345fb3b6d ("migration/postcopy: Add latency distribution report for
blocktime")
Resolves: Coverity CID 1612248
Suggested-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20250716182648.30202-2-faro...@suse.de
Signed-off-by: Fabiano Rosas <faro...@suse.de>
Commit: fd1514cbd97bcad5b3dc5d002cab6fee4d7cd45e
https://github.com/qemu/qemu/commit/fd1514cbd97bcad5b3dc5d002cab6fee4d7cd45e
Author: Fabiano Rosas <faro...@suse.de>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M migration/migration-hmp-cmds.c
Log Message:
-----------
migration: HMP: Fix postcopy latency distribution label
Fix the loop condition to avoid having a label with "1000 us" instead
of "1 ms".
Reported-by: Prasad Pandit <ppan...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Link: https://lore.kernel.org/qemu-devel/20250716182648.30202-3-faro...@suse.de
Signed-off-by: Fabiano Rosas <faro...@suse.de>
Commit: eaec556bc88cc1196f7bbf23d5de311aac1d812f
https://github.com/qemu/qemu/commit/eaec556bc88cc1196f7bbf23d5de311aac1d812f
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M migration/migration-hmp-cmds.c
Log Message:
-----------
migration: show error message when postcopy fails
The 'info migrate' command only shows the error message when the
migration state is 'failed'. When postcopy is used, however,
the 'postcopy-paused' state is used instead of 'failed', so we
must show the error message there too.
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250721133913.2914669-1-berra...@redhat.com
[line break to satisfy checkpatch]
Signed-off-by: Fabiano Rosas <faro...@suse.de>
Commit: 24ad5e19952b326796c8a3a1595c57ff180dab84
https://github.com/qemu/qemu/commit/24ad5e19952b326796c8a3a1595c57ff180dab84
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M crypto/tlssession.c
M include/crypto/tlssession.h
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
crypto: implement workaround for GNUTLS thread safety problems
When TLS 1.3 is negotiated on a TLS session, GNUTLS will perform
automatic rekeying of the session after 16 million records. This
is done for all algorithms except CHACHA20_POLY1305 which does
not require rekeying.
Unfortunately the rekeying breaks GNUTLS' promise that it is safe
to use a gnutls_session_t object concurrently from multiple threads
if they are exclusively calling gnutls_record_send/recv.
This patch implements a workaround for QEMU that adds a mutex lock
around any gnutls_record_send/recv call to serialize execution
within GNUTLS code. When GNUTLS calls into the push/pull functions
we can release the lock so the OS level I/O calls can at least
have some parallelism.
The big downside of this is that the actual encryption/decryption
code is fully serialized, which will halve performance of that
cipher operations if two threads are contending.
The workaround is not enabled by default, since most use of GNUTLS
in QEMU does not tickle the problem, only non-multifd migration
with a return path open is affected. Fortunately the migration
code also won't trigger the halving of performance, since only
the outbound channel diretion needs to sustain high data rates,
the inbound direction is low volume.
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250718150514.2635338-2-berra...@redhat.com
[add stub for qcrypto_tls_session_require_thread_safety; fix unused var]
Signed-off-by: Fabiano Rosas <faro...@suse.de>
Commit: edea818371bd7179b55f38d3b113d342251d8f9b
https://github.com/qemu/qemu/commit/edea818371bd7179b55f38d3b113d342251d8f9b
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M include/io/channel.h
M io/channel-tls.c
Log Message:
-----------
io: add support for activating TLS thread safety workaround
Add a QIO_CHANNEL_FEATURE_CONCURRENT_IO feature flag.
If this is set on a QIOChannelTLS session object, the TLS
session will be marked as requiring thread safety, which
will activate the workaround for GNUTLS bug 1717 if needed.
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250718150514.2635338-3-berra...@redhat.com
Signed-off-by: Fabiano Rosas <faro...@suse.de>
Commit: eb3618e9e259ef93f5a1a76867fbccae540fcd61
https://github.com/qemu/qemu/commit/eb3618e9e259ef93f5a1a76867fbccae540fcd61
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M migration/tls.c
Log Message:
-----------
migration: activate TLS thread safety workaround
When either the postcopy or return path capabilities are
enabled, the migration code will use the primary channel
for bidirectional I/O.
If either of those capabilities are enabled, the migration
code needs to mark the channel as expecting concurrent I/O
in order to activate the thread safety workarounds for
GNUTLS bug 1717
Closes: https://gitlab.com/qemu-project/qemu/-/issues/1937
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250718150514.2635338-4-berra...@redhat.com
Signed-off-by: Fabiano Rosas <faro...@suse.de>
Commit: 0db6f798024ea6f57ecf2020209b761b50a01d71
https://github.com/qemu/qemu/commit/0db6f798024ea6f57ecf2020209b761b50a01d71
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-07-22 (Tue, 22 Jul 2025)
Changed paths:
M crypto/tlssession.c
M crypto/trace-events
Log Message:
-----------
crypto: add tracing & warning about GNUTLS countermeasures
We want some visibility on stderr when the GNUTLS thread
safety countermeasures are activated, to encourage people
to get the real fix deployed (once it exists). Some trace
points will also help if we see any further wierd crash
scenario we've not anticipated.
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Fabiano Rosas <faro...@suse.de>
Link:
https://lore.kernel.org/qemu-devel/20250718150514.2635338-5-berra...@redhat.com
[add missing include]
Signed-off-by: Fabiano Rosas <faro...@suse.de>
Commit: c4103b27973653a7a9f64244de8fb5243e4397c5
https://github.com/qemu/qemu/commit/c4103b27973653a7a9f64244de8fb5243e4397c5
Author: Harsh Prateek Bora <hars...@linux.ibm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Adding myself as a co-maintainer for ppc/spapr
Have been contributing in ppc/spapr and related areas for quite some
time as a contributor and reviewer. I think its time to step up as a
co-maintainer to help with maintainer activities.
Signed-off-by: Harsh Prateek Bora <hars...@linux.ibm.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250724100623.3071131-2-hars...@linux.ibm.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 1da3e7f863d65bb850a7662c6b8dfba623ac7cb7
https://github.com/qemu/qemu/commit/1da3e7f863d65bb850a7662c6b8dfba623ac7cb7
Author: Harsh Prateek Bora <hars...@linux.ibm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Adding myself as reviewer for PPC KVM cpus.
Have been contributing in ppc/spapr from tcg/kvm perspective, stepping
up to help with patch reviews and get notified of incoming changes.
Signed-off-by: Harsh Prateek Bora <hars...@linux.ibm.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250724100623.3071131-3-hars...@linux.ibm.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 884216cf419bb56664e3a8e7c0ce19d180fe2b24
https://github.com/qemu/qemu/commit/884216cf419bb56664e3a8e7c0ce19d180fe2b24
Author: Chinmay Rath <ra...@linux.ibm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add myself as reviewer for PowerPC TCG CPUs
I have been working on Power ISA for a long time now and have mostly
contributed in TCG instruction translation area (moved 300+ instructions to
decodetree as of yet) and would like to continue contributing to PPC TCG in
best possible ways I can. I think it's time to step up and assist in reviewing
related patches to enable myself contribute more effectively in this direction.
Signed-off-by: Chinmay Rath <ra...@linux.ibm.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Signed-off-by: Harsh Prateek Bora <hars...@linux.ibm.com>
Link:
https://lore.kernel.org/qemu-devel/20250724100623.3071131-4-hars...@linux.ibm.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 01286ee41ea3fc030a171dc5813945370f18955b
https://github.com/qemu/qemu/commit/01286ee41ea3fc030a171dc5813945370f18955b
Author: Aditya Gupta <adit...@linux.ibm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add myself as a reviewer of PowerNV emulation
Proposing myself as a reviewer in the PowerNV emulation in QEMU
Have been working on PowerNV QEMU for sometime, with contributions in
Power11, MPIPL and minor fixes and things such as dtb support
Cc: Cédric Le Goater <c...@kaod.org>
Cc: Frédéric Barrat <fbar...@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mah...@linux.ibm.com>
Cc: Madhavan Srinivasan <ma...@linux.ibm.com>
Cc: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Aditya Gupta <adit...@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <hars...@linux.ibm.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250724100623.3071131-5-hars...@linux.ibm.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 076b4306f9b6743059592e9632b149ac7708fa40
https://github.com/qemu/qemu/commit/076b4306f9b6743059592e9632b149ac7708fa40
Author: Gautam Menghani <gau...@linux.ibm.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add myself as a reviewer for XIVE
Proposing myself as a reviewer for XIVE on PPC.
I have been looking at XIVE in context of KVM internally at IBM for some time
in addition to testing a few XIVE upstream patches; and I'll be closely looking
at XIVE going forward.
Signed-off-by: Gautam Menghani <gau...@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <hars...@linux.ibm.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250724100623.3071131-6-hars...@linux.ibm.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: cf8f0f006d380d50ef10ab77a4673e83eb19006c
https://github.com/qemu/qemu/commit/cf8f0f006d380d50ef10ab77a4673e83eb19006c
Author: Cédric Le Goater <c...@redhat.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove Frédéric as reviewer
Frédéric has moved to other tasks within IBM and no longer does QEMU
development.
Cc: Frédéric Barrat <fbar...@linux.ibm.com>
Acked-by: Frédéric Barrat <fbar...@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Link: https://lore.kernel.org/qemu-devel/20250724075916.1593420-1-...@redhat.com
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 0fb961e392e2055adc5429236989b01bb763f12c
https://github.com/qemu/qemu/commit/0fb961e392e2055adc5429236989b01bb763f12c
Author: Daniel Henrique Barboza <danielhb...@gmail.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: remove myself as ppc maintainer/reviewer
It has been awhile since I actively did anything for qemu-ppc aside from
reading the qemu-ppc inbox a couple of times each month. It's not enough
to justify a reviewer role, let alone being a maintainer.
Given that we're doing qemu-ppc maintainership changes across the board
I'll take the opportunity and remove myself from the premises too. Feel
free to reach out with questions about code I did in the past, but at
this moment I'm no longer able to keep up with qemu-ppc activities.
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Link:
https://lore.kernel.org/qemu-devel/20250724123416.3115941-1-danielhb...@gmail.com
[ clg: Adjusted context ]
Signed-off-by: Cédric Le Goater <c...@redhat.com>
Commit: 012842c075520dbe1bd96a2fdcf4e218874ba443
https://github.com/qemu/qemu/commit/012842c075520dbe1bd96a2fdcf4e218874ba443
Author: Daniel P. Berrangé <berra...@redhat.com>
Date: 2025-07-24 (Thu, 24 Jul 2025)
Changed paths:
M scripts/tracetool/backend/log.py
M util/log.c
Log Message:
-----------
log: make '-msg timestamp=on' apply to all qemu_log usage
Currently the tracing 'log' back emits special code to add timestamps
to trace points sent via qemu_log(). This current impl is a bad design
for a number of reasons.
* It changes the QEMU headers, such that 'error-report.h' content
is visible to all files using tracing, but only when the 'log'
backend is enabled. This has led to build failure bugs as devs
rarely test without the (default) 'log' backend enabled, and
CI can't cover every scenario for every trace backend.
* It bloats the trace points definitions which are inlined into
every probe location due to repeated inlining of timestamp
formatting code, adding MBs of overhead to QEMU.
* The tracing subsystem should not be treated any differently
from other users of qemu_log. They all would benefit from
having timestamps present.
* The timestamp emitted with the tracepoints is in a needlessly
different format to that used by error_report() in response
to '-msg timestamp=on'.
This fixes all these issues simply by moving timestamp formatting
into qemu_log, using the same approach as for error_report.
The code before:
static inline void _nocheck__trace_qcrypto_tls_creds_get_path(void * creds,
const char * filename, const char * path)
{
if (trace_event_get_state(TRACE_QCRYPTO_TLS_CREDS_GET_PATH) &&
qemu_loglevel_mask(LOG_TRACE)) {
if (message_with_timestamp) {
struct timeval _now;
gettimeofday(&_now, NULL);
qemu_log("%d@%zu.%06zu:qcrypto_tls_creds_get_path " "TLS creds
path creds=%p filename=%s path=%s" "\n",
qemu_get_thread_id(),
(size_t)_now.tv_sec, (size_t)_now.tv_usec
, creds, filename, path);
} else {
qemu_log("qcrypto_tls_creds_get_path " "TLS creds path creds=%p
filename=%s path=%s" "\n", creds, filename, path);
}
}
}
and after:
static inline void _nocheck__trace_qcrypto_tls_creds_get_path(void * creds,
const char * filename, const char * path)
{
if (trace_event_get_state(TRACE_QCRYPTO_TLS_CREDS_GET_PATH) &&
qemu_loglevel_mask(LOG_TRACE)) {
qemu_log("qcrypto_tls_creds_get_path " "TLS creds path creds=%p
filename=%s path=%s" "\n", creds, filename, path);
}
}
The log and error messages before:
$ qemu-system-x86_64 -trace qcrypto* -object
tls-creds-x509,id=tls0,dir=$HOME/tls -msg timestamp=on
2986097@1753122905.917608:qcrypto_tls_creds_x509_load TLS creds x509 load
creds=0x55d925bd9490 dir=/var/home/berrange/tls
2986097@1753122905.917621:qcrypto_tls_creds_get_path TLS creds path
creds=0x55d925bd9490 filename=ca-cert.pem path=<none>
2025-07-21T18:35:05.917626Z qemu-system-x86_64: Unable to access credentials
/var/home/berrange/tls/ca-cert.pem: No such file or directory
and after:
$ qemu-system-x86_64 -trace qcrypto* -object
tls-creds-x509,id=tls0,dir=$HOME/tls -msg timestamp=on
2025-07-21T18:43:28.089797Z qcrypto_tls_creds_x509_load TLS creds x509 load
creds=0x55bf5bf12380 dir=/var/home/berrange/tls
2025-07-21T18:43:28.089815Z qcrypto_tls_creds_get_path TLS creds path
creds=0x55bf5bf12380 filename=ca-cert.pem path=<none>
2025-07-21T18:43:28.089819Z qemu-system-x86_64: Unable to access credentials
/var/home/berrange/tls/ca-cert.pem: No such file or directory
The binary size before:
$ ls -alh qemu-system-x86_64
-rwxr-xr-x. 1 berrange berrange 87M Jul 21 19:39 qemu-system-x86_64
$ strip qemu-system-x86_64
$ ls -alh qemu-system-x86_64
-rwxr-xr-x. 1 berrange berrange 30M Jul 21 19:39 qemu-system-x86_64
and after:
$ ls -alh qemu-system-x86_64
-rwxr-xr-x. 1 berrange berrange 85M Jul 21 19:41 qemu-system-x86_64
$ strip qemu-system-x86_64
$ ls -alh qemu-system-x86_64
-rwxr-xr-x. 1 berrange berrange 29M Jul 21 19:41 qemu-system-x86_64
Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Markus Armbruster <arm...@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsement...@yandex-team.ru>
Message-id: 20250721185452.3016488-1-berra...@redhat.com
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 0e171b427b1d2f68d76a2b7cae987432c10ca8aa
https://github.com/qemu/qemu/commit/0e171b427b1d2f68d76a2b7cae987432c10ca8aa
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M target/arm/tcg/helper-sme.h
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sme.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Expand the descriptor for SME/SVE memory ops to i64
We have run out of room attempting to pack both the gvec
descriptor and the mte descriptor into 32 bits.
Here, change nothing except the parameter type, which
affects all declarations, the function typedefs, and the
type used with tcg expansion.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250723165458.3509150-2-peter.mayd...@linaro.org
Commit: aba39946baaf5ca73aae0b79e2cd0790ddafe291
https://github.com/qemu/qemu/commit/aba39946baaf5ca73aae0b79e2cd0790ddafe291
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M target/arm/internals.h
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Pack mtedesc into upper 32 bits of descriptor
Instead of trying to pack mtedesc into the upper 17 bits of a 32-bit
gvec descriptor, pass the gvec descriptor in the lower 32 bits and
the mte descriptor in the upper 32 bits of a 64-bit operand.
This fixes two bugs:
(1) in gen_sve_ldr() and gen_sve_str() call gen_mte_checkN() with a
length value which is the SVE vector length and can be up to 256
bytes. We don't assert there that it fits in the descriptor, so
we would just fail to do the MTE checks on the right length of memory
if the VL is more than 32 bytes
(2) the new-in-SVE2p1 insns LD3Q, LD4Q, ST3Q, ST4Q also involve
transfers of more than 32 bytes of memory. In this case we would
assert at translate time.
(Note for potential backporting: this commit depends on the previous
"target/arm: Expand the descriptor for SME/SVE memory ops to i64".)
Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250723165458.3509150-3-peter.mayd...@linaro.org
[PMM: expand commit message to clarify that we are fixing bugs here]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: b79f944e09657f63b6dd6e78ac7966fdc7a3e6d1
https://github.com/qemu/qemu/commit/b79f944e09657f63b6dd6e78ac7966fdc7a3e6d1
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M scripts/decodetree.py
M tests/decode/meson.build
A tests/decode/succ_infer1.decode
Log Message:
-----------
decodetree: Infer argument set before inferring format
Failure to confirm an argument set first may result in
the selection of a format which leaves extra arguments
to be filled in by the pattern.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Tested-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250723165458.3509150-4-peter.mayd...@linaro.org
Message-id: 20250722183343.273533-1-richard.hender...@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Tested-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 1c6aae5efbd28ac35003dea341364cd63a4515a1
https://github.com/qemu/qemu/commit/1c6aae5efbd28ac35003dea341364cd63a4515a1
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M target/arm/tcg/sve.decode
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: LD1Q, ST1Q are vector + scalar, not scalar + vector
Unlike the "LD1D (scalar + vector)" etc instructions, LD1Q is
vector + scalar. This means that:
* the vector and the scalar register are in opposite fields
in the encoding
* 31 in the scalar register field is XZR, not XSP
The same applies for ST1Q.
This means we can't reuse the trans_LD1_zprz() and trans_ST1_zprz()
functions for LD1Q and ST1Q. Split them out to use their own
trans functions.
Note that the change made here to sve.decode requires the decodetree
bugfix "decodetree: Infer argument set before inferring format" to
avoid a spurious compile-time error about "dtype".
Fixes: d2aa9a804ee678f ("target/arm: Implement LD1Q, ST1Q for SVE2p1")
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250723165458.3509150-5-peter.mayd...@linaro.org
Commit: 4726be1c69606e34c3cc4c26e39e252a9856b3d3
https://github.com/qemu/qemu/commit/4726be1c69606e34c3cc4c26e39e252a9856b3d3
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M target/arm/tcg/sve_helper.c
Log Message:
-----------
target/arm: Pass correct esize to sve_st1_z() for LD1Q, ST1Q
Our implementation of the helper functions for the LD1Q and ST1Q
insns reused the existing DO_LD1_ZPZ_D and DO_ST1_ZPZ_D macros. This
passes the wrong esize (8, not 16) to sve_ldl_z().
Create new macros DO_LD1_ZPZ_Q and DO_ST1_ZPZ_Q which pass the
correct esize, and use them for the LD1Q and ST1Q helpers.
Fixes: d2aa9a804ee ("target/arm: Implement LD1Q, ST1Q for SVE2p1")
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250723165458.3509150-6-peter.mayd...@linaro.org
Commit: 7428c46c06b4365ee5131dcdcc3da218c5e99ddd
https://github.com/qemu/qemu/commit/7428c46c06b4365ee5131dcdcc3da218c5e99ddd
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M target/arm/tcg/sve_helper.c
Log Message:
-----------
target/arm: Fix LD1W, LD1D to 128-bit elements
In our implementation of the SVE2p1 contiguous load to 128-bit
element insns such as LD1D (scalar plus scalar, single register), we
got the order of the arguments to the DO_LD1_2() macro wrong. Here
the first argument is the element size and the second is the memory
size, and the element size is always the same size or larger than
the memory size.
For the 128-bit versions, we want to load either 32-bit or 64-bit
values from memory and extend them to the 128-bit vector element, but
were trying to load 128 bit values and then stuff them into 32-bit or
64-bit vector elements. Correct the macro ordering.
Fixes: fc5f060bcb7b ("target/arm: Implement {LD1, ST1}{W, D} (128-bit element)
for SVE2p1")
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250723165458.3509150-7-peter.mayd...@linaro.org
Commit: bd52d8bc9e01dcf68731dcdd9d2b8ebcb9fc5692
https://github.com/qemu/qemu/commit/bd52d8bc9e01dcf68731dcdd9d2b8ebcb9fc5692
Author: JianChunfu <jansef.j...@hj-micro.com>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M hw/arm/smmu-common.c
Log Message:
-----------
hw/arm/smmu-common: Avoid using inlined functions with external linkage
Similarly to commit 9de9fa5c ("hw/arm/smmu-common: Avoid using
inlined functions with external linkage"):
None of our code base require / use inlined functions with external
linkage. Some places use internal inlining in the hot path. These
two functions are certainly not in any hot path and don't justify
any inlining, so these are likely oversights rather than intentional.
Fixes: b8fa4c23 (hw/arm/smmu: Support nesting in the rest of commands)
Signed-off-by: JianChunfu <jansef.j...@hj-micro.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: a7aa2af13e287e11cb2d73972353bfec161803a4
https://github.com/qemu/qemu/commit/a7aa2af13e287e11cb2d73972353bfec161803a4
Author: Mohamed Mediouni <moha...@unpredictable.fr>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
target/arm: hvf: stubbing reads to LORC_EL1
Linux zeroes LORC_EL1 on boot at EL2, without further interaction with FEAT_LOR
afterwards.
Stub out LORC_EL1 accesses as FEAT_LOR is a mandatory extension on Armv8.1+.
Signed-off-by: Mohamed Mediouni <moha...@unpredictable.fr>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 919c486c406a34823c6cef5438f1a13e2c79a7d5
https://github.com/qemu/qemu/commit/919c486c406a34823c6cef5438f1a13e2c79a7d5
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M crypto/tlssession.c
M crypto/trace-events
M include/crypto/tlssession.h
M include/io/channel.h
M io/channel-tls.c
M meson.build
M meson_options.txt
M migration/migration-hmp-cmds.c
M migration/tls.c
M scripts/meson-buildoptions.sh
Log Message:
-----------
Merge tag 'migration-20250722-pull-request' of
https://gitlab.com/farosas/qemu into staging
Migration pull request
- Fixes to postcopy blocktime latency display code
- Fix to QMP error message (not)shown when postcopy fails
- Workaround to a GNUTLS bug that crashes QEMU
# -----BEGIN PGP SIGNATURE-----
#
# iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmiAG1wQHGZhcm9zYXNA
# c3VzZS5kZQAKCRDHmNx0G+wxnR0xEACZMIqnVIFUu57V5gJ8v/4IJv70n6jrjtzJ
# 5/TzdAAY9bKJE5y84axovZy4iHijbZnGz+kVKr5Wai9KKb41tW0liWAe5RART2TE
# VuRBgxXODCmg3US6w0niy9cR3NH7WXbEQ5gyexC7D3/1R1ahpqOragZQxzvtA+3e
# aKe2pqRyQODHU9D1tnKexeFNJM6dGBVd9FVsYAHDfhx0Bk1vcpVXVrAJcfaSY2Y5
# +4/g7CXOJCUFBrFbVxYFU9muU8JrMvWv8lU4nG2ztDhmSH7Uy/DVCfEUa9/jEjDa
# 1BwZbOIIFMJy0P/G3toK6Z9lJEVfiUXaboNtqgSK5ZM8ZL1L1yHKQi631Qny/Wuf
# pzJWR1nOSL2f/bsueWj2OmZKl3FpXcaDWisZuDeS3wXWrtPRuJEXi6f//6JcYd2i
# Zm0kVRNf3CbXGnJxwDrsbh0hr5sN+bonaI+N4hHGxDCqUHhND4p0JMaPMte+PF4u
# pOooaRKq2a6KRZFyDPjyBgESXfDJ0Tdw5IeOKbFPskOEIpBVxyc3mpwu8Kz45qoV
# 8b2GYCKBjWLpqfTPwUcJd5MNVDO1ZUyqOPuarHNADth6pJglnWyFI/TIBoARzAKB
# EzS4dQ+DKM/Jz5cM++0dMPL75/1i2q2x7BBhCBBm9yeZDqDIKeT07yl8JGL/OCq9
# 7gNGfyze5w==
# =DGn2
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 22 Jul 2025 19:14:36 EDT
# gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D
# gpg: issuer "faro...@suse.de"
# gpg: Good signature from "Fabiano Rosas <faro...@suse.de>" [unknown]
# gpg: aka "Fabiano Almeida Rosas <fabiano.ro...@suse.com>"
[unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D
* tag 'migration-20250722-pull-request' of https://gitlab.com/farosas/qemu:
crypto: add tracing & warning about GNUTLS countermeasures
migration: activate TLS thread safety workaround
io: add support for activating TLS thread safety workaround
crypto: implement workaround for GNUTLS thread safety problems
migration: show error message when postcopy fails
migration: HMP: Fix postcopy latency distribution label
migration: HMP: Fix possible out-of-bounds access
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: 92ac518223c73484c89236ae26afb56f00a4bc15
https://github.com/qemu/qemu/commit/92ac518223c73484c89236ae26afb56f00a4bc15
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
Merge tag 'pull-ppc-20250724' of https://github.com/legoater/qemu into staging
ppc queue:
* Update maintainers
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmiCMyUACgkQUaNDx8/7
# 7KEfqhAAvyOcR8r2bFfbLcOXWnHLgh+zjO5WlJpofMdktKK+AkzDK3oRZJHi8KtH
# Xu+F68F2Qt2AFZC7K4ddI/6hT+ki78yTUCSCVr73YTa+R94iHlOIWn/8CaQJjNjU
# FZPRIGQuGg5kNw0IJQj4qqo0qk77v2mkLhi0nuQ69mjuiCnydr2UWDrkaNCP9qtx
# WwhcneTK5UIwelowWVBpV3E6aH8jo1psj9PyIn11nBaLmriFtcu4Uz1X3WG6ydxW
# AKDDD5hBom9SwRMlKPNJjRqZ5ydDdMkgmRSrCCMWSv0m5wdvzbA3pqTPkl5Cc/o5
# IH8m/YAlF5mGAHbIBryys0OnCqMd7AiYjCdVrP14qc/Ccrar61v8rBMQo24qUDcB
# NF6+4MlbgYMqns79VJftu7s/DI4p4R9cJmkInKNFGlpVIaDHYhENz3KTTszlntp2
# aV8fILK9oFpoQllgtFuSx89Ay2DG8kqU/D8OKR6haHXwdaFaKGMSyB+hoZ9+Iv3R
# LNne5hGKr6p0j6k0kyIAXi11KS1i0mOg+Eha+v0fLqRqsIPt1Nt7ysRbxV+Yf6zc
# zsxK4CR98FERKSlBbNtMU2sb3AJRamdX35+cGG8/lWq+RK5RbweCMBgHktLFW5/8
# BXPF2Ju0fZk5kvhxoJ0qg9SRU6t4C6kApSa/buKj22Ix/41KpWI=
# =bWN6
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 24 Jul 2025 09:20:37 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <c...@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <c...@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-ppc-20250724' of https://github.com/legoater/qemu:
MAINTAINERS: remove myself as ppc maintainer/reviewer
MAINTAINERS: Remove Frédéric as reviewer
MAINTAINERS: Add myself as a reviewer for XIVE
MAINTAINERS: Add myself as a reviewer of PowerNV emulation
MAINTAINERS: Add myself as reviewer for PowerPC TCG CPUs
MAINTAINERS: Adding myself as reviewer for PPC KVM cpus.
MAINTAINERS: Adding myself as a co-maintainer for ppc/spapr
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: d3c9de45b2a54f6021c9a48a216263aa76847a29
https://github.com/qemu/qemu/commit/d3c9de45b2a54f6021c9a48a216263aa76847a29
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M scripts/tracetool/backend/log.py
M util/log.c
Log Message:
-----------
Merge tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu into
staging
Pull request
This commit is still worth having in QEMU 10.1 for the all-round improvements
made (consistent timestamping, binary size reduction, header pollution cleanup)
even if it's debatable whether this is a bug fix.
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmiCR0UACgkQnKSrs4Gr
# c8g4AggAyBo1oNAVSMQIC6JRRcLrVBCWGPWVyU1/3AaayKLy8egs1pImmT09DcdQ
# D2CHCjEp0xbTzFlN3YiBymAOeq/a73G7NPzWdCi/PY1qBmB4td8Eli/tBoQUYvmE
# k0a0r6DrOo6vGddCqv6fAKnvamcs/IB2ogzpqLVLCC4oAP6TVG0LeHsaqTAtO8bv
# yZb+1YQxFZtum2yp9I4+mk8c1R04cCdDL17TRCrv4hTkpGRYfaDs8LRy5yJ4Nw6V
# AID3fkLTaxOcQpb2EItfcoGalF/JcCdZoOlJ/91clJ1MWFAnV9Y9gBZtlSF4dx+k
# c2rTlcBw9j402imuotLOP7Cl8mLNeg==
# =lXaI
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 24 Jul 2025 10:46:29 EDT
# gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefa...@redhat.com>" [ultimate]
# gpg: aka "Stefan Hajnoczi <stefa...@gmail.com>" [ultimate]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu:
log: make '-msg timestamp=on' apply to all qemu_log usage
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Commit: c017386f28c03a03b8f14444f8671d3d8f7180fe
https://github.com/qemu/qemu/commit/c017386f28c03a03b8f14444f8671d3d8f7180fe
Author: Stefan Hajnoczi <stefa...@redhat.com>
Date: 2025-07-25 (Fri, 25 Jul 2025)
Changed paths:
M hw/arm/smmu-common.c
M scripts/decodetree.py
M target/arm/hvf/hvf.c
M target/arm/internals.h
M target/arm/tcg/helper-sme.h
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve.decode
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sme.c
M target/arm/tcg/translate-sve.c
M tests/decode/meson.build
A tests/decode/succ_infer1.decode
Log Message:
-----------
Merge tag 'pull-target-arm-20250725' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* Fix various bugs in SMEp/SVE2p1 load/store handling
* hw/arm/smmu-common: Avoid using inlined functions with external linkage
* target/arm: hvf: stubbing reads to LORC_EL1
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmiDbRIZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3sifD/9uJRrZ0o/PQfRVIYl7vIFE
# MjUl6sncznX1zk/B7xNuiJ5KDoziQm/L3KPcb0JPoqhO3nLeqvLIvfmB6W85cV/w
# OD0PFnL1inuxWf1rKdeheGtyZ0R9Ep3BFzB6NJMDxVJC9aP0eqfGxVo2BCdydv/9
# m3v7gCkp/lj5LcpJ+8w0bEzuqT3xzcbibFdFi4eKBiG5P3OvwGv3Kt+FhOISXcBe
# cU+RpXEkd0MBusOWq1OXLgWS+IPx/e67l1ehxAfVztxFUI3gwej7JgLCnIIoxRsw
# EWGQYhSSg6QE8h2TknxDKj9jmMcqnjluRjaefPQS8BxbYc6s6dsSBCxbeZJ/zNyJ
# gD/ymK/nayTBfoP+S7eWGDaldNv/AnKSWa28GEpi3dmDDfKlwRB77arGU2zXirjo
# dG/0tcg+G7mmkSH5BbPJfFJgjUqEu+D2wq1wm53SSb/AqK8BL4ODF3LE6r6+65ft
# fg5nalDbn2uTa90M7BHfaGEJj0hdP8xM9wmRHCoJ1LEDieSsjInZWwIbSwQBL6Rc
# Rr2PmnTWdMKuyr9WgOBzFfCAzmFDwJmqlIqRIRHPKo21xAiGYh8oTp31MhgZWdaj
# yK+V9t5Mznp1PVfL5xYwe/xG1CmKE6FKOwuvF3RkTF5lBU88x9fIcPOjaWZymW4n
# iqkUZmp+nS9K3V4WWjGxnQ==
# =quq9
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 25 Jul 2025 07:40:02 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.mayd...@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmayd...@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <pe...@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250725' of https://gitlab.com/pm215/qemu:
target/arm: hvf: stubbing reads to LORC_EL1
hw/arm/smmu-common: Avoid using inlined functions with external linkage
target/arm: Fix LD1W, LD1D to 128-bit elements
target/arm: Pass correct esize to sve_st1_z() for LD1Q, ST1Q
target/arm: LD1Q, ST1Q are vector + scalar, not scalar + vector
decodetree: Infer argument set before inferring format
target/arm: Pack mtedesc into upper 32 bits of descriptor
target/arm: Expand the descriptor for SME/SVE memory ops to i64
Signed-off-by: Stefan Hajnoczi <stefa...@redhat.com>
Compare: https://github.com/qemu/qemu/compare/9e601684dc24...c017386f28c0
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