Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 27ea28a0b369b4b14a485a5d6f045e0dc1db4e38
https://github.com/qemu/qemu/commit/27ea28a0b369b4b14a485a5d6f045e0dc1db4e38
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Fix tgen_deposit
When converting from tcg_out_deposit, the arguments were not
shuffled properly.
Cc: qemu-sta...@nongnu.org
Fixes: cf4905c03135f1181e8 ("tcg: Convert deposit to TCGOutOpDeposit")
Reported-by: Michael Tokarev <m...@tls.msk.ru>
Tested-by: Michael Tokarev <m...@tls.msk.ru>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: b8eb3dd49583729edceb18628e626eac15a15de4
https://github.com/qemu/qemu/commit/b8eb3dd49583729edceb18628e626eac15a15de4
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M host/include/i386/host/cpuinfo.h
M include/qemu/cpuid.h
M util/cpuinfo-i386.c
Log Message:
-----------
cpuinfo/i386: Detect GFNI as an AVX extension
We won't use the SSE GFNI instructions, so delay
detection until we know AVX is present.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 26c41cc4a3d998caa700407a27e18755a6e1895c
https://github.com/qemu/qemu/commit/26c41cc4a3d998caa700407a27e18755a6e1895c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Expand sari of bits-1 as pcmpgt
Expand arithmetic right shift of bits-1 as a comparison vs 0.
Suggested-by: Paolo Bonzini <pbonz...@redhat.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: ba8a86d67aca43a854c78380c917845059c83d4c
https://github.com/qemu/qemu/commit/ba8a86d67aca43a854c78380c917845059c83d4c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Use canonical operand ordering in expand_vec_sari
The optimizer prefers to have constants as the second operand,
so expand LT x,0 instead of GT 0,x. This will not affect the
generated code at all.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 6c76a1f687cd509d26dae44ea39bf396b251fe0e
https://github.com/qemu/qemu/commit/6c76a1f687cd509d26dae44ea39bf396b251fe0e
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M tcg/i386/tcg-target-opc.h.inc
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Add INDEX_op_x86_vgf2p8affineqb_vec
Add a backend-specific opcode for expanding the
GFNI vgf2p8affineqb instruction, which we can use
for expanding 8-bit immediate shifts and rotates.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: cb2540979264c8d3984e26c5dd90a840e47ec5dd
https://github.com/qemu/qemu/commit/cb2540979264c8d3984e26c5dd90a840e47ec5dd
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Use vgf2p8affineqb for MO_8 vector shifts
A constant matrix can describe the movement of the 8 bits,
so these shifts can be performed with one instruction.
Logic courtesy of Andi Kleen <a...@linux.intel.com>:
https://gcc.gnu.org/pipermail/gcc-patches/2025-August/691624.html
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Commit: 6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8
https://github.com/qemu/qemu/commit/6a9fa5ef3230a7d51e0d953a59ee9ef10af705b8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-05 (Fri, 05 Sep 2025)
Changed paths:
M host/include/i386/host/cpuinfo.h
M include/qemu/cpuid.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-opc.h.inc
M tcg/i386/tcg-target.c.inc
M util/cpuinfo-i386.c
Log Message:
-----------
Merge tag 'pull-tcg-20250905' of https://gitlab.com/rth7680/qemu into staging
tcg/arm: Fix tgen_deposit
tcg/i386: Use vgf2p8affineqb for MO_8 vector shifts
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[ultimate]
* tag 'pull-tcg-20250905' of https://gitlab.com/rth7680/qemu:
tcg/i386: Use vgf2p8affineqb for MO_8 vector shifts
tcg/i386: Add INDEX_op_x86_vgf2p8affineqb_vec
tcg/i386: Use canonical operand ordering in expand_vec_sari
tcg/i386: Expand sari of bits-1 as pcmpgt
cpuinfo/i386: Detect GFNI as an AVX extension
tcg/arm: Fix tgen_deposit
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/baa79455fa92...6a9fa5ef3230
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