Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 424dc390ec68263b5fc82b88f0f81bc3f374ad44
https://github.com/qemu/qemu/commit/424dc390ec68263b5fc82b88f0f81bc3f374ad44
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M scripts/userfaultfd-wrlat.py
M tests/guest-debug/test_gdbstub.py
M tests/tcg/aarch64/gdbstub/test-mte.py
M tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
M tests/tcg/aarch64/gdbstub/test-sve.py
M tests/tcg/multiarch/gdbstub/interrupt.py
M tests/tcg/multiarch/gdbstub/memory.py
M tests/tcg/multiarch/gdbstub/sha1.py
M tests/tcg/multiarch/gdbstub/test-proc-mappings.py
M tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py
M tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py
M tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py
M tests/tcg/s390x/gdbstub/test-signals-s390x.py
M tests/tcg/s390x/gdbstub/test-svc.py
Log Message:
-----------
tests, scripts: Don't import print_function from __future__
Some of our Python scripts still include the line
from __future__ import print_function
which is intended to allow a Python 2 to handle the Python 3 print()
syntax. This particular part of the future arrived many years ago,
and our minimum Python version is 3.9, so we don't need to keep
this line around.
NB: the scripts in tests/tcg/*/gdbstub/ are run with whatever Python
gdb was built against, but we can safely assume that that was a
Python 3 because our supported distros are all on Python 3. In any
case these are only run as part of "make check-tcg", not by
end-users.
Commit created with:
sed -i -e '/import print_function/d' $(git grep -l 'from __future__')
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: John Snow <js...@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250819102409.2117969-1-peter.mayd...@linaro.org
Commit: 71eba045758289e12133c4977f81c9132325c648
https://github.com/qemu/qemu/commit/71eba045758289e12133c4977f81c9132325c648
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M linux-user/aarch64/cpu_loop.c
Log Message:
-----------
linux-user/aarch64: Split out signal_for_exception
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 5fe3151c5e18eb15347c2ea572b551c7aed67a9f
https://github.com/qemu/qemu/commit/5fe3151c5e18eb15347c2ea572b551c7aed67a9f
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M linux-user/aarch64/cpu_loop.c
Log Message:
-----------
linux-user/aarch64: Check syndrome for EXCP_UDEF
Note that we have been passing the incorrect code for most
exception codes: uncategorized (do_el0_undef),
systemregistertrap (do_el0_sys), smetrap (do_sme_acc),
btitrap (do_el0_bti) and illegalstate (bad_el0_sync).
Only pacfail uses ILL_ILLOPN (do_el0_fpac).
Note that EC_MOP (do_el0_mops) ought not signal at all.
For now, preserve existing behavior signalling ILL_ILLOPN.
List all other exception codes and document why they do
not apply to user-only.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: e1b31ba94d143c5026b199c5df7523fa4d9fa4cf
https://github.com/qemu/qemu/commit/e1b31ba94d143c5026b199c5df7523fa4d9fa4cf
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M linux-user/aarch64/cpu_loop.c
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Generate ESR signal records
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 76fea609082d9673449a1f6aca9a28af6f20f8cf
https://github.com/qemu/qemu/commit/76fea609082d9673449a1f6aca9a28af6f20f8cf
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/m_helper.c
Log Message:
-----------
target/arm: Add prot_check parameter to pmsav8_mpu_lookup
Separate the access_type from the protection check.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 015cefc0ed65ef054616171128f5962f1cccb2d1
https://github.com/qemu/qemu/commit/015cefc0ed65ef054616171128f5962f1cccb2d1
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Add in_prot_check to S1Translate
Separate the access_type from the protection check.
Save the trouble of modifying all helper functions
by passing the new data in the control structure.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 7e130764415e0a15faf09c5c26043b016ba798fc
https://github.com/qemu/qemu/commit/7e130764415e0a15faf09c5c26043b016ba798fc
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Skip permission check from arm_cpu_get_phys_page_attrs_debug
Do not require read permission when translating addresses
for debugging purposes.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 8818b2d91363dc6b478edc4e6325e958e7348648
https://github.com/qemu/qemu/commit/8818b2d91363dc6b478edc4e6325e958e7348648
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/cpregs-at.c
Log Message:
-----------
target/arm: Introduce get_phys_addr_for_at
Rename get_phys_addr_with_space_nogpc for its only
caller, do_ats_write. Drop the MemOp memop argument
as it doesn't make sense in the new context. Replace
the access_type parameter with prot_check.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: efebeec13d076100191a4a5a98f047c46c0d592c
https://github.com/qemu/qemu/commit/efebeec13d076100191a4a5a98f047c46c0d592c
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Skip AF and DB updates for AccessType_AT
We are required to skip DB update for AT instructions, and
we are allowed to skip AF updates. Choose to skip both.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 95901c43a8845a86a6895a8bd5d141f3ce36b3d1
https://github.com/qemu/qemu/commit/95901c43a8845a86a6895a8bd5d141f3ce36b3d1
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/tcg/cpregs-at.c
Log Message:
-----------
target/arm: Add prot_check parameter to do_ats_write
Separate protection check from access type, in preparation
for skipping the protection check altogether.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: b41cfb6d17ee29f3c5474d8a8f79260535a11335
https://github.com/qemu/qemu/commit/b41cfb6d17ee29f3c5474d8a8f79260535a11335
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/cpregs.h
Log Message:
-----------
target/arm: Fill in HFG[RWI]TR_EL2 bits for Arm v9.5
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 171a302a041ed5532d997d40bb50f39b2b9435a3
https://github.com/qemu/qemu/commit/171a302a041ed5532d997d40bb50f39b2b9435a3
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Remove outdated comment for ZCR_EL12
The comment about not being included in the summary table
has been out of date for quite a while.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-12-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 2b5daf79c32656264a23104c0693aa89c528cff8
https://github.com/qemu/qemu/commit/2b5daf79c32656264a23104c0693aa89c528cff8
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpregs.h
M target/arm/cpu-features.h
M target/arm/tcg/cpregs-at.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Implement FEAT_ATS1A
Implement FEAT_ATS1A and enable for -cpu max.
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250830054128.448363-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: cc2c5027dc755b0b7e2a6531b089e5a239d3e0ce
https://github.com/qemu/qemu/commit/cc2c5027dc755b0b7e2a6531b089e5a239d3e0ce
Author: Osama Abdelkader <osama.abdelka...@gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/arm/raspi4b.c
Log Message:
-----------
hw/arm/raspi4b: remove redundant check in raspi_add_memory_node
The if (acells == 0 || scells == 0) check is redundant in
raspi_add_memory_node, since it is already checked in the call
chain, arm_load_dtb. Also the return value of the function is
not checked/used so it's removed.
Signed-off-by: Osama Abdelkader <osama.abdelka...@gmail.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Tested-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20250902200818.43305-1-osama.abdelka...@gmail.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 5b3764d9e30627853c5b9171925c51232e56a293
https://github.com/qemu/qemu/commit/5b3764d9e30627853c5b9171925c51232e56a293
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M target/arm/tcg/cpu32.c
Log Message:
-----------
target/arm: Remove deprecated pxa CPU family
In 10.0 we deprecated the pxa CPU family (pxa250, pxa255, pxa260
pxa261, pxa262, pxa270-a0, pxa270-a1, pxa270, pxa270-b0, pxa270-b1,
pxa270-c0, pxa270-c5). Now we have released 10.1 we can remove them.
This commit removes only the top level CPU definitions and updates
the documentation. Removing the CPUs means that there is now a lot
of dead iwMMXt code, which we will delete in subsequent commits.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250828140422.3271703-2-peter.mayd...@linaro.org
Commit: cdafe5bd90eef82bec798029ad5669bf2ee15023
https://github.com/qemu/qemu/commit/cdafe5bd90eef82bec798029ad5669bf2ee15023
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/hflags.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Remove XScale and iWMMXt translate.c code
Remove all the translator code that is accessible only via
ARM_FEATURE_XSCALE or ARM_FEATURE_IWMMXT. This includes the
xscale-only cp15_cpar TB flags and cpu_{V0,V1,M0} TCG temps.
The no-longer-used helper functions will be removed in a separate
commit.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250828140422.3271703-3-peter.mayd...@linaro.org
Commit: 144aac11d6e0600f6dc644ad0d7e47110d8484f1
https://github.com/qemu/qemu/commit/144aac11d6e0600f6dc644ad0d7e47110d8484f1
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/tcg/helper.h
R target/arm/tcg/iwmmxt_helper.c
M target/arm/tcg/meson.build
Log Message:
-----------
target/arm: Remove iwmmxt helper functions
Remove the iwmmxt helper functions which are no longer called now
that we have removed the associated translate.c handling.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250828140422.3271703-4-peter.mayd...@linaro.org
Commit: 4f0fa4bfd98f3ccdcdeed6f43a2340084a6e0a92
https://github.com/qemu/qemu/commit/4f0fa4bfd98f3ccdcdeed6f43a2340084a6e0a92
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/ptw.c
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Drop ARM_FEATURE_XSCALE handling
We have now removed all the CPU types which had the Intel XScale
extensions indicated via ARM_FEATURE_XSCALE, so this feature bit
is never set. Remove all the code that can only be reached when
using this flag.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250828140422.3271703-5-peter.mayd...@linaro.org
Commit: effe47ff4840860811e2e1cccfd60cb1cea8e459
https://github.com/qemu/qemu/commit/effe47ff4840860811e2e1cccfd60cb1cea8e459
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M bsd-user/arm/target_arch_elf.h
M linux-user/arm/elfload.c
M linux-user/arm/signal.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/machine.c
Log Message:
-----------
target/arm: Drop ARM_FEATURE_IWMMXT handling
We have now removed all the CPU types which had the Intel XScale
extensions indicated via ARM_FEATURE_IWMMXT, so this feature bit
is never set. Remove all the code that can only be reached when
using this flag.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250828140422.3271703-6-peter.mayd...@linaro.org
Commit: 116c2c21d521eb31fffb44eb74d918975c9a5658
https://github.com/qemu/qemu/commit/116c2c21d521eb31fffb44eb74d918975c9a5658
Author: Peter Maydell <peter.mayd...@linaro.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/arm/boot.c
M include/system/system.h
M qemu-options.hx
M system/globals.c
M system/vl.c
Log Message:
-----------
system: drop the -old-param option
We deprecated the command line option -old-param for the 10.0
release, which allows us to drop it in 10.2. This option was used to
boot Arm targets with a very old boot protocol using the
'param_struct' ABI. We only ever needed this on a handful of board
types which have all now been removed from QEMU.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Manos Pitsidianakis <manos.pitsidiana...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Message-id: 20250828162700.3308812-1-peter.mayd...@linaro.org
Commit: 19f6dcfe6b8b2a3523362812fc696ab83050d316
https://github.com/qemu/qemu/commit/19f6dcfe6b8b2a3523362812fc696ab83050d316
Author: Cornelia Huck <coh...@redhat.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/kvm.c
Log Message:
-----------
arm/kvm: report registers we failed to set
If we fail migration because of a mismatch of some registers between
source and destination, the error message is not very informative:
qemu-system-aarch64: error while loading state for instance 0x0 ofdevice 'cpu'
qemu-system-aarch64: Failed to put registers after init: Invalid argument
At least try to give the user a hint which registers had a problem,
even if they cannot really do anything about it right now.
Sample output:
Could not set register op0:3 op1:0 crn:0 crm:0 op2:0 to c00fac31 (is 413fd0c1)
We could be even more helpful once we support writable ID registers,
at which point the user might actually be able to configure something
that is migratable.
Suggested-by: Eric Auger <eric.au...@redhat.com>
Reviewed-by: Sebastian Ott <seb...@redhat.com>
Signed-off-by: Cornelia Huck <coh...@redhat.com>
Message-id: 20250911154159.158046-1-coh...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 71cda981208ebcfa403d8e3451d1d5bdef0b0931
https://github.com/qemu/qemu/commit/71cda981208ebcfa403d8e3451d1d5bdef0b0931
Author: Vacha Bhavsar <vacha.bhav...@oss.qualcomm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M gdbstub/internals.h
Log Message:
-----------
target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging
This patch increases the value of the MAX_PACKET_LEGNTH to
131104 from 4096 to allow the GDBState.line_buf to be large enough
to accommodate the full contents of the SME ZA storage when the
vector length is maximal. This is in preparation for a related
patch that allows SME register visibility through remote GDB
debugging.
Signed-off-by: Vacha Bhavsar <vacha.bhav...@oss.qualcomm.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20250909161012.2561593-2-vacha.bhav...@oss.qualcomm.com
[PMM: fixed up comment formatting]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 030f0ba11767c7bd4148d9cd4f63e299d38139b3
https://github.com/qemu/qemu/commit/030f0ba11767c7bd4148d9cd4f63e299d38139b3
Author: Vacha Bhavsar <vacha.bhav...@oss.qualcomm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Added support for SME register exposure to GDB
The QEMU GDB stub does not expose the ZA storage SME register to GDB
via the remote serial protocol, which can be a useful functionality
to debug SME code. To provide this functionality for AArch64
targets, this patch registers the SME register set with the GDB stub.
To do so, this patch implements the aarch64_gdb_get_sme_reg() and
aarch64_gdb_set_sme_reg() functions to specify how to get and set the
SME registers, and the arm_gen_dynamic_smereg_feature() function to
generate the target description in XML format to indicate the target
architecture supports SME. Finally, this patch includes a
dyn_smereg_feature structure to hold this GDB XML description of the
SME registers for each CPU.
Note that according to the GDB documentation the ZA register is
defined as a vector of bytes; however the target description xml
retrieved when using gdb natively on a host with SME capabilities
represents the ZA register as a vector of vectors of bytes, so this
is a GDB documentation error. We follow GDB's own gdbstub
implementation and represent the ZA register as a vector of vectors
of bytes as is done by GDB here:
https://github.com/bminor/binutils-gdb/blob/5cce2b7006daa7073b98e3d1a3b176199d1381d7/gdb/features/aarch64-sme.c#L50
Signed-off-by: Vacha Bhavsar <vacha.bhav...@oss.qualcomm.com>
Message-id: 20250909161012.2561593-3-vacha.bhav...@oss.qualcomm.com
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
[PMM: fixed minor checkpatch nits]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 904b8aae52a7b23fa00285decba535bd1e8f8d50
https://github.com/qemu/qemu/commit/904b8aae52a7b23fa00285decba535bd1e8f8d50
Author: Vacha Bhavsar <vacha.bhav...@oss.qualcomm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M configure
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/gdbstub/test-sme.py
Log Message:
-----------
target/arm: Added test case for SME register exposure to GDB
This patch adds a test case to test SME register exposure to
a remote gdb debugging session. This test simply sets and
reads SME registers.
Signed-off-by: Vacha Bhavsar <vacha.bhav...@oss.qualcomm.com>
Message-id: 20250909161012.2561593-4-vacha.bhav...@oss.qualcomm.com
[PMM: fixed various python formatting nits]
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d9e6b8424fd2523a0361972d5dd841471879479c
https://github.com/qemu/qemu/commit/d9e6b8424fd2523a0361972d5dd841471879479c
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/arm/smmu-common.c
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/pci/pci_bridge.h
Log Message:
-----------
hw/arm/smmu-common: Check SMMU has PCIe Root Complex association
We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra
root complexes to be associated with SMMU.
Although this change does not affect functionality at present, it is
required when we add support for user-creatable SMMUv3 devices in
future patches.
Note: Added a specific check to identify pxb-pcie to avoid matching
pxb-cxl host bridges, which are also of type PCI_HOST_BRIDGE. This
restriction can be relaxed once support for CXL devices on arm/virt
is added and validated with SMMUv3.
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nathan Chen <nath...@nvidia.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Message-id: 20250829082543.7680-2-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 0e6a5bfb0eb17f57fb923b7905bd1435204bdd62
https://github.com/qemu/qemu/commit/0e6a5bfb0eb17f57fb923b7905bd1435204bdd62
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build
Introduce a new struct AcpiIortSMMUv3Dev to hold all the information
required for SMMUv3 IORT node and use that for populating the node.
The current machine wide SMMUv3 is named as legacy SMMUv3 as we will
soon add support for user-creatable SMMUv3 devices. These changes will
be useful to have common code paths when we add that support.
Tested-by: Nathan Chen <nath...@nvidia.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Message-id: 20250829082543.7680-3-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 01e9a18730e6f56f713ed074603a8b0f2982ed26
https://github.com/qemu/qemu/commit/01e9a18730e6f56f713ed074603a8b0f2982ed26
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices
With the soon to be introduced user-creatable SMMUv3 devices for
virt, it is possible to have multiple SMMUv3 devices associated
with different PCIe root complexes.
Update IORT nodes accordingly.
An example IORT Id mappings for a Qemu virt machine with two
PCIe Root Complexes each assocaited with a SMMUv3 will
be something like below,
-device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0
-device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1
...
+--------------------+ +--------------------+
| Root Complex 0 | | Root Complex 1 |
| | | |
| Requestor IDs | | Requestor IDs |
| 0x0000 - 0x00FF | | 0x0100 - 0x01FF |
+---------+----------+ +---------+----------+
| |
| |
| Stream ID Mapping |
v v
+--------------------+ +--------------------+
| SMMUv3 Node 0 | | SMMUv3 Node 1 |
| | | |
| Stream IDs 0x0000- | | Stream IDs 0x0100- |
| 0x00FF mapped from | | 0x01FF mapped from |
| RC0 Requestor IDs | | RC1 Requestor IDs |
+--------------------+ +--------------------+
| |
| |
+----------------+---------------+
|
|Device ID Mapping
v
+----------------------------+
| ITS Node 0 |
| |
| Device IDs: |
| 0x0000 - 0x00FF (from RC0) |
| 0x0100 - 0x01FF (from RC1) |
| 0x0200 - 0xFFFF (No SMMU) |
+----------------------------+
Tested-by: Nathan Chen <nath...@nvidia.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Message-id: 20250829082543.7680-4-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 7a276b7570266ec39611f9d91089741ec7e9295b
https://github.com/qemu/qemu/commit/7a276b7570266ec39611f9d91089741ec7e9295b
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Factor out common SMMUV3 dt bindings code
No functional changes intended. This will be useful when we
add support for user-creatable smmuv3 device.
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nathan Chen <nath...@nvidia.com>
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Message-id: 20250829082543.7680-5-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 466197fc7a25658f9187d538c26887f5738d1ac9
https://github.com/qemu/qemu/commit/466197fc7a25658f9187d538c26887f5738d1ac9
Author: Nicolin Chen <nicol...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Add an SMMU_IO_LEN macro
This is useful as the subsequent support for new SMMUv3 dev will also
use the same.
Signed-off-by: Nicolin Chen <nicol...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nathan Chen <nath...@nvidia.com>
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Message-id: 20250829082543.7680-6-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 951bc76fb669eab96cc60e38a50097ad4435163e
https://github.com/qemu/qemu/commit/951bc76fb669eab96cc60e38a50097ad4435163e
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/pci/pci.c
M include/hw/pci/pci.h
M include/hw/pci/pci_bus.h
Log Message:
-----------
hw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrieval
Currently, pci_setup_iommu() registers IOMMU ops for a given PCIBus.
However, when retrieving IOMMU ops for a device using
pci_device_get_iommu_bus_devfn(), the function checks the parent_dev
and fetches IOMMU ops from the parent device, even if the current
bus does not have any associated IOMMU ops.
This behavior works for now because QEMU's IOMMU implementations are
globally scoped, and host bridges rely on the bypass_iommu property
to skip IOMMU translation when needed.
However, this model will break with the soon to be introduced
arm-smmuv3 device, which allows users to associate the IOMMU
with a specific PCIe root complex (e.g., the default pcie.0
or a pxb-pcie root complex).
For example, consider the following setup with multiple root
complexes:
-device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0 \
...
-device pxb-pcie,id=pcie.1,bus_nr=8,bus=pcie.0 \
-device pcie-root-port,id=pcie.port1,bus=pcie.1 \
-device virtio-net-pci,bus=pcie.port1
In Qemu, pxb-pcie acts as a special root complex whose parent is
effectively the default root complex(pcie.0). Hence, though pcie.1
has no associated SMMUv3 as per above, pci_device_get_iommu_bus_devfn()
will incorrectly return the IOMMU ops from pcie.0 due to the fallback
via parent_dev.
To fix this, introduce a new helper pci_setup_iommu_per_bus() that
explicitly sets the new iommu_per_bus field in the PCIBus structure.
This helper will be used in a subsequent patch that adds support for
the new arm-smmuv3 device.
Update pci_device_get_iommu_bus_devfn() to use iommu_per_bus when
determining the correct IOMMU ops, ensuring accurate behavior for
per-bus IOMMUs.
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nathan Chen <nath...@nvidia.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Message-id: 20250829082543.7680-7-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 66d2f665e163cf1afccd171e3c16f8d3acb3d94a
https://github.com/qemu/qemu/commit/66d2f665e163cf1afccd171e3c16f8d3acb3d94a
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/virt.c
M hw/core/sysbus-fdt.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
Allow cold-plugging of an SMMUv3 device on the virt machine when no
global (legacy) SMMUv3 is present or when a virtio-iommu is specified.
This user-created SMMUv3 device is tied to a specific PCI bus provided
by the user, so ensure the IOMMU ops are configured accordingly.
Due to current limitations in QEMU’s device tree support, specifically
its inability to properly present pxb-pcie based root complexes and
their devices, the device tree support for the new SMMUv3 device is
limited to cases where it is attached to the default pcie.0 root complex.
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nathan Chen <nath...@nvidia.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Message-id: 20250829082543.7680-8-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 73d3d0187bc6b482d8b15116edce1475c7975b89
https://github.com/qemu/qemu/commit/73d3d0187bc6b482d8b15116edce1475c7975b89
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options.hx: Document the arm-smmuv3 device
Now that arm,virt can have user-creatable smmuv3 devices, document it.
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Message-id: 20250829082543.7680-9-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: c69520c13d6ea45a69a7a49361806fa05b19046d
https://github.com/qemu/qemu/commit/c69520c13d6ea45a69a7a49361806fa05b19046d
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
A tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev
A tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy
A tests/data/acpi/aarch64/virt/IORT.smmuv3-dev
A tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
bios-tables-test: Allow for smmuv3 test data.
The tests to be added exercise both legacy(iommu=smmuv3) and new
-device arm-smmuv3,.. cases.
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Message-id: 20250829082543.7680-10-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: 3f8cd046c151c471d9a34181320f4a7d3f72b32a
https://github.com/qemu/qemu/commit/3f8cd046c151c471d9a34181320f4a7d3f72b32a
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device
For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes,
one of which has bypass_iommu enabled. The generated IORT table contains
a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node.
RC node features 4 ID mappings, of which 2 points to SMMU node and the
remaining ones points to ITS.
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU0} -> {ITS}
pcie.2 -> {ITS}
[all other ids] -> {ITS}
For the -device arm-smmuv3,... test, the configuration also includes three
Root Complexes, with two connected to separate SMMUv3 devices.
The resulting IORT table contains 1 RC node, 2 SMMU nodes and 1 ITS node.
RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while
the others targets the ITS.
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU1} -> {ITS}
pcie.2 -> {ITS}
[all other ids] -> {ITS}
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Message-id: 20250829082543.7680-11-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: d35146a6606cf6ebb4e24bb97dfc0330f074f6e3
https://github.com/qemu/qemu/commit/d35146a6606cf6ebb4e24bb97dfc0330f074f6e3
Author: Shameer Kolothum <skolothum...@nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev
M tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy
M tests/data/acpi/aarch64/virt/IORT.smmuv3-dev
M tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
qtest/bios-tables-test: Update tables for smmuv3 tests
For the legacy smmuv3 test case, generated IORT has a single SMMUv3 node,
a Root Complex(RC) node and 1 ITS node.
RC node features 4 ID mappings, of which 2 points to SMMU node and the
remaining ones points to ITS.
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU0} -> {ITS}
pcie.2 -> {ITS}
[all other ids] -> {ITS}
...
[030h 0048 1] Type : 00
[031h 0049 2] Length : 0018
[033h 0051 1] Revision : 01
[034h 0052 4] Identifier : 00000000
[038h 0056 4] Mapping Count : 00000000
[03Ch 0060 4] Mapping Offset : 00000000
[040h 0064 4] ItsCount : 00000001
[044h 0068 4] Identifiers : 00000000
[048h 0072 1] Type : 04
[049h 0073 2] Length : 0058
[04Bh 0075 1] Revision : 04
[04Ch 0076 4] Identifier : 00000001
[050h 0080 4] Mapping Count : 00000001
[054h 0084 4] Mapping Offset : 00000044
[058h 0088 8] Base Address : 0000000009050000
[060h 0096 4] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
[064h 0100 4] Reserved : 00000000
[068h 0104 8] VATOS Address : 0000000000000000
[070h 0112 4] Model : 00000000
[074h 0116 4] Event GSIV : 0000006A
[078h 0120 4] PRI GSIV : 0000006B
[07Ch 0124 4] GERR GSIV : 0000006D
[080h 0128 4] Sync GSIV : 0000006C
[084h 0132 4] Proximity Domain : 00000000
[088h 0136 4] Device ID Mapping Index : 00000000
[08Ch 0140 4] Input base : 00000000
[090h 0144 4] ID Count : 0000FFFF
[094h 0148 4] Output Base : 00000000
[098h 0152 4] Output Reference : 00000030
[09Ch 0156 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0A0h 0160 1] Type : 02
[0A1h 0161 2] Length : 0074
[0A3h 0163 1] Revision : 03
[0A4h 0164 4] Identifier : 00000002
[0A8h 0168 4] Mapping Count : 00000004
[0ACh 0172 4] Mapping Offset : 00000024
[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties]
[0B0h 0176 4] Cache Coherency : 00000001
[0B4h 0180 1] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
[0B5h 0181 2] Reserved : 0000
[0B7h 0183 1] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
[0B8h 0184 4] ATS Attribute : 00000000
[0BCh 0188 4] PCI Segment Number : 00000000
[0C0h 0192 1] Memory Size Limit : 40
[0C1h 0193 2] PASID Capabilities : 0000
[0C3h 0195 1] Reserved : 00
[0C4h 0196 4] Input base : 00000000
[0C8h 0200 4] ID Count : 000001FF
[0CCh 0204 4] Output Base : 00000000
[0D0h 0208 4] Output Reference : 00000048
[0D4h 0212 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0D8h 0216 4] Input base : 00001000
[0DCh 0220 4] ID Count : 000000FF
[0E0h 0224 4] Output Base : 00001000
[0E4h 0228 4] Output Reference : 00000048
[0E8h 0232 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0ECh 0236 4] Input base : 00000200
[0F0h 0240 4] ID Count : 00000DFF
[0F4h 0244 4] Output Base : 00000200
[0F8h 0248 4] Output Reference : 00000030
[0FCh 0252 4] Flags (decoded below) : 00000000
Single Mapping : 0
[100h 0256 4] Input base : 00001100
[104h 0260 4] ID Count : 0000EEFF
[108h 0264 4] Output Base : 00001100
[10Ch 0268 4] Output Reference : 00000030
[110h 0272 4] Flags (decoded below) : 00000000
Single Mapping : 0
For the smmuv3-dev test case, IORT has 2 SMMUV3 nodes,
1 RC node and 1 ITS node.
RC node features 4 ID mappings. 2 of them target the 2
SMMU nodes while the others targets the ITS.
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU1} -> {ITS}
pcie.2 -> {ITS}
[all other ids] -> {ITS}
...
[030h 0048 1] Type : 00
[031h 0049 2] Length : 0018
[033h 0051 1] Revision : 01
[034h 0052 4] Identifier : 00000000
[038h 0056 4] Mapping Count : 00000000
[03Ch 0060 4] Mapping Offset : 00000000
[040h 0064 4] ItsCount : 00000001
[044h 0068 4] Identifiers : 00000000
[048h 0072 1] Type : 04
[049h 0073 2] Length : 0058
[04Bh 0075 1] Revision : 04
[04Ch 0076 4] Identifier : 00000001
[050h 0080 4] Mapping Count : 00000001
[054h 0084 4] Mapping Offset : 00000044
[058h 0088 8] Base Address : 000000000C000000
[060h 0096 4] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
[064h 0100 4] Reserved : 00000000
[068h 0104 8] VATOS Address : 0000000000000000
[070h 0112 4] Model : 00000000
[074h 0116 4] Event GSIV : 00000090
[078h 0120 4] PRI GSIV : 00000091
[07Ch 0124 4] GERR GSIV : 00000093
[080h 0128 4] Sync GSIV : 00000092
[084h 0132 4] Proximity Domain : 00000000
[088h 0136 4] Device ID Mapping Index : 00000000
[08Ch 0140 4] Input base : 00000000
[090h 0144 4] ID Count : 0000FFFF
[094h 0148 4] Output Base : 00000000
[098h 0152 4] Output Reference : 00000030
[09Ch 0156 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0A0h 0160 1] Type : 04
[0A1h 0161 2] Length : 0058
[0A3h 0163 1] Revision : 04
[0A4h 0164 4] Identifier : 00000002
[0A8h 0168 4] Mapping Count : 00000001
[0ACh 0172 4] Mapping Offset : 00000044
[0B0h 0176 8] Base Address : 000000000C020000
[0B8h 0184 4] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
[0BCh 0188 4] Reserved : 00000000
[0C0h 0192 8] VATOS Address : 0000000000000000
[0C8h 0200 4] Model : 00000000
[0CCh 0204 4] Event GSIV : 00000094
[0D0h 0208 4] PRI GSIV : 00000095
[0D4h 0212 4] GERR GSIV : 00000097
[0D8h 0216 4] Sync GSIV : 00000096
[0DCh 0220 4] Proximity Domain : 00000000
[0E0h 0224 4] Device ID Mapping Index : 00000000
[0E4h 0228 4] Input base : 00000000
[0E8h 0232 4] ID Count : 0000FFFF
[0ECh 0236 4] Output Base : 00000000
[0F0h 0240 4] Output Reference : 00000030
[0F4h 0244 4] Flags (decoded below) : 00000000
Single Mapping : 0
[0F8h 0248 1] Type : 02
[0F9h 0249 2] Length : 0074
[0FBh 0251 1] Revision : 03
[0FCh 0252 4] Identifier : 00000003
[100h 0256 4] Mapping Count : 00000004
[104h 0260 4] Mapping Offset : 00000024
[108h 0264 8] Memory Properties : [IORT Memory Access Properties]
[108h 0264 4] Cache Coherency : 00000001
[10Ch 0268 1] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
[10Dh 0269 2] Reserved : 0000
[10Fh 0271 1] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
[110h 0272 4] ATS Attribute : 00000000
[114h 0276 4] PCI Segment Number : 00000000
[118h 0280 1] Memory Size Limit : 40
[119h 0281 2] PASID Capabilities : 0000
[11Bh 0283 1] Reserved : 00
[11Ch 0284 4] Input base : 00000000
[120h 0288 4] ID Count : 000001FF
[124h 0292 4] Output Base : 00000000
[128h 0296 4] Output Reference : 00000048
[12Ch 0300 4] Flags (decoded below) : 00000000
Single Mapping : 0
[130h 0304 4] Input base : 00001000
[134h 0308 4] ID Count : 000000FF
[138h 0312 4] Output Base : 00001000
[13Ch 0316 4] Output Reference : 000000A0
[140h 0320 4] Flags (decoded below) : 00000000
Single Mapping : 0
[144h 0324 4] Input base : 00000200
[148h 0328 4] ID Count : 00000DFF
[14Ch 0332 4] Output Base : 00000200
[150h 0336 4] Output Reference : 00000030
[154h 0340 4] Flags (decoded below) : 00000000
Single Mapping : 0
[158h 0344 4] Input base : 00001100
[15Ch 0348 4] ID Count : 0000EEFF
[160h 0352 4] Output Base : 00001100
[164h 0356 4] Output Reference : 00000030
[168h 0360 4] Flags (decoded below) : 00000000
Single Mapping : 0
Note: DSDT changes are not described here as it is not impacted by the
way the SMMUv3 is instantiated.
Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com>
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Eric Auger <eric.au...@redhat.com>
Tested-by: Nicolin Chen <nicol...@nvidia.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
Signed-off-by: Shameer Kolothum <skolothum...@nvidia.com>
Reviewed-by: Donald Dutile <ddut...@redhat.com>
Reviewed-by: Nicolin Chen <nicol...@nvidia.com>
Message-id: 20250829082543.7680-12-skolothum...@nvidia.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: aaf042299acf83919862c7d7dd5fc36acf4e0671
https://github.com/qemu/qemu/commit/aaf042299acf83919862c7d7dd5fc36acf4e0671
Author: Stéphane Graber <stgra...@stgraber.org>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M hw/usb/dev-network.c
Log Message:
-----------
hw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR response
USB NICs have a "40:" prefix hardcoded for all MAC addresses when we
return the guest the MAC address if it queries the STRING_ETHADDR USB
string property. This doesn't match what we use for the
OID_802_3_PERMANENT_ADDRESS or OID_802_3_CURRENT_ADDRESS OIDs for
NDIS, or the MAC address we actually use in the QEMU networking code
to send/receive packets for this device, or the NIC info string we
print for users. In all those other places we directly use
s->conf.macaddr.a, which is the full thing the user asks for.
This overrides user-provided configuration and leads to an inconsistent
experience.
I couldn't find any documented reason (comment or git commits) for
this behavior. It seems like everyone is just expecting the MAC
address to be fully passed through to the guest, but it isn't.
This may have been a debugging hack that accidentally made it through
to the accepted patch: it has been in the code since it was originally
added back in 2008.
This is also particularly problematic as the "40:" prefix isn't a
reserved prefix for MAC addresses (IEEE OUI). There are a number of
valid allocations out there which use this prefix, meaning that QEMU
may be causing MAC address conflicts.
Cc: qemu-sta...@nongnu.org
Fixes: 6c9f886ceae5b ("Add CDC-Ethernet usb NIC (original patch from Thomas
Sailer)"
Signed-off-by: Stéphane Graber <stgra...@stgraber.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2951
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
[PMM: beef up commit message based on mailing list discussion]
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Commit: f0007b7f03e2d7fc33e71c3a582f2364c51a226b
https://github.com/qemu/qemu/commit/f0007b7f03e2d7fc33e71c3a582f2364c51a226b
Author: Richard Henderson <richard.hender...@linaro.org>
Date: 2025-09-17 (Wed, 17 Sep 2025)
Changed paths:
M bsd-user/arm/target_arch_elf.h
M configure
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M docs/system/arm/emulation.rst
M gdbstub/internals.h
M hw/arm/boot.c
M hw/arm/raspi4b.c
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/core/sysbus-fdt.c
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci/pci.c
M hw/usb/dev-network.c
M include/hw/arm/smmu-common.h
M include/hw/arm/virt.h
M include/hw/pci/pci.h
M include/hw/pci/pci_bridge.h
M include/hw/pci/pci_bus.h
M include/system/system.h
M linux-user/aarch64/cpu_loop.c
M linux-user/aarch64/signal.c
M linux-user/arm/elfload.c
M linux-user/arm/signal.c
M qemu-options.hx
M scripts/userfaultfd-wrlat.py
M system/globals.c
M system/vl.c
M target/arm/cpregs.h
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm.c
M target/arm/machine.c
M target/arm/ptw.c
M target/arm/tcg/cpregs-at.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/helper.h
M target/arm/tcg/hflags.c
R target/arm/tcg/iwmmxt_helper.c
M target/arm/tcg/m_helper.c
M target/arm/tcg/meson.build
M target/arm/tcg/op_helper.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
A tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev
A tests/data/acpi/aarch64/virt/DSDT.smmuv3-legacy
A tests/data/acpi/aarch64/virt/IORT.smmuv3-dev
A tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy
M tests/guest-debug/test_gdbstub.py
M tests/qtest/bios-tables-test.c
M tests/tcg/aarch64/Makefile.target
M tests/tcg/aarch64/gdbstub/test-mte.py
A tests/tcg/aarch64/gdbstub/test-sme.py
M tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
M tests/tcg/aarch64/gdbstub/test-sve.py
M tests/tcg/multiarch/gdbstub/interrupt.py
M tests/tcg/multiarch/gdbstub/memory.py
M tests/tcg/multiarch/gdbstub/sha1.py
M tests/tcg/multiarch/gdbstub/test-proc-mappings.py
M tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py
M tests/tcg/multiarch/gdbstub/test-qxfer-siginfo-read.py
M tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py
M tests/tcg/s390x/gdbstub/test-signals-s390x.py
M tests/tcg/s390x/gdbstub/test-svc.py
Log Message:
-----------
Merge tag 'pull-target-arm-20250916' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* tests, scripts: Don't import print_function from __future__
* Implement FEAT_ATS1A
* Remove deprecated pxa CPU family
* arm/kvm: report registers we failed to set
* Expose SME registers to GDB via gdbstub
* linux-user/aarch64: Generate ESR signal records
* hw/arm/raspi4b: remove redundant check in raspi_add_memory_node
* hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
* system: drop the -old-param option
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# gpg: Signature made Tue 16 Sep 2025 11:05:19 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.mayd...@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>" [unknown]
# gpg: aka "Peter Maydell <pmayd...@gmail.com>" [unknown]
# gpg: aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>"
[unknown]
# gpg: aka "Peter Maydell <pe...@archaic.org.uk>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250916' of https://gitlab.com/pm215/qemu: (36 commits)
hw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR response
qtest/bios-tables-test: Update tables for smmuv3 tests
qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device
bios-tables-test: Allow for smmuv3 test data.
qemu-options.hx: Document the arm-smmuv3 device
hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
hw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrieval
hw/arm/virt: Add an SMMU_IO_LEN macro
hw/arm/virt: Factor out common SMMUV3 dt bindings code
hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices
hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build
hw/arm/smmu-common: Check SMMU has PCIe Root Complex association
target/arm: Added test case for SME register exposure to GDB
target/arm: Added support for SME register exposure to GDB
target/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debugging
arm/kvm: report registers we failed to set
system: drop the -old-param option
target/arm: Drop ARM_FEATURE_IWMMXT handling
target/arm: Drop ARM_FEATURE_XSCALE handling
target/arm: Remove iwmmxt helper functions
...
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Compare: https://github.com/qemu/qemu/compare/6be998b9863b...f0007b7f03e2
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