Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f2d31df0d92546a86e8cdbf51436db6aae8c167a
https://github.com/qemu/qemu/commit/f2d31df0d92546a86e8cdbf51436db6aae8c167a
Author: Nicolin Chen <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M backends/iommufd.c
M backends/trace-events
M include/system/iommufd.h
Log Message:
-----------
backends/iommufd: Introduce iommufd_backend_alloc_viommu
Add a helper to allocate a viommu object.
Also introduce a struct IOMMUFDViommu that can be used later by vendor
IOMMU implementations.
Signed-off-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: cd438bf9bdf75cc7251ffb968ea59e640fe096e6
https://github.com/qemu/qemu/commit/cd438bf9bdf75cc7251ffb968ea59e640fe096e6
Author: Nicolin Chen <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M backends/iommufd.c
M backends/trace-events
M include/system/iommufd.h
Log Message:
-----------
backends/iommufd: Introduce iommufd_backend_alloc_vdev
Add a helper to allocate an iommufd device's virtual device (in the user
space) per a viommu instance.
While at it, introduce a struct IOMMUFDVdev for later use by vendor
IOMMU implementations.
Signed-off-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 8d9633f1edbbdf693f39106a23dc020476cc2ebc
https://github.com/qemu/qemu/commit/8d9633f1edbbdf693f39106a23dc020476cc2ebc
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmu-common.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu-common: Factor out common helper functions and export
Factor out common helper functions and export. Subsequent patches for
smmuv3 accel support will make use of this.
Signed-off-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 797fffedac9355495c010a12d4766517db2aa911
https://github.com/qemu/qemu/commit/797fffedac9355495c010a12d4766517db2aa911
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmu-common.c
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu-common: Make iommu ops part of SMMUState
Make iommu ops part of SMMUState and set to the current default smmu_ops.
No functional change intended. This will allow SMMUv3 accel implementation
to set a different iommu ops later.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 79fcbec80a85891b30684703d3ac96a7b992ae49
https://github.com/qemu/qemu/commit/79fcbec80a85891b30684703d3ac96a7b992ae49
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/Kconfig
M hw/arm/meson.build
A hw/arm/smmuv3-accel.c
A hw/arm/smmuv3-accel.h
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3-accel: Introduce smmuv3 accel device
Set up dedicated PCIIOMMUOps for the accel SMMUv3, since it will need
different callback handling in upcoming patches. This also adds a
CONFIG_ARM_SMMUV3_ACCEL build option so the feature can be disabled
at compile time. Because we now include CONFIG_DEVICES in the header to
check for ARM_SMMUV3_ACCEL, the meson file entry for smmuv3.c needs to
be changed to arm_ss.add.
The “accel” property isn’t user visible yet and it will be introduced in
a later patch once all the supporting pieces are ready.
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7d7931257d6f748d8f0cd595952425c19670f0b5
https://github.com/qemu/qemu/commit/7d7931257d6f748d8f0cd595952425c19670f0b5
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
Log Message:
-----------
hw/arm/smmuv3-accel: Initialize shared system address space
To support accelerated SMMUv3 instances, introduce a shared system-wide
AddressSpace (shared_as_sysmem) that aliases the global system memory.
This shared AddressSpace will be used in a subsequent patch for all
vfio-pci devices behind all accelerated SMMUv3 instances within a VM.
Sharing a single system AddressSpace ensures that all devices behind
accelerated SMMUv3s use the same system address space pointer. This
allows VFIO/iommufd to reuse a single IOAS ID in iommufd_cdev_attach(),
enabling the Stage-2 page tables to be shared within the VM rather than
duplicated for each SMMUv3 instance.
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e4eab7d4a1480016876e74081ffef10ab495210b
https://github.com/qemu/qemu/commit/e4eab7d4a1480016876e74081ffef10ab495210b
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/pci/pci.c
Log Message:
-----------
hw/pci/pci: Move pci_init_bus_master() after adding device to bus
During PCI hotplug, in do_pci_register_device(), pci_init_bus_master()
is called before storing the pci_dev pointer in bus->devices[devfn].
This causes a problem if pci_init_bus_master() (via its
get_address_space() callback) attempts to retrieve the device using
pci_find_device(), since the PCI device is not yet visible on the bus.
Fix this by moving the pci_init_bus_master() call to after the device
has been added to bus->devices[devfn].
This prepares for a subsequent patch where the accel SMMUv3
get_address_space() callback retrieves the pci_dev to identify the
attached device type.
No functional change intended.
Cc: Michael S. Tsirkin <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 84ce97290c198a36efc596aefb78f5d3b0e86f6c
https://github.com/qemu/qemu/commit/84ce97290c198a36efc596aefb78f5d3b0e86f6c
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/pci/pci.c
M include/hw/pci/pci.h
Log Message:
-----------
hw/pci/pci: Add optional supports_address_space() callback
Introduce an optional supports_address_space() callback in PCIIOMMUOps to
allow a vIOMMU implementation to reject devices that should not be attached
to it.
Currently, get_address_space() is the first and mandatory callback into the
vIOMMU layer, which always returns an address space. For certain setups, such
as hardware accelerated vIOMMUs (e.g. ARM SMMUv3 with accel=on), attaching
emulated endpoint devices is undesirable as it may impact the behavior or
performance of VFIO passthrough devices, for example, by triggering
unnecessary invalidations on the host IOMMU.
The new callback allows a vIOMMU to check and reject unsupported devices
early during PCI device registration.
Cc: Michael S. Tsirkin <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d1c585db8bb0a65107f1e5903133bc56b29c46f2
https://github.com/qemu/qemu/commit/d1c585db8bb0a65107f1e5903133bc56b29c46f2
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/pci/pci_bridge.h
Log Message:
-----------
hw/pci-bridge/pci_expander_bridge: Move TYPE_PXB_PCIE_DEV to header
Move the TYPE_PXB_PCIE_DEV definition to header so that it can be
referenced by other code in subsequent patch.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: c7ecb4cf2e9458678d649ffd3b8aa61a7976552e
https://github.com/qemu/qemu/commit/c7ecb4cf2e9458678d649ffd3b8aa61a7976552e
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
Log Message:
-----------
hw/arm/smmuv3-accel: Restrict accelerated SMMUv3 to vfio-pci endpoints with
iommufd
Accelerated SMMUv3 is only meaningful when a device can leverage the host
SMMUv3 in nested mode (S1+S2 translation). To keep the model consistent
and correct, this mode is restricted to vfio-pci endpoint devices using
the iommufd backend.
Non-endpoint emulated devices such as PCIe root ports and bridges are also
permitted so that vfio-pci devices can be attached downstream. All other
device types are unsupported in accelerated mode.
Implement supports_address_space() callback to reject all such unsupported
devices.
This restriction also avoids complications with IOTLB invalidations. Some
TLBI commands (e.g. CMD_TLBI_NH_ASID) lack an associated SID, making it
difficult to trace the originating device. Allowing emulated endpoints
would require invalidating both QEMU’s software IOTLB and the host’s
hardware IOTLB, which can significantly degrade performance.
A key design choice is the address space returned for accelerated vfio-pci
endpoints. VFIO core has a container that manages an HWPT. By default, it
allocates a stage-1 normal HWPT, unless vIOMMU requests for a nesting
parent HWPT for accelerated cases.
VFIO core adds a listener for that HWPT and sets up a handler
vfio_container_region_add() where it checks the memory region.
-If the region is a non-IOMMU translated one (system address space), VFIO
treats it as RAM and handles all stage-2 mappings for the core allocated
nesting parent HWPT.
-If the region is an IOMMU address space, VFIO instead enables IOTLB
notifier handling and translation replay, skipping the RAM listener and
therefore not installing stage-2 mappings.
For accelerated SMMUv3, correct operation requires the S1+S2 nesting
model, and therefore VFIO must take the "system address space" path so
that stage-2 mappings are properly built. Returning an alias of the
system address space ensures this happens. Returning the IOMMU address
space would omit stage-2 mapping and break nested translation.
Another option considered was forcing a pre-registration path using
vfio_prereg_listener() to set up stage-2 mappings, but this requires
changes in VFIO core and was not adopted. Returning an alias of the
system address space keeps the design aligned with existing VFIO/iommufd
nesting flows and avoids the need for cross-subsystem changes.
In summary:
- vfio-pci devices(with iommufd as backend) return an address space
aliased to system address space.
- bridges and root ports return the IOMMU address space.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: fc6dafb98cec0905fca61c15eb8287de75af2230
https://github.com/qemu/qemu/commit/fc6dafb98cec0905fca61c15eb8287de75af2230
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
Log Message:
-----------
hw/arm/smmuv3: Implement get_viommu_cap() callback
For accelerated SMMUv3, we need nested parent domain creation. Add the
callback support so that VFIO can create a nested parent.
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 703b7b91db064b94bb67bc49eaf503b2d6a8d333
https://github.com/qemu/qemu/commit/703b7b91db064b94bb67bc49eaf503b2d6a8d333
Author: Nicolin Chen <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3-accel.h
M hw/arm/trace-events
M include/hw/arm/smmuv3-common.h
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3-accel: Add set/unset_iommu_device callback
Implement the VFIO/PCI callbacks to attach and detach a HostIOMMUDevice
to a vSMMUv3 when accel=on,
- set_iommu_device(): attach a HostIOMMUDevice to a vIOMMU
- unset_iommu_device(): detach and release associated resources
In SMMUv3 accel=on mode, the guest SMMUv3 is backed by the host SMMUv3 via
IOMMUFD. A vIOMMU object (created via IOMMU_VIOMMU_ALLOC) provides a per-VM,
security-isolated handle to the physical SMMUv3. Without a vIOMMU, the
vSMMUv3 cannot relay guest operations to the host hardware nor maintain
isolation across VMs or devices. Therefore, set_iommu_device() allocates
a vIOMMU object if one does not already exist.
There are two main points to consider in this implementation:
1) VFIO core allocates and attaches a S2 HWPT that acts as the nesting
parent for nested HWPTs(IOMMU_DOMAIN_NESTED). This parent HWPT will
be shared across multiple vSMMU instances within a VM.
2) A device cannot attach directly to a vIOMMU. Instead, it attaches
through a proxy nested HWPT (IOMMU_DOMAIN_NESTED). Based on the STE
configuration,there are three types of nested HWPTs: bypass, abort,
and translate.
-The bypass and abort proxy HWPTs are pre-allocated. When SMMUv3
operates in global abort or bypass modes, as controlled by the GBPA
register, or issues a vSTE for bypass or abort we attach these
pre-allocated nested HWPTs.
-The translate HWPT requires a vDEVICE to be allocated first, since
invalidations and events depend on a valid vSID.
-The vDEVICE allocation and attach operations for vSTE based HWPTs
are implemented in subsequent patches.
In summary, a device placed behind a vSMMU instance must have a vSID for
translate vSTE. The bypass and abort vSTEs are pre-allocated as proxy
nested HWPTs and is attached based on GBPA register. The core-managed
nesting parent S2 HWPT is used as parent S2 HWPT for all the nested
HWPTs and is intended to be shared across vSMMU instances within the
same VM.
set_iommu_device():
- Reuse an existing vIOMMU for the same physical SMMU if available.
If not, allocate a new one using the nesting parent S2 HWPT.
- Pre-allocate two proxy nested HWPTs (bypass and abort) under the
vIOMMU and install one based on GBPA.ABORT value.
- Add the device to the vIOMMU’s device list.
unset_iommu_device():
- Re-attach device to the nesting parent S2 HWPT.
- Remove the device from the vIOMMU’s device list.
- If the list is empty, free the proxy HWPTs (bypass and abort)
and release the vIOMMU object.
Introduce struct SMMUv3AccelState, representing an accelerated SMMUv3
instance backed by an iommufd vIOMMU object, and storing the bypass and
abort proxy HWPT IDs.
Signed-off-by: Nicolin Chen <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 95d855167af43e958903f29430f563205b8b2afd
https://github.com/qemu/qemu/commit/95d855167af43e958903f29430f563205b8b2afd
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: propagate smmuv3_cmdq_consume() errors to caller
smmuv3_cmdq_consume() is updated to return detailed errors via errp.
Although this is currently a no-op, it prepares the ground for accel
SMMUv3 specific command handling where proper error reporting will be
useful.
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2da17a988c2d387b8fde04fdaddf03afa73085f5
https://github.com/qemu/qemu/commit/2da17a988c2d387b8fde04fdaddf03afa73085f5
Author: Nicolin Chen <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3-accel.h
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M include/hw/arm/smmuv3-common.h
Log Message:
-----------
hw/arm/smmuv3-accel: Add nested vSTE install/uninstall support
A device placed behind a vSMMU instance must have corresponding vSTEs
(bypass, abort, or translate) installed. The bypass and abort proxy nested
HWPTs are pre-allocated.
For translat HWPT, a vDEVICE object is allocated and associated with the
vIOMMU for each guest device. This allows the host kernel to establish a
virtual SID to physical SID mapping, which is required for handling
invalidations and event reporting.
An translate HWPT is allocated based on the guest STE configuration and
attached to the device when the guest issues SMMU_CMD_CFGI_STE or
SMMU_CMD_CFGI_STE_RANGE, provided the STE enables S1 translation.
If the guest STE is invalid or S1 translation is disabled, the device is
attached to one of the pre-allocated ABORT or BYPASS HWPTs instead.
While at it, export smmu_find_ste() for use here.
Signed-off-by: Nicolin Chen <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: b6b867b9c16d479af0ba95ac71411a0ff788220a
https://github.com/qemu/qemu/commit/b6b867b9c16d479af0ba95ac71411a0ff788220a
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3-accel.h
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3-accel: Install SMMUv3 GBPA based hwpt
On guest reboot or on GBPA update, attach a nested HWPT based on the
GPBA.ABORT bit which either aborts all incoming transactions or bypasses
them.
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5c921b29c9898bc44b86b88127b9e9bef76dc2ef
https://github.com/qemu/qemu/commit/5c921b29c9898bc44b86b88127b9e9bef76dc2ef
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/pci/pci.c
M include/hw/pci/pci.h
M target/arm/kvm.c
Log Message:
-----------
hw/pci/pci: Introduce a callback to retrieve the MSI doorbell GPA directly
For certain vIOMMU implementations, such as SMMUv3 in accelerated mode,
the translation tables are programmed directly into the physical SMMUv3
in a nested configuration. While QEMU knows where the guest tables live,
safely walking them in software would require trapping and ordering all
guest invalidations on every command queue. Without this, QEMU could race
with guest updates and walk stale or freed page tables.
This constraint is fundamental to the design of HW-accelerated vSMMU when
used with downstream vfio-pci endpoint devices, where QEMU must never walk
guest translation tables and must rely on the physical SMMU for
translation. Future accelerated vSMMU features, such as virtual CMDQ, will
also prevent trapping invalidations, reinforcing this restriction.
For vfio-pci endpoints behind such a vSMMU, the only translation QEMU
needs is for the MSI doorbell used when setting up KVM MSI route tables.
Instead of attempting a software walk, introduce an optional vIOMMU
callback that returns the MSI doorbell GPA directly.
kvm_arch_fixup_msi_route() uses this callback when available and ignores
the guest provided IOVA in that case.
If the vIOMMU does not implement the callback, we fall back to the
existing IOMMU based address space translation path.
This ensures correct MSI routing for accelerated SMMUv3 + VFIO passthrough
while avoiding unsafe software walks of guest translation tables.
As a related change, replace RCU_READ_LOCK_GUARD() with explicit
rcu_read_lock()/rcu_read_unlock(). The introduction of an early goto
(set_doorbell) path means the RCU read side critical section can no longer
be safely scoped using RCU_READ_LOCK_GUARD().
Cc: Michael S. Tsirkin <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3558c85392a46db064eb983633de998a25ea9705
https://github.com/qemu/qemu/commit/3558c85392a46db064eb983633de998a25ea9705
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3-accel: Implement get_msi_direct_gpa callback
Accelerated SMMUv3 instances rely on the physical SMMUv3 for nested
translation (guest Stage-1, host Stage-2). In this mode, the guest Stage-1
tables are programmed directly into hardware, and QEMU must not attempt to
walk them for translation, as doing so is not reliably safe. For vfio-pci
endpoints behind such a vSMMU, the only translation QEMU needs to perform
is for the MSI doorbell used during KVM MSI setup.
Implement the callback so that kvm_arch_fixup_msi_route() can retrieve the
MSI doorbell GPA directly, instead of attempting a software walk of the
guest translation tables.
Also introduce an SMMUv3 device property to carry the MSI doorbell GPA.
This property will be set by the virt machine in a subsequent patch.
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5ec2700dcbf72c6bbeb00322e5258f999071d9d5
https://github.com/qemu/qemu/commit/5ec2700dcbf72c6bbeb00322e5258f999071d9d5
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Set msi-gpa property
Set the MSI doorbell GPA property for accelerated SMMUv3 devices for use
by KVM MSI setup. Also, since any meaningful use of vfio-pci devices with
an accelerated SMMUv3 requires both KVM and a kernel irqchip, ensure
those are specified when accel=on is selected.
Reviewed-by: Nicolin Chen <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 58a789c389cb691c8b25c1a673cfffe49fe93554
https://github.com/qemu/qemu/commit/58a789c389cb691c8b25c1a673cfffe49fe93554
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3-accel.h
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3-accel: Add support to issue invalidation cmd to host
Provide a helper and use that to issue the invalidation cmd to host SMMUv3.
We only issue one cmd at a time for now.
Support for batching of commands will be added later after analysing the
impact.
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f577dcdb5c1ca7d458d2cb365e884813c1505f9b
https://github.com/qemu/qemu/commit/f577dcdb5c1ca7d458d2cb365e884813c1505f9b
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Initialize ID registers early during realize()
Factor out ID register init into smmuv3_init_id_regs() and call it from
realize(). This ensures ID registers are initialized early for use in the
accelerated SMMUv3 path and will be utilized in subsequent patch.
Other registers remain initialized in smmuv3_reset().
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ad32238ad26bcaa6293742dd712782425253b6fe
https://github.com/qemu/qemu/commit/ad32238ad26bcaa6293742dd712782425253b6fe
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
Log Message:
-----------
hw/arm/smmuv3-accel: Get host SMMUv3 hw info and validate
Just before the device gets attached to the SMMUv3, make sure QEMU SMMUv3
features are compatible with the host SMMUv3.
Not all fields in the host SMMUv3 IDR registers are meaningful for userspace.
Only the following fields can be used:
- IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
- IDR1: SIDSIZE, SSIDSIZE
- IDR3: BBML, RIL
- IDR5: VAX, GRAN64K, GRAN16K, GRAN4K
For now, the check is to make sure the features are in sync to enable
basic accelerated SMMUv3 support. AIDR is not checked, as hardware
implementations often provide a mix of architecture features regardless
of the revision reported in AIDR.
Note that SSIDSIZE check will be added later when support for PASID is
introduced.
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 59a5c80623abbb7f5f52fc227cfe0c142858858c
https://github.com/qemu/qemu/commit/59a5c80623abbb7f5f52fc227cfe0c142858858c
Author: Eric Auger <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/pci-host/gpex-acpi.c
M include/hw/pci-host/gpex.h
Log Message:
-----------
hw/pci-host/gpex: Allow to generate preserve boot config DSM #5
Add a 'preserve_config' field in struct GPEXConfig and, if set, generate
the _DSM function #5 for preserving PCI boot configurations.
This will be used for SMMUv3 accel=on support in subsequent patch. When
SMMUv3 acceleration (accel=on) is enabled, QEMU exposes IORT Reserved
Memory Region (RMR) nodes to support MSI doorbell translations. As per
the Arm IORT specification, using IORT RMRs mandates the presence of
_DSM function #5 so that the OS retains the firmware-assigned PCI
configuration. Hence, this patch adds conditional support for generating
_DSM #5.
According to the ACPI Specification, Revision 6.6, Section 9.1.1 -
“_DSM (Device Specific Method)”,
"
If Function Index is zero, the return is a buffer containing one bit for
each function index, starting with zero. Bit 0 indicates whether there
is support for any functions other than function 0 for the specified
UUID and Revision ID. If set to zero, no functions are supported (other
than function zero) for the specified UUID and Revision ID. If set to
one, at least one additional function is supported. For all other bits
in the buffer, a bit is set to zero to indicate if that function index
is not supported for the specific UUID and Revision ID. (For example,
bit 1 set to 0 indicates that function index 1 is not supported for the
specific UUID and Revision ID.)
"
Please refer PCI Firmware Specification, Revision 3.3, Section 4.6.5 —
"_DSM for Preserving PCI Boot Configurations" for Function 5 of _DSM
method.
Also, while at it, move the byte_list declaration to the top of the
function for clarity.
At the moment, DSM generation is not yet enabled.
The resulting AML when preserve_config=true is:
Method (_DSM, 4, NotSerialized)
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d")))
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x21
})
}
If ((Arg2 == 0x05))
{
Return (Zero)
}
}
...
}
Cc: Michael S. Tsirkin <[email protected]>
Signed-off-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Tested-by: Eric Auger <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Message-id: [email protected]
[Shameer: Removed possible duplicate _DSM creations]
Signed-off-by: Shameer Kolothum <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 45c57eaefd4c7a67c93e77d6f4436c8569aefbb9
https://github.com/qemu/qemu/commit/45c57eaefd4c7a67c93e77d6f4436c8569aefbb9
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Set PCI preserve_config for accel SMMUv3
Introduce a new pci_preserve_config field in virt machine state which
allows the generation of DSM #5. This field is only set if accel SMMU
is instantiated.
In a subsequent patch, SMMUv3 accel mode will make use of IORT RMR nodes
to enable nested translation of MSI doorbell addresses. IORT RMR requires
_DSM #5 to be set for the PCI host bridge so that the Guest kernel
preserves the PCI boot configuration.
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: b8e196a746eb279ba5b713de9b236259f944c82d
https://github.com/qemu/qemu/commit/b8e196a746eb279ba5b713de9b236259f944c82d
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/qtest/bios-tables-test: Prepare for IORT revison upgrade
Subsequent patch will upgrade IORT revision to 5 to add support
for IORT RMR nodes.
Add the affected IORT blobs to allowed-diff list for bios-table
tests.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 06c0c8fde7867f634f226cec6a318606885b9bc8
https://github.com/qemu/qemu/commit/06c0c8fde7867f634f226cec6a318606885b9bc8
Author: Eric Auger <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding
To handle SMMUv3 accel=on mode(which configures the host SMMUv3 in nested
mode), it is practical to expose the guest with reserved memory regions
(RMRs) covering the IOVAs used by the host kernel to map physical MSI
doorbells.
Those IOVAs belong to [0x8000000, 0x8100000] matching MSI_IOVA_BASE and
MSI_IOVA_LENGTH definitions in kernel arm-smmu-v3 driver. This is the
window used to allocate IOVAs matching physical MSI doorbells.
With those RMRs, the guest is forced to use a flat mapping for this range.
Hence the assigned device is programmed with one IOVA from this range.
Stage 1, owned by the guest has a flat mapping for this IOVA. Stage2,
owned by the VMM then enforces a mapping from this IOVA to the physical
MSI doorbell.
The creation of those RMR nodes is only relevant if nested stage SMMU is
in use, along with VFIO. As VFIO devices can be hotplugged, all RMRs need
to be created in advance.
Initialise AcpiIortSMMUv3Dev structures to avoid using uninitialised
state when building the IORT, as legacy and device SMMUv3 paths
populate different fields now(e.g. accel).
Signed-off-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Signed-off-by: Nicolin Chen <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Tested-by: Eric Auger <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Message-id: [email protected]
Suggested-by: Jean-Philippe Brucker <[email protected]>
Signed-off-by: Nicolin Chen <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: f48bddafa251503a2aa4a6eb9dd612ec9c0781f7
https://github.com/qemu/qemu/commit/f48bddafa251503a2aa4a6eb9dd612ec9c0781f7
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M tests/data/acpi/aarch64/virt/IORT
M tests/data/acpi/aarch64/virt/IORT.its_off
M tests/data/acpi/aarch64/virt/IORT.smmuv3-dev
M tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/qtest/bios-tables-test: Update IORT blobs after revision upgrade
Update the reference IORT blobs after revision upgrade for RMR node
support. This affects the aarch64 'virt' IORT tests.
IORT diff is the same for all the tests:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20230628 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporation
*
- * Disassembly of tests/data/acpi/aarch64/virt/IORT, Mon Oct 20 14:42:41 2025
+ * Disassembly of /tmp/aml-B4ZRE3, Mon Oct 20 14:42:41 2025
*
* ACPI Data Table [IORT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in
hex)
*/
[000h 0000 004h] Signature : "IORT" [IO Remapping Table]
[004h 0004 004h] Table Length : 00000080
-[008h 0008 001h] Revision : 03
-[009h 0009 001h] Checksum : B3
+[008h 0008 001h] Revision : 05
+[009h 0009 001h] Checksum : B1
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[018h 0024 004h] Oem Revision : 00000001
[01Ch 0028 004h] Asl Compiler ID : "BXPC"
[020h 0032 004h] Asl Compiler Revision : 00000001
...
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: be0cf3c8f121f5c0ec398429666d2ef0e88aa37a
https://github.com/qemu/qemu/commit/be0cf3c8f121f5c0ec398429666d2ef0e88aa37a
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3: Block migration when accel is enabled
Live migration is not supported when the SMMUv3 accelerator mode is
enabled. Add a migration blocker to prevent migration in this
configuration.
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 6cc3a621c6f184ffa04bf68f7a57323c63f6ef56
https://github.com/qemu/qemu/commit/6cc3a621c6f184ffa04bf68f7a57323c63f6ef56
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
Log Message:
-----------
hw/arm/smmuv3: Add accel property for SMMUv3 device
Add an "accel" property to enable SMMUv3 accelerator mode.
Accelerator mode relies on IORT RMR entries for MSI support and is
therefore not supported when booting with a device tree.
In this mode, the host SMMUv3 operates in nested translation
(Stage-1 + Stage-2), with the guest owning the Stage-1 page tables.
Expose only Stage-1 to the guest to ensure it uses the correct page
table format
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: bd715ff5bda973c85caa16f1cabf1e9aef30dc70
https://github.com/qemu/qemu/commit/bd715ff5bda973c85caa16f1cabf1e9aef30dc70
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3-accel.h
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3-accel: Add a property to specify RIL support
Currently QEMU SMMUv3 has RIL support by default. But if accelerated mode
is enabled, RIL has to be compatible with host SMMUv3 support.
Add a property so that the user can specify this.
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f7f5013a55a3447ca81383d8969626e092feb0c9
https://github.com/qemu/qemu/commit/f7f5013a55a3447ca81383d8969626e092feb0c9
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3.c
M hw/arm/virt-acpi-build.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3-accel: Add support for ATS
QEMU SMMUv3 does not enable ATS (Address Translation Services) by default.
When accelerated mode is enabled and the host SMMUv3 supports ATS, it can
be useful to report ATS capability to the guest so it can take advantage
of it if the device also supports ATS.
Note: ATS support cannot be reliably detected from the host SMMUv3 IDR
registers alone, as firmware ACPI IORT tables may override them. The
user must therefore ensure the support before enabling it.
The ATS support enabled here is only relevant for vfio-pci endpoints,
as SMMUv3 accelerated mode does not support emulated endpoint devices.
QEMU’s SMMUv3 implementation still lacks support for handling ATS
translation requests, which would be required for emulated endpoints.
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: a015ac990fd31bd4c93ce430aa4fce19dbfa49f8
https://github.com/qemu/qemu/commit/a015ac990fd31bd4c93ce430aa4fce19dbfa49f8
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3-common.h
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3-accel: Add property to specify OAS bits
QEMU SMMUv3 currently sets the output address size (OAS) to 44 bits.
With accelerator mode enabled, a device may use SVA, where CPU page tables
are shared with the SMMU, requiring an OAS at least as large as the
CPU’s output address size. A user option is added to configure this.
However, the OAS value advertised by the virtual SMMU must remain
compatible with the capabilities of the host SMMUv3. In accelerated
mode, the host SMMU performs stage-2 translation and must be able to
consume the intermediate physical addresses (IPA) produced by stage-1.
The OAS exposed by the virtual SMMU defines the maximum IPA width that
stage-1 translations may generate. For AArch64 implementations, the
maximum usable IPA size on the host SMMU is determined by its own OAS.
Check that the configured OAS does not exceed what the host SMMU
can safely support.
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 550beca3d7b0159681a09d63dfce19ac31509f9f
https://github.com/qemu/qemu/commit/550beca3d7b0159681a09d63dfce19ac31509f9f
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M backends/iommufd.c
M hw/arm/smmuv3-accel.c
M hw/vfio/iommufd.c
M include/system/host_iommu_device.h
M include/system/iommufd.h
Log Message:
-----------
backends/iommufd: Retrieve PASID width from iommufd_backend_get_device_info()
Retrieve PASID width from iommufd_backend_get_device_info() and store it
in HostIOMMUDeviceCaps for later use.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Tested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 22afd9d865cb05d93c92c8fca7a23e1eb879e889
https://github.com/qemu/qemu/commit/22afd9d865cb05d93c92c8fca7a23e1eb879e889
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M backends/iommufd.c
M include/system/host_iommu_device.h
Log Message:
-----------
backends/iommufd: Add get_pasid_info() callback
The get_pasid_info callback retrieves PASID capability information
when the HostIOMMUDevice backend supports it. Currently, only the
Linux IOMMUFD backend provides this information.
This will be used by a subsequent patch to synthesize a PASID
capability for vfio-pci devices behind a vIOMMU that supports PASID.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 49a2bed19b0e4e68bdc06e6c37532313193e766c
https://github.com/qemu/qemu/commit/49a2bed19b0e4e68bdc06e6c37532313193e766c
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/pci/pcie.c
M include/hw/pci/pcie.h
Log Message:
-----------
hw/pci: Add helper to insert PCIe extended capability at a fixed offset
Add pcie_insert_capability(), a helper to insert a PCIe extended
capability into an existing extended capability list at a caller
specified offset.
Unlike pcie_add_capability(), which always appends a capability to the
end of the list, this helper preserves the existing list ordering while
allowing insertion at an arbitrary offset.
The helper only validates that the insertion does not overwrite an
existing PCIe extended capability header, since corrupting a header
would break the extended capability linked list. Validation of overlaps
with other configuration space registers or capability-specific
register blocks is left to the caller.
Reviewed-by: Michael S. Tsirkin <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7d59fa20594ec053861f7c49ac53090a41901209
https://github.com/qemu/qemu/commit/7d59fa20594ec053861f7c49ac53090a41901209
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/pci/pcie.c
M include/hw/pci/pcie.h
Log Message:
-----------
hw/pci: Factor out common PASID capability initialization
Refactor PCIe PASID capability initialization by moving the common
register init into a new helper, pcie_pasid_common_init().
Subsequent patch to synthesize a vPASID will make use of this
helper.
No functional change intended.
Cc: Michael S. Tsirkin <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 06b38473cda8cbeb5f4aa0c2480c3b8c06a8d500
https://github.com/qemu/qemu/commit/06b38473cda8cbeb5f4aa0c2480c3b8c06a8d500
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/vfio/pci.c
M hw/vfio/pci.h
M hw/vfio/trace-events
M include/hw/core/iommu.h
Log Message:
-----------
hw/vfio/pci: Synthesize PASID capability for vfio-pci devices
Add support for synthesizing a PCIe PASID extended capability for
vfio-pci devices when PASID is enabled via a vIOMMU and supported by
the host IOMMU backend.
PASID capability parameters are retrieved via IOMMUFD APIs and the
capability is inserted into the PCIe extended capability list using
the insertion helper. A new x-vpasid-cap-offset property allows
explicit control over the placement; by default the capability is
placed at the end of the PCIe extended configuration space.
If the kernel does not expose PASID information or insertion fails,
the device continues without PASID support.
Reviewed-by: Jonathan Cameron <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Yi Liu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: b8c6f8a69d2734a65a00f11788d6711e5d28a4ec
https://github.com/qemu/qemu/commit/b8c6f8a69d2734a65a00f11788d6711e5d28a4ec
Author: Shameer Kolothum <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M hw/arm/smmuv3-accel.c
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3-common.h
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm/smmuv3-accel: Make SubstreamID support configurable
QEMU SMMUv3 currently reports no SubstreamID support, forcing SSID to
zero. This prevents accelerated use cases such as Shared Virtual
Addressing (SVA), which require multiple Stage-1 context descriptors
indexed by SubstreamID.
Add a new "ssidsize" property to explicitly configure the number of bits
used for SubstreamIDs. A value greater than zero enables SubstreamID
support and advertises PASID capability to the vIOMMU.
The requested SSIDSIZE is validated against host SMMUv3 capabilities and
is only supported when accel=on.
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Tested-by: Eric Auger <[email protected]>
Tested-by: Zhangfei Gao <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: c0f2a78e2c7f449a07d2432cc7905c9c48e2fa3b
https://github.com/qemu/qemu/commit/c0f2a78e2c7f449a07d2432cc7905c9c48e2fa3b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
target/arm/hvf: Move hvf_sysreg_[read, write]_cp() functions around
Next commit will use these functions prototype earlier. Rather
than forward-declaring them, move them around.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: bfbea371ef2cabc47effac5a286e2644d727a8d6
https://github.com/qemu/qemu/commit/bfbea371ef2cabc47effac5a286e2644d727a8d6
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
target/arm/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0
Keep CNTV_CTL_EL0 and CNTV_CVAL_EL0 synchronized with the
host hardware accelerator.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 591b9b94cea67d3ea733a7162bd98b395c9ab570
https://github.com/qemu/qemu/commit/591b9b94cea67d3ea733a7162bd98b395c9ab570
Author: Alex Bennée <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: add emulation.rst to ARM TCG CPUs
This is updated as Arm architectural features are added so we should
catch changes to the docs as well.
Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 8a0d94ab4adbe219942084926ba0fdd363c22a63
https://github.com/qemu/qemu/commit/8a0d94ab4adbe219942084926ba0fdd363c22a63
Author: Alex Bennée <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M docs/system/arm/emulation.rst
Log Message:
-----------
docs/system: update FEAT_BBML[12] references
It looks like the features were renamed to include the levels at some
point. To make it easier to match features up to the Arm ARM update to
use the full name.
Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7d2e2d0941be49b11143698e23f10b61fffb32e7
https://github.com/qemu/qemu/commit/7d2e2d0941be49b11143698e23f10b61fffb32e7
Author: Cornelia Huck <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/translate-a64.c
Log Message:
-----------
arm: add {get,set}_dczid_bs helpers
Most accesses to cpu->dcz_blocksize really care about
DCZID_EL0.BS (i.e. the part of the register that does not change at
different EL.) Wean them off directly dealing with cpu->dcz_blocksize
so that we can switch to handling DCZID_EL0 differently in a followup
patch.
Signed-off-by: Cornelia Huck <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Sebastian Ott <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5252c077467a5570bf3b6b6278d206c46f51f9b8
https://github.com/qemu/qemu/commit/5252c077467a5570bf3b6b6278d206c46f51f9b8
Author: Cornelia Huck <[email protected]>
Date: 2026-01-29 (Thu, 29 Jan 2026)
Changed paths:
M target/arm/cpu-sysregs.h.inc
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/tcg/translate.h
Log Message:
-----------
arm: add DCZID_EL0 to idregs array
Continue moving ID registers to the idregs array, so that we
eventually can switch to an autogenerated cpu-sysregs.h.inc.
This requires a bit of care, since we still have to handle the EL
specific part (DCZID_EL0.DZP). The value previously saved in
cpu->dcz_blocksize is now kept in DCZID_EL.BS (transparent to
callers using the wrappers.)
KVM currently does not support DCZID_EL0 via ONE_REG, assert that
we're not trying to do anything with it until it does.
Signed-off-by: Cornelia Huck <[email protected]>
Reviewed-by: Sebastian Ott <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 792d94406ab911ed637d7d770e99633b2a77a72a
https://github.com/qemu/qemu/commit/792d94406ab911ed637d7d770e99633b2a77a72a
Author: Alex Bennée <[email protected]>
Date: 2026-01-30 (Fri, 30 Jan 2026)
Changed paths:
M .gitlab-ci.d/container-cross.yml
M .gitlab-ci.d/container-template.yml
R tests/docker/dockerfiles/emsdk-wasm-cross.docker
A tests/docker/dockerfiles/emsdk-wasm64-cross.docker
Log Message:
-----------
tests/docker: rename wasm cross container
Now we are 64 bit only there is no need to keep the generic name. This
also fixes a check failure in the weekly container build which was
checking containers based on the expansion of DOCKER_IMAGES which is
based of the dockerfile names.
Remove the DOCKERFILE bits that were added to handle multiple
containers from the same dockerfile.
Fixes: 4203ea0247f (gitlab-ci: Add build tests for wasm64)
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>
Commit: d9ca273f8f31acb22d3f5aca5f063b94fb962e19
https://github.com/qemu/qemu/commit/d9ca273f8f31acb22d3f5aca5f063b94fb962e19
Author: Alex Bennée <[email protected]>
Date: 2026-01-30 (Fri, 30 Jan 2026)
Changed paths:
M tests/functional/aarch64/test_sbsaref.py
Log Message:
-----------
tests/functional: migrate sbsa_ref test images
As the builds in codelinaro.org are going away migrate the binaries to
share.linaro.org. As the hotlinks don't encode the filename we need to
explicitly tell uncompress how to handle the files.
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>
Commit: b6bba79e97dd6ecfceaf30b88da5c71963fb9d37
https://github.com/qemu/qemu/commit/b6bba79e97dd6ecfceaf30b88da5c71963fb9d37
Author: Richard Henderson <[email protected]>
Date: 2026-02-02 (Mon, 02 Feb 2026)
Changed paths:
M .gitlab-ci.d/container-cross.yml
M .gitlab-ci.d/container-template.yml
R tests/docker/dockerfiles/emsdk-wasm-cross.docker
A tests/docker/dockerfiles/emsdk-wasm64-cross.docker
M tests/functional/aarch64/test_sbsaref.py
Log Message:
-----------
Merge tag 'pull-11.0-testing-fixes-300126-1' of
https://gitlab.com/stsquad/qemu into staging
testing updates (sbsa-ref, docker)
- restore weekly container job
- move assets for sbsa-ref tests
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# gpg: Signature made Sat 31 Jan 2026 12:53:52 AM AEDT
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key)
<[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
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* tag 'pull-11.0-testing-fixes-300126-1' of https://gitlab.com/stsquad/qemu:
tests/functional: migrate sbsa_ref test images
tests/docker: rename wasm cross container
Signed-off-by: Richard Henderson <[email protected]>
Commit: d21a442a5ab9bc1597afea13f01113d5bb3e772c
https://github.com/qemu/qemu/commit/d21a442a5ab9bc1597afea13f01113d5bb3e772c
Author: Richard Henderson <[email protected]>
Date: 2026-02-02 (Mon, 02 Feb 2026)
Changed paths:
M MAINTAINERS
M backends/iommufd.c
M backends/trace-events
M docs/system/arm/emulation.rst
M hw/arm/Kconfig
M hw/arm/meson.build
M hw/arm/smmu-common.c
A hw/arm/smmuv3-accel.c
A hw/arm/smmuv3-accel.h
M hw/arm/smmuv3-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci-host/gpex-acpi.c
M hw/pci/pci.c
M hw/pci/pcie.c
M hw/vfio/iommufd.c
M hw/vfio/pci.c
M hw/vfio/pci.h
M hw/vfio/trace-events
M include/hw/arm/smmu-common.h
M include/hw/arm/smmuv3-common.h
M include/hw/arm/smmuv3.h
M include/hw/arm/virt.h
M include/hw/core/iommu.h
M include/hw/pci-host/gpex.h
M include/hw/pci/pci.h
M include/hw/pci/pci_bridge.h
M include/hw/pci/pcie.h
M include/system/host_iommu_device.h
M include/system/iommufd.h
M target/arm/cpu-sysregs.h.inc
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/kvm.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.h
M tests/data/acpi/aarch64/virt/IORT
M tests/data/acpi/aarch64/virt/IORT.its_off
M tests/data/acpi/aarch64/virt/IORT.smmuv3-dev
M tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy
Log Message:
-----------
Merge tag 'pull-target-arm-20260129' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* Support SMMUv3 acceleration
* A few other minor cleanups and fixes
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# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [unknown]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# gpg: aka "Peter Maydell <[email protected]>"
[unknown]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
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# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20260129' of https://gitlab.com/pm215/qemu: (43 commits)
arm: add DCZID_EL0 to idregs array
arm: add {get,set}_dczid_bs helpers
docs/system: update FEAT_BBML[12] references
MAINTAINERS: add emulation.rst to ARM TCG CPUs
target/arm/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0
target/arm/hvf: Move hvf_sysreg_[read, write]_cp() functions around
hw/arm/smmuv3-accel: Make SubstreamID support configurable
hw/vfio/pci: Synthesize PASID capability for vfio-pci devices
hw/pci: Factor out common PASID capability initialization
hw/pci: Add helper to insert PCIe extended capability at a fixed offset
backends/iommufd: Add get_pasid_info() callback
backends/iommufd: Retrieve PASID width from iommufd_backend_get_device_info()
hw/arm/smmuv3-accel: Add property to specify OAS bits
hw/arm/smmuv3-accel: Add support for ATS
hw/arm/smmuv3-accel: Add a property to specify RIL support
hw/arm/smmuv3: Add accel property for SMMUv3 device
hw/arm/smmuv3: Block migration when accel is enabled
tests/qtest/bios-tables-test: Update IORT blobs after revision upgrade
hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding
tests/qtest/bios-tables-test: Prepare for IORT revison upgrade
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/a8e6997ef81a...d21a442a5ab9
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