Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 03f1049bc5d89551ea8f02f3b58059a9da598c5d
https://github.com/qemu/qemu/commit/03f1049bc5d89551ea8f02f3b58059a9da598c5d
Author: Daniel Henrique Barboza <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M tests/functional/riscv64/test_boston.py
Log Message:
-----------
riscv64/test_boston.py: fix intermitent test timeout
The recently added Boston MIPS board selftest times out consistently in a
machine running 'make check-functional' with -j 16:
18/18 func-thorough+func-riscv64-thorough+thorough - qemu:func-riscv64-boston
TIMEOUT 120.09s killed by signal 15 SIGTERM
The reason is quite boring: it is testing too much stuff.
Note that functional tests aren't supposed to be used as stress tests,
e.g. it doesn't have to test every single corner case that might hit the
board. It is supposed to catch most common user ooopsies. A timeout, in
this context, is most likely to be considered something abnormal slowing
down the emulation, not a lack of CPU horsepower to run all the tests
before timeout.
Some of the tests claim to test odd CPU SMP numbers to either "ensures
proper core distribution across clusters" or "validating proper handling
of larger asymmetric SMP configurations". But there's no SMP/NUMA check
made anywhere after boot, so in the end we're just testing whether the
board is able to boot with 7/35 CPUs. As far as these tests are concerned
we could have a completely broken, but bootable, SMP topology with 7/35
CPUS, and we're oblivious about it.
Remove the 7 and 35 SMP tests, keeping the minimal CPUs (2) and maximum
(64) tests. With these changes we're now able to run the test with a
good TIMEOUT margin:
17/18 func-thorough+func-riscv64-thorough+thorough - qemu:func-riscv64-boston
OK 61.28s 3 subtests passed
Fixes: e71111e26b ("test/functional: Add test for boston-aia board")
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Djordje Todorovic <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 4d784c9120fb27efc2adb5fac1e93aa26b2f07a8
https://github.com/qemu/qemu/commit/4d784c9120fb27efc2adb5fac1e93aa26b2f07a8
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/mmu_helper.c
Log Message:
-----------
target/s390x: Use address_space_ldq_be() in read_table_entry()
address_space_read/write() is meant for accessing random
amount of memory blobs. When the access size is known,
use the address_space_ld/st() API which can directly swap
endianness.
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Eric Farman <[email protected]>
Message-Id: <[email protected]>
Commit: 8a2286cd40cca4fe535491802879fe45946748fc
https://github.com/qemu/qemu/commit/8a2286cd40cca4fe535491802879fe45946748fc
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/helper.c
Log Message:
-----------
target/s390x: Rename get_phys_page_debug() @vaddr argument as @v_addr
In order to use the %vaddr type in s390_cpu_get_phys_page_debug()
in the next commit, rename the argument @vaddr -> @v_addr.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Commit: 1ba04414cce79d14c32407f89c3410438c54b80b
https://github.com/qemu/qemu/commit/1ba04414cce79d14c32407f89c3410438c54b80b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/helper.c
M target/s390x/mmu_helper.c
M target/s390x/s390x-internal.h
M target/s390x/tcg/excp_helper.c
Log Message:
-----------
target/s390x: Replace %target_ulong -> %vaddr where appropriate
Use the %vaddr type for virtual addresses.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Commit: 4a41b5ecc5e23fe0d4284ddcd6695fc90ab3e22b
https://github.com/qemu/qemu/commit/4a41b5ecc5e23fe0d4284ddcd6695fc90ab3e22b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/helper.c
M target/s390x/mmu_helper.c
M target/s390x/s390x-internal.h
M target/s390x/tcg/excp_helper.c
Log Message:
-----------
target/s390x: Replace %target_ulong -> %hwaddr where appropriate
Use the %hwaddr type for physical addresses.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Commit: e0abd3de7659a1e6e3ac1222eadb159623d1bc79
https://github.com/qemu/qemu/commit/e0abd3de7659a1e6e3ac1222eadb159623d1bc79
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/kvm/pv.h
M target/s390x/kvm/stubs.c
Log Message:
-----------
target/s390x: Un-inline KVM Protected Virtualization stubs
By removing the target-specific 'CONFIG_KVM' definition this
header can be used by files in meson common_ss[].
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Eric Farman <[email protected]>
Message-Id: <[email protected]>
Commit: 8d2fd8696527c8ccae49b74340010ac494503615
https://github.com/qemu/qemu/commit/8d2fd8696527c8ccae49b74340010ac494503615
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/kvm/stubs.c
Log Message:
-----------
target/s390x: Add more unreachable KVM stubs
Next patch will move s390x system objects from the target
specific source set to the common one. Unfortunately the
kvm_enabled() macro won't be evaluable at built-time
anymore. Add stubs for KVM symbols unreachable at runtime.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Thomas Huth <[email protected]>
Reviewed-by: Eric Farman <[email protected]>
Message-Id: <[email protected]>
Commit: dacb7a6510a8827d5932388b6f8d477478a43e02
https://github.com/qemu/qemu/commit/dacb7a6510a8827d5932388b6f8d477478a43e02
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/meson.build
M target/s390x/tcg/meson.build
Log Message:
-----------
target/s390x: Build system units in common source set
Except the ioinst.c file which uses the TARGET_PAGE_SIZE
definition in the ioinst_handle_chsc() method, all other
files in meson's s390x_system_ss[] source set don't use
any target-specific code. Moving them in the other
s390x_common_system_ss[] set to build as common objects
ensures these files won't use any target-specific API
such target_ulong / TARGET_PAGE_SIZE, thus forcing to use
the appropriate types instead (such vaddr, hwaddr, uint64_t,
...).
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Commit: ad429e3a38c68784c09f441fa570490e6f28b0d1
https://github.com/qemu/qemu/commit/ad429e3a38c68784c09f441fa570490e6f28b0d1
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Expand TCGv type as 64-bit target
The s390x target is a 64-bit one, so TCGv expands to TCGv_i64.
Use the latter which is already used about a hundred times in
this file, and is also more explicit.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Commit: b29c1d33a27c26f6324710395fc7fe86b376cb24
https://github.com/qemu/qemu/commit/b29c1d33a27c26f6324710395fc7fe86b376cb24
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Expand tcg_gen_qemu_ld/st_tl() as 64-bit target
The s390x target is a 64-bit one, so we have these expansions
in the "tcg/tcg-op.h" header:
. tcg_gen_qemu_ld_tl() -> tcg_gen_qemu_ld_i64()
. tcg_gen_qemu_st_tl() -> tcg_gen_qemu_st_i64()
Use the expanded form which is more explicit when a target
isn't built for different words size.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Commit: e9c3aafb5fc483434c4428fdb727abc6f44b5016
https://github.com/qemu/qemu/commit/e9c3aafb5fc483434c4428fdb727abc6f44b5016
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Expand tcg_global_mem_new() -> tcg_global_mem_new_i64()
The s390x target is a 64-bit one, so tcg_global_mem_new()
expands to tcg_global_mem_new_i64(). Use the latter which
is more explicit.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Commit: 3ca2cadd392ade9714d202cb1a4daba0516d594c
https://github.com/qemu/qemu/commit/3ca2cadd392ade9714d202cb1a4daba0516d594c
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/arm/arm-qmp-cmds.c
M target/arm/kvm-stub.c
M target/arm/kvm.c
M target/arm/kvm_arm.h
M target/arm/meson.build
Log Message:
-----------
target/arm/arm-qmp-cmds.c: make compilation unit common
Move gic_cap_kvm_probe to target/arm/kvm.c to remove #ifdef CONFIG_KVM.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: f811e8ba6ce516b962182f5f3261b804e59d6c95
https://github.com/qemu/qemu/commit/f811e8ba6ce516b962182f5f3261b804e59d6c95
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/sparc/ldst_helper.c
Log Message:
-----------
target/sparc: Remove dubious swapping in LD_code() helper
Since the endianness is contained in %oi, cpu_ld*_code_mmu() has
already honored it. Swapping again makes no sense. Remove the
bswap() calls.
Fixes: 2786a3f8d3a ("Use GET_ASI_CODE for ASI_KERNELTXT / ASI_USERTXT")
Reported-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 136b1158094f6d61e8fa4a397d62982fa85f31ad
https://github.com/qemu/qemu/commit/136b1158094f6d61e8fa4a397d62982fa85f31ad
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Replace MO_TE -> MO_BE
We only build the SPARC targets using big endianness order,
therefore the MO_TE definitions expand to the big endian
one. Use the latter which is more explicit.
Mechanical change running:
$ sed -i -e s/MO_TE/MO_BE/ \
$(git grep -wl MO_TE target/sparc/)
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 3563f6093179fc023890c08337fde18e61d3bac0
https://github.com/qemu/qemu/commit/3563f6093179fc023890c08337fde18e61d3bac0
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M configs/targets/sparc-linux-user.mak
M configs/targets/sparc-softmmu.mak
M configs/targets/sparc32plus-linux-user.mak
M configs/targets/sparc64-linux-user.mak
M configs/targets/sparc64-softmmu.mak
Log Message:
-----------
configs/targets: Forbid SPARC to use legacy native endianness APIs
All SPARC-related binaries are buildable without a single
use of the legacy "native endian" API. Set the transitional
TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API definition to forbid
further uses of the legacy API.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 11eb2f873b55575c7ee1af3364917c1b231ab15b
https://github.com/qemu/qemu/commit/11eb2f873b55575c7ee1af3364917c1b231ab15b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/sparc/mmu_helper.c
Log Message:
-----------
target/sparc: Replace legacy st_phys() -> address_space_st()
Prefer the address_space_ld/st API over the legacy ld_phys()
because it allow checking for bus access fault.
get_physical_address() already accessed the PTE stored at
%pde_ptr and is going to update it. Assume the address space
is also writeable there. The SPARC v8 manual only mentions
faults (with error condition bits updated) in the READ path
but not on the WRITE (update) one.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 6172a4257e84ba5fc9b818ea7797d17bd730ada4
https://github.com/qemu/qemu/commit/6172a4257e84ba5fc9b818ea7797d17bd730ada4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M configs/targets/sparc-softmmu.mak
Log Message:
-----------
configs/targets: Restrict legacy ldst_phys() API on 32-bit SPARC target
Since we removed the last legacy uses of the legacy ldst_phys()
API, set the TARGET_NOT_USING_LEGACY_LDST_PHYS_API variable to
hide the legacy API to the qemu-system-sparc binary, avoiding
further API uses to creep in.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: c2e7579505bf62204d650bb3329d147d2df096bd
https://github.com/qemu/qemu/commit/c2e7579505bf62204d650bb3329d147d2df096bd
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target/i386/helper.c
M target/i386/tcg/system/misc_helper.c
Log Message:
-----------
target/i386: Use explicit little-endian LD/ST API
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change running:
$ for a in uw w l q; do \
sed -i -e "s/ld${a}_p(/ld${a}_le_p(/" \
$(git grep -wlE '(ld|st)u?[wlq]_p' target/i386/);
done
Coding style adapted manually.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 3f1926200822adca007258797cb9c0ce153e8729
https://github.com/qemu/qemu/commit/3f1926200822adca007258797cb9c0ce153e8729
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M hw/intc/apic.c
M hw/intc/ioapic.c
Log Message:
-----------
hw/intc: Mark x86-specific [IO]APIC peripherals as little-endian
These devices are only used by the x86 targets, which are
only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN
definition expand to DEVICE_LITTLE_ENDIAN (besides, the
DEVICE_BIG_ENDIAN case isn't tested). Simplify directly
using DEVICE_LITTLE_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 33f79f636f0ee94dc05ab474ae3f679f0ddf3a75
https://github.com/qemu/qemu/commit/33f79f636f0ee94dc05ab474ae3f679f0ddf3a75
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M hw/intc/ioapic.c
Log Message:
-----------
hw/intc/ioapic: Replace legacy st_phys() -> address_space_st()
Prefer the address_space_ld/st API over the legacy ld_phys()
because it allow checking for bus access fault. However the
IOAPIC datasheet (82093AA Order Number: 290566-001) doesn't
mention any fault occuring when the system bus (ISA bus) is
accessed. The ISA bus neither offer a way to signal recoverable
access faults. Therefore just inline the stl_le_phys() call,
not specifying any memory transaction attribute nor expecting
transation result, per the definition in
"system/memory_ldst_phys_endian.h.inc":
42 static inline void ST_PHYS(l)(ARG1_DECL, hwaddr addr, uint32_t val)
43 {
44 ADDRESS_SPACE_ST(l)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
45 }
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: a8b5e57635c80017034cf89225386b79d734294b
https://github.com/qemu/qemu/commit/a8b5e57635c80017034cf89225386b79d734294b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M configs/targets/i386-softmmu.mak
M configs/targets/x86_64-softmmu.mak
Log Message:
-----------
configs/targets: Restrict the legacy ldst_phys() API on x86 targets
The x86 targets don't use the legacy ldst_phys() API anymore.
Set the TARGET_NOT_USING_LEGACY_LDST_PHYS_API variable to hide
the legacy API to the x86 binaries, avoiding further API uses
to creep in.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 62822fc7e0f2d04cbbd08507509c9379af21f49b
https://github.com/qemu/qemu/commit/62822fc7e0f2d04cbbd08507509c9379af21f49b
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M MAINTAINERS
M configs/targets/or1k-linux-user.mak
M configs/targets/or1k-softmmu.mak
M hw/openrisc/Kconfig
M hw/openrisc/meson.build
M include/exec/poison.h
M include/system/arch_init.h
M include/user/abitypes.h
M linux-user/meson.build
R linux-user/openrisc/cpu_loop.c
R linux-user/openrisc/elfload.c
R linux-user/openrisc/meson.build
R linux-user/openrisc/signal.c
R linux-user/openrisc/sockbits.h
R linux-user/openrisc/syscall.tbl
R linux-user/openrisc/syscallhdr.sh
R linux-user/openrisc/target_cpu.h
R linux-user/openrisc/target_elf.h
R linux-user/openrisc/target_errno_defs.h
R linux-user/openrisc/target_fcntl.h
R linux-user/openrisc/target_mman.h
R linux-user/openrisc/target_prctl.h
R linux-user/openrisc/target_proc.h
R linux-user/openrisc/target_ptrace.h
R linux-user/openrisc/target_resource.h
R linux-user/openrisc/target_signal.h
R linux-user/openrisc/target_structs.h
R linux-user/openrisc/target_syscall.h
R linux-user/openrisc/termbits.h
A linux-user/or1k/cpu_loop.c
A linux-user/or1k/elfload.c
A linux-user/or1k/meson.build
A linux-user/or1k/signal.c
A linux-user/or1k/sockbits.h
A linux-user/or1k/syscall.tbl
A linux-user/or1k/syscallhdr.sh
A linux-user/or1k/target_cpu.h
A linux-user/or1k/target_elf.h
A linux-user/or1k/target_errno_defs.h
A linux-user/or1k/target_fcntl.h
A linux-user/or1k/target_mman.h
A linux-user/or1k/target_prctl.h
A linux-user/or1k/target_proc.h
A linux-user/or1k/target_ptrace.h
A linux-user/or1k/target_resource.h
A linux-user/or1k/target_signal.h
A linux-user/or1k/target_structs.h
A linux-user/or1k/target_syscall.h
A linux-user/or1k/termbits.h
M linux-user/syscall_defs.h
M system/qdev-monitor.c
M target/Kconfig
M target/meson.build
R target/openrisc/Kconfig
R target/openrisc/cpu-param.h
R target/openrisc/cpu-qom.h
R target/openrisc/cpu.c
R target/openrisc/cpu.h
R target/openrisc/disas.c
R target/openrisc/exception.c
R target/openrisc/exception.h
R target/openrisc/exception_helper.c
R target/openrisc/fpu_helper.c
R target/openrisc/gdbstub.c
R target/openrisc/helper.h
R target/openrisc/insns.decode
R target/openrisc/interrupt.c
R target/openrisc/interrupt_helper.c
R target/openrisc/machine.c
R target/openrisc/meson.build
R target/openrisc/mmu.c
R target/openrisc/sys_helper.c
R target/openrisc/translate.c
A target/or1k/Kconfig
A target/or1k/cpu-param.h
A target/or1k/cpu-qom.h
A target/or1k/cpu.c
A target/or1k/cpu.h
A target/or1k/disas.c
A target/or1k/exception.c
A target/or1k/exception.h
A target/or1k/exception_helper.c
A target/or1k/fpu_helper.c
A target/or1k/gdbstub.c
A target/or1k/helper.h
A target/or1k/insns.decode
A target/or1k/interrupt.c
A target/or1k/interrupt_helper.c
A target/or1k/machine.c
A target/or1k/meson.build
A target/or1k/mmu.c
A target/or1k/sys_helper.c
A target/or1k/translate.c
Log Message:
-----------
target/or1k: Rename from openrisc
This is the minimal change beginning with TARGET_ARCH in
configs/targets/or1k-* from openrisc to or1k, then adjust
TARGET_OR1K, QEMU_ARCH_OR1K, directory names,
and meson.build to match.
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 8cbc31d341cb4cc1bc3ac0e22522c163161e0c92
https://github.com/qemu/qemu/commit/8cbc31d341cb4cc1bc3ac0e22522c163161e0c92
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M MAINTAINERS
M hw/openrisc/boot.c
M hw/openrisc/openrisc_sim.c
M hw/openrisc/virt.c
R include/hw/openrisc/boot.h
A include/hw/or1k/boot.h
Log Message:
-----------
include/hw/or1k: Rename from openrisc
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Stafford Horne <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 44967f9422dde879c4ec100c54d44ce887f3fa4a
https://github.com/qemu/qemu/commit/44967f9422dde879c4ec100c54d44ce887f3fa4a
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M MAINTAINERS
M hw/Kconfig
M hw/meson.build
R hw/openrisc/Kconfig
R hw/openrisc/boot.c
R hw/openrisc/cputimer.c
R hw/openrisc/meson.build
R hw/openrisc/openrisc_sim.c
R hw/openrisc/virt.c
A hw/or1k/Kconfig
A hw/or1k/boot.c
A hw/or1k/cputimer.c
A hw/or1k/meson.build
A hw/or1k/openrisc_sim.c
A hw/or1k/virt.c
Log Message:
-----------
hw/or1k: Rename from openrisc
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: e4dad5f55f52752001e9c11702ff77d85e874663
https://github.com/qemu/qemu/commit/e4dad5f55f52752001e9c11702ff77d85e874663
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M MAINTAINERS
R tests/tcg/openrisc/Makefile
R tests/tcg/openrisc/test_add.c
R tests/tcg/openrisc/test_addc.c
R tests/tcg/openrisc/test_addi.c
R tests/tcg/openrisc/test_addic.c
R tests/tcg/openrisc/test_and_or.c
R tests/tcg/openrisc/test_bf.c
R tests/tcg/openrisc/test_bnf.c
R tests/tcg/openrisc/test_div.c
R tests/tcg/openrisc/test_divu.c
R tests/tcg/openrisc/test_extx.c
R tests/tcg/openrisc/test_fx.c
R tests/tcg/openrisc/test_j.c
R tests/tcg/openrisc/test_jal.c
R tests/tcg/openrisc/test_lf_add.c
R tests/tcg/openrisc/test_lf_div.c
R tests/tcg/openrisc/test_lf_eqs.c
R tests/tcg/openrisc/test_lf_ges.c
R tests/tcg/openrisc/test_lf_gts.c
R tests/tcg/openrisc/test_lf_les.c
R tests/tcg/openrisc/test_lf_lts.c
R tests/tcg/openrisc/test_lf_mul.c
R tests/tcg/openrisc/test_lf_nes.c
R tests/tcg/openrisc/test_lf_rem.c
R tests/tcg/openrisc/test_lf_sub.c
R tests/tcg/openrisc/test_logic.c
R tests/tcg/openrisc/test_lx.c
R tests/tcg/openrisc/test_movhi.c
R tests/tcg/openrisc/test_mul.c
R tests/tcg/openrisc/test_muli.c
R tests/tcg/openrisc/test_mulu.c
R tests/tcg/openrisc/test_sfeq.c
R tests/tcg/openrisc/test_sfeqi.c
R tests/tcg/openrisc/test_sfges.c
R tests/tcg/openrisc/test_sfgesi.c
R tests/tcg/openrisc/test_sfgeu.c
R tests/tcg/openrisc/test_sfgeui.c
R tests/tcg/openrisc/test_sfgts.c
R tests/tcg/openrisc/test_sfgtsi.c
R tests/tcg/openrisc/test_sfgtu.c
R tests/tcg/openrisc/test_sfgtui.c
R tests/tcg/openrisc/test_sfles.c
R tests/tcg/openrisc/test_sflesi.c
R tests/tcg/openrisc/test_sfleu.c
R tests/tcg/openrisc/test_sfleui.c
R tests/tcg/openrisc/test_sflts.c
R tests/tcg/openrisc/test_sfltsi.c
R tests/tcg/openrisc/test_sfltu.c
R tests/tcg/openrisc/test_sfltui.c
R tests/tcg/openrisc/test_sfne.c
R tests/tcg/openrisc/test_sfnei.c
R tests/tcg/openrisc/test_sub.c
A tests/tcg/or1k/Makefile
A tests/tcg/or1k/test_add.c
A tests/tcg/or1k/test_addc.c
A tests/tcg/or1k/test_addi.c
A tests/tcg/or1k/test_addic.c
A tests/tcg/or1k/test_and_or.c
A tests/tcg/or1k/test_bf.c
A tests/tcg/or1k/test_bnf.c
A tests/tcg/or1k/test_div.c
A tests/tcg/or1k/test_divu.c
A tests/tcg/or1k/test_extx.c
A tests/tcg/or1k/test_fx.c
A tests/tcg/or1k/test_j.c
A tests/tcg/or1k/test_jal.c
A tests/tcg/or1k/test_lf_add.c
A tests/tcg/or1k/test_lf_div.c
A tests/tcg/or1k/test_lf_eqs.c
A tests/tcg/or1k/test_lf_ges.c
A tests/tcg/or1k/test_lf_gts.c
A tests/tcg/or1k/test_lf_les.c
A tests/tcg/or1k/test_lf_lts.c
A tests/tcg/or1k/test_lf_mul.c
A tests/tcg/or1k/test_lf_nes.c
A tests/tcg/or1k/test_lf_rem.c
A tests/tcg/or1k/test_lf_sub.c
A tests/tcg/or1k/test_logic.c
A tests/tcg/or1k/test_lx.c
A tests/tcg/or1k/test_movhi.c
A tests/tcg/or1k/test_mul.c
A tests/tcg/or1k/test_muli.c
A tests/tcg/or1k/test_mulu.c
A tests/tcg/or1k/test_sfeq.c
A tests/tcg/or1k/test_sfeqi.c
A tests/tcg/or1k/test_sfges.c
A tests/tcg/or1k/test_sfgesi.c
A tests/tcg/or1k/test_sfgeu.c
A tests/tcg/or1k/test_sfgeui.c
A tests/tcg/or1k/test_sfgts.c
A tests/tcg/or1k/test_sfgtsi.c
A tests/tcg/or1k/test_sfgtu.c
A tests/tcg/or1k/test_sfgtui.c
A tests/tcg/or1k/test_sfles.c
A tests/tcg/or1k/test_sflesi.c
A tests/tcg/or1k/test_sfleu.c
A tests/tcg/or1k/test_sfleui.c
A tests/tcg/or1k/test_sflts.c
A tests/tcg/or1k/test_sfltsi.c
A tests/tcg/or1k/test_sfltu.c
A tests/tcg/or1k/test_sfltui.c
A tests/tcg/or1k/test_sfne.c
A tests/tcg/or1k/test_sfnei.c
A tests/tcg/or1k/test_sub.c
Log Message:
-----------
tests/tcg/or1k: Rename from openrisc
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Stafford Horne <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 322963969e1f282fa5412f8be0afa13b3c473d6c
https://github.com/qemu/qemu/commit/322963969e1f282fa5412f8be0afa13b3c473d6c
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M MAINTAINERS
R docs/system/openrisc/cpu-features.rst
R docs/system/openrisc/emulation.rst
R docs/system/openrisc/or1k-sim.rst
R docs/system/openrisc/virt.rst
A docs/system/or1k/cpu-features.rst
A docs/system/or1k/emulation.rst
A docs/system/or1k/or1k-sim.rst
A docs/system/or1k/virt.rst
R docs/system/target-openrisc.rst
A docs/system/target-or1k.rst
M docs/system/targets.rst
Log Message:
-----------
docs/system/or1k: Rename from openrisc
Also rename docs/system/target-or1k.rst from target-openrisc.rst,
and update all toctree entries to match.
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Stafford Horne <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: afc63fb06794cc2b5409e0f98030796497311876
https://github.com/qemu/qemu/commit/afc63fb06794cc2b5409e0f98030796497311876
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M MAINTAINERS
M hw/or1k/meson.build
R hw/or1k/openrisc_sim.c
A hw/or1k/or1k-sim.c
Log Message:
-----------
hw/or1k: Rename or1k-sim.c from openrisc_sim.c
Match the filename to the machine type: or1k-sim.
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Stafford Horne <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 3fdc58a30bfb268e2e7722254f060217bb1e7b51
https://github.com/qemu/qemu/commit/3fdc58a30bfb268e2e7722254f060217bb1e7b51
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M qapi/machine.json
Log Message:
-----------
qapi: Add hexagon to SysEmuTarget
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Brian Cain <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: f87f7e145d63f93315e0f0e00fb9ba0b6ee8570f
https://github.com/qemu/qemu/commit/f87f7e145d63f93315e0f0e00fb9ba0b6ee8570f
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M meson.build
Log Message:
-----------
meson: Add TARGET_ARCH to config_target_data
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: e934c624f32f6f44f427d73a2e6a67e983a02ae6
https://github.com/qemu/qemu/commit/e934c624f32f6f44f427d73a2e6a67e983a02ae6
Author: Richard Henderson <[email protected]>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M target-info-stub.c
M target-info.c
Log Message:
-----------
target-info: Statically initialize target_arch
Use TARGET_ARCH and token pasting to initialize
target_arch from SYS_EMU_TARGET_*.
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 5cf9a035aa11f8ddc2fd459703fc9b0d9c3c58bb
https://github.com/qemu/qemu/commit/5cf9a035aa11f8ddc2fd459703fc9b0d9c3c58bb
Author: Jiajie Chen <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
Log Message:
-----------
target/loongarch: Require atomics to be aligned
Currently, all atomic instructions in LoongArch require the address to
be aligned.
Signed-off-by: Jiajie Chen <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 2276261a01fbf0c08d491c1f8312b90a5f7373c3
https://github.com/qemu/qemu/commit/2276261a01fbf0c08d491c1f8312b90a5f7373c3
Author: Jiajie Chen <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/disas.c
M target/loongarch/insns.decode
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add am{swap/add}[_db].{b/h}
The new instructions are introduced in LoongArch v1.1:
- amswap.b
- amswap.h
- amadd.b
- amadd.h
- amswap_db.b
- amswap_db.h
- amadd_db.b
- amadd_db.h
The instructions are gated by CPUCFG2.LAM_BH.
Signed-off-by: Jiajie Chen <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: c1db8eb023f952e6065e479171f091efb255ac49
https://github.com/qemu/qemu/commit/c1db8eb023f952e6065e479171f091efb255ac49
Author: Jiajie Chen <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/disas.c
M target/loongarch/insns.decode
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add amcas[_db].{b/h/w/d}
The new instructions are introduced in LoongArch v1.1:
- amcas.b
- amcas.h
- amcas.w
- amcas.d
- amcas_db.b
- amcas_db.h
- amcas_db.w
- amcas_db.d
The new instructions are gated by CPUCFG2.LAMCAS.
Signed-off-by: Jiajie Chen <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: ebe521ad930b04a2cb8b0e98011751b12e84a653
https://github.com/qemu/qemu/commit/ebe521ad930b04a2cb8b0e98011751b12e84a653
Author: Jiajie Chen <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/disas.c
M target/loongarch/insns.decode
M target/loongarch/tcg/insn_trans/trans_farith.c.inc
M target/loongarch/tcg/insn_trans/trans_vec.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add estimated reciprocal instructions
Add the following new instructions in LoongArch v1.1:
- frecipe.s
- frecipe.d
- frsqrte.s
- frsqrte.d
- vfrecipe.s
- vfrecipe.d
- vfrsqrte.s
- vfrsqrte.d
- xvfrecipe.s
- xvfrecipe.d
- xvfrsqrte.s
- xvfrsqrte.d
They are guarded by CPUCFG2.FRECIPE. Altought the instructions allow
implementation to improve performance by reducing precision, we use the
existing softfloat implementation.
Signed-off-by: Jiajie Chen <[email protected]>
Acked-by: Richard Henderson <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 6e533aca52358dae53d6f4b9db00afb4e50b1e80
https://github.com/qemu/qemu/commit/6e533aca52358dae53d6f4b9db00afb4e50b1e80
Author: Jiajie Chen <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/disas.c
M target/loongarch/insns.decode
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add llacq/screl instructions
Add the following instructions in LoongArch v1.1:
- llacq.w
- screl.w
- llacq.d
- screl.d
They are guarded by CPUCFG2.LLACQ_SCREL.
Signed-off-by: Jiajie Chen <[email protected]>
Co-developed-by: Richard Henderson <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 424227ff546b8d90471b2baea0c822fabb24df97
https://github.com/qemu/qemu/commit/424227ff546b8d90471b2baea0c822fabb24df97
Author: Jiajie Chen <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/disas.c
M target/loongarch/insns.decode
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/tcg/insn_trans/trans_memory.c.inc
M target/loongarch/tcg/translate.c
M target/loongarch/translate.h
Log Message:
-----------
target/loongarch: Add sc.q instructions
Add the sc.q instruction in LoongArch v1.1, guarded by CPUCFG2.SCQ. It
is implemented by reading 128bit data (llval + llval_high) in ll.d when
aligned to 16B boundary, and cmpxchg 128bit in sc.q. If ld.d
matches the higher part of the 128bit, its data is taken from
llval_high.
Expected assembly sequence:
ll.d lo, base, 0
ld.d hi, base, 8
sc.q lo, hi, base
Signed-off-by: Jiajie Chen <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 59c8adc2830342c2cff5fe8867191d0e166abb29
https://github.com/qemu/qemu/commit/59c8adc2830342c2cff5fe8867191d0e166abb29
Author: Jiajie Chen <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Add LA v1.1 instructions to max cpu
Add LA v1.1 new instructinos to max cpu by enabling new features in
CPUCFG2.
Signed-off-by: Jiajie Chen <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 37daf4ec82411f7c65b3287cf6b2c27a128cec3b
https://github.com/qemu/qemu/commit/37daf4ec82411f7c65b3287cf6b2c27a128cec3b
Author: Peter Maydell <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M MAINTAINERS
M configs/targets/i386-softmmu.mak
M configs/targets/or1k-linux-user.mak
M configs/targets/or1k-softmmu.mak
M configs/targets/sparc-linux-user.mak
M configs/targets/sparc-softmmu.mak
M configs/targets/sparc32plus-linux-user.mak
M configs/targets/sparc64-linux-user.mak
M configs/targets/sparc64-softmmu.mak
M configs/targets/x86_64-softmmu.mak
R docs/system/openrisc/cpu-features.rst
R docs/system/openrisc/emulation.rst
R docs/system/openrisc/or1k-sim.rst
R docs/system/openrisc/virt.rst
A docs/system/or1k/cpu-features.rst
A docs/system/or1k/emulation.rst
A docs/system/or1k/or1k-sim.rst
A docs/system/or1k/virt.rst
R docs/system/target-openrisc.rst
A docs/system/target-or1k.rst
M docs/system/targets.rst
M hw/Kconfig
M hw/intc/apic.c
M hw/intc/ioapic.c
M hw/meson.build
R hw/openrisc/Kconfig
R hw/openrisc/boot.c
R hw/openrisc/cputimer.c
R hw/openrisc/meson.build
R hw/openrisc/openrisc_sim.c
R hw/openrisc/virt.c
A hw/or1k/Kconfig
A hw/or1k/boot.c
A hw/or1k/cputimer.c
A hw/or1k/meson.build
A hw/or1k/or1k-sim.c
A hw/or1k/virt.c
M include/exec/poison.h
R include/hw/openrisc/boot.h
A include/hw/or1k/boot.h
M include/system/arch_init.h
M include/user/abitypes.h
M linux-user/meson.build
R linux-user/openrisc/cpu_loop.c
R linux-user/openrisc/elfload.c
R linux-user/openrisc/meson.build
R linux-user/openrisc/signal.c
R linux-user/openrisc/sockbits.h
R linux-user/openrisc/syscall.tbl
R linux-user/openrisc/syscallhdr.sh
R linux-user/openrisc/target_cpu.h
R linux-user/openrisc/target_elf.h
R linux-user/openrisc/target_errno_defs.h
R linux-user/openrisc/target_fcntl.h
R linux-user/openrisc/target_mman.h
R linux-user/openrisc/target_prctl.h
R linux-user/openrisc/target_proc.h
R linux-user/openrisc/target_ptrace.h
R linux-user/openrisc/target_resource.h
R linux-user/openrisc/target_signal.h
R linux-user/openrisc/target_structs.h
R linux-user/openrisc/target_syscall.h
R linux-user/openrisc/termbits.h
A linux-user/or1k/cpu_loop.c
A linux-user/or1k/elfload.c
A linux-user/or1k/meson.build
A linux-user/or1k/signal.c
A linux-user/or1k/sockbits.h
A linux-user/or1k/syscall.tbl
A linux-user/or1k/syscallhdr.sh
A linux-user/or1k/target_cpu.h
A linux-user/or1k/target_elf.h
A linux-user/or1k/target_errno_defs.h
A linux-user/or1k/target_fcntl.h
A linux-user/or1k/target_mman.h
A linux-user/or1k/target_prctl.h
A linux-user/or1k/target_proc.h
A linux-user/or1k/target_ptrace.h
A linux-user/or1k/target_resource.h
A linux-user/or1k/target_signal.h
A linux-user/or1k/target_structs.h
A linux-user/or1k/target_syscall.h
A linux-user/or1k/termbits.h
M linux-user/syscall_defs.h
M meson.build
M qapi/machine.json
M system/qdev-monitor.c
M target-info-stub.c
M target-info.c
M target/Kconfig
M target/arm/arm-qmp-cmds.c
M target/arm/kvm-stub.c
M target/arm/kvm.c
M target/arm/kvm_arm.h
M target/arm/meson.build
M target/i386/helper.c
M target/i386/tcg/system/misc_helper.c
M target/meson.build
R target/openrisc/Kconfig
R target/openrisc/cpu-param.h
R target/openrisc/cpu-qom.h
R target/openrisc/cpu.c
R target/openrisc/cpu.h
R target/openrisc/disas.c
R target/openrisc/exception.c
R target/openrisc/exception.h
R target/openrisc/exception_helper.c
R target/openrisc/fpu_helper.c
R target/openrisc/gdbstub.c
R target/openrisc/helper.h
R target/openrisc/insns.decode
R target/openrisc/interrupt.c
R target/openrisc/interrupt_helper.c
R target/openrisc/machine.c
R target/openrisc/meson.build
R target/openrisc/mmu.c
R target/openrisc/sys_helper.c
R target/openrisc/translate.c
A target/or1k/Kconfig
A target/or1k/cpu-param.h
A target/or1k/cpu-qom.h
A target/or1k/cpu.c
A target/or1k/cpu.h
A target/or1k/disas.c
A target/or1k/exception.c
A target/or1k/exception.h
A target/or1k/exception_helper.c
A target/or1k/fpu_helper.c
A target/or1k/gdbstub.c
A target/or1k/helper.h
A target/or1k/insns.decode
A target/or1k/interrupt.c
A target/or1k/interrupt_helper.c
A target/or1k/machine.c
A target/or1k/meson.build
A target/or1k/mmu.c
A target/or1k/sys_helper.c
A target/or1k/translate.c
M target/s390x/helper.c
M target/s390x/kvm/pv.h
M target/s390x/kvm/stubs.c
M target/s390x/meson.build
M target/s390x/mmu_helper.c
M target/s390x/s390x-internal.h
M target/s390x/tcg/excp_helper.c
M target/s390x/tcg/meson.build
M target/s390x/tcg/translate.c
M target/sparc/ldst_helper.c
M target/sparc/mmu_helper.c
M target/sparc/translate.c
M tests/functional/riscv64/test_boston.py
R tests/tcg/openrisc/Makefile
R tests/tcg/openrisc/test_add.c
R tests/tcg/openrisc/test_addc.c
R tests/tcg/openrisc/test_addi.c
R tests/tcg/openrisc/test_addic.c
R tests/tcg/openrisc/test_and_or.c
R tests/tcg/openrisc/test_bf.c
R tests/tcg/openrisc/test_bnf.c
R tests/tcg/openrisc/test_div.c
R tests/tcg/openrisc/test_divu.c
R tests/tcg/openrisc/test_extx.c
R tests/tcg/openrisc/test_fx.c
R tests/tcg/openrisc/test_j.c
R tests/tcg/openrisc/test_jal.c
R tests/tcg/openrisc/test_lf_add.c
R tests/tcg/openrisc/test_lf_div.c
R tests/tcg/openrisc/test_lf_eqs.c
R tests/tcg/openrisc/test_lf_ges.c
R tests/tcg/openrisc/test_lf_gts.c
R tests/tcg/openrisc/test_lf_les.c
R tests/tcg/openrisc/test_lf_lts.c
R tests/tcg/openrisc/test_lf_mul.c
R tests/tcg/openrisc/test_lf_nes.c
R tests/tcg/openrisc/test_lf_rem.c
R tests/tcg/openrisc/test_lf_sub.c
R tests/tcg/openrisc/test_logic.c
R tests/tcg/openrisc/test_lx.c
R tests/tcg/openrisc/test_movhi.c
R tests/tcg/openrisc/test_mul.c
R tests/tcg/openrisc/test_muli.c
R tests/tcg/openrisc/test_mulu.c
R tests/tcg/openrisc/test_sfeq.c
R tests/tcg/openrisc/test_sfeqi.c
R tests/tcg/openrisc/test_sfges.c
R tests/tcg/openrisc/test_sfgesi.c
R tests/tcg/openrisc/test_sfgeu.c
R tests/tcg/openrisc/test_sfgeui.c
R tests/tcg/openrisc/test_sfgts.c
R tests/tcg/openrisc/test_sfgtsi.c
R tests/tcg/openrisc/test_sfgtu.c
R tests/tcg/openrisc/test_sfgtui.c
R tests/tcg/openrisc/test_sfles.c
R tests/tcg/openrisc/test_sflesi.c
R tests/tcg/openrisc/test_sfleu.c
R tests/tcg/openrisc/test_sfleui.c
R tests/tcg/openrisc/test_sflts.c
R tests/tcg/openrisc/test_sfltsi.c
R tests/tcg/openrisc/test_sfltu.c
R tests/tcg/openrisc/test_sfltui.c
R tests/tcg/openrisc/test_sfne.c
R tests/tcg/openrisc/test_sfnei.c
R tests/tcg/openrisc/test_sub.c
A tests/tcg/or1k/Makefile
A tests/tcg/or1k/test_add.c
A tests/tcg/or1k/test_addc.c
A tests/tcg/or1k/test_addi.c
A tests/tcg/or1k/test_addic.c
A tests/tcg/or1k/test_and_or.c
A tests/tcg/or1k/test_bf.c
A tests/tcg/or1k/test_bnf.c
A tests/tcg/or1k/test_div.c
A tests/tcg/or1k/test_divu.c
A tests/tcg/or1k/test_extx.c
A tests/tcg/or1k/test_fx.c
A tests/tcg/or1k/test_j.c
A tests/tcg/or1k/test_jal.c
A tests/tcg/or1k/test_lf_add.c
A tests/tcg/or1k/test_lf_div.c
A tests/tcg/or1k/test_lf_eqs.c
A tests/tcg/or1k/test_lf_ges.c
A tests/tcg/or1k/test_lf_gts.c
A tests/tcg/or1k/test_lf_les.c
A tests/tcg/or1k/test_lf_lts.c
A tests/tcg/or1k/test_lf_mul.c
A tests/tcg/or1k/test_lf_nes.c
A tests/tcg/or1k/test_lf_rem.c
A tests/tcg/or1k/test_lf_sub.c
A tests/tcg/or1k/test_logic.c
A tests/tcg/or1k/test_lx.c
A tests/tcg/or1k/test_movhi.c
A tests/tcg/or1k/test_mul.c
A tests/tcg/or1k/test_muli.c
A tests/tcg/or1k/test_mulu.c
A tests/tcg/or1k/test_sfeq.c
A tests/tcg/or1k/test_sfeqi.c
A tests/tcg/or1k/test_sfges.c
A tests/tcg/or1k/test_sfgesi.c
A tests/tcg/or1k/test_sfgeu.c
A tests/tcg/or1k/test_sfgeui.c
A tests/tcg/or1k/test_sfgts.c
A tests/tcg/or1k/test_sfgtsi.c
A tests/tcg/or1k/test_sfgtu.c
A tests/tcg/or1k/test_sfgtui.c
A tests/tcg/or1k/test_sfles.c
A tests/tcg/or1k/test_sflesi.c
A tests/tcg/or1k/test_sfleu.c
A tests/tcg/or1k/test_sfleui.c
A tests/tcg/or1k/test_sflts.c
A tests/tcg/or1k/test_sfltsi.c
A tests/tcg/or1k/test_sfltu.c
A tests/tcg/or1k/test_sfltui.c
A tests/tcg/or1k/test_sfne.c
A tests/tcg/or1k/test_sfnei.c
A tests/tcg/or1k/test_sub.c
Log Message:
-----------
Merge tag 'single-binary-20260206' of https://github.com/philmd/qemu into
staging
Various patches related to single binary effort:
- Reduce RISC-V Boston tests
- Prohibit target_ulong / TARGET_PAGE_SIZE uses on s390x target
- Build target/arm/arm-qmp-cmds once
- Forbid legacy native endianness & ld/st_phys APIs on SPARC targets
- Forbid legacy ld/st_phys APIs on x86 targets
- Rename OpenRISC -> or1k
- Avoid QAPI parsing in target_arch()
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# gpg: Signature made Mon Feb 9 19:55:08 2026 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <[email protected]>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'single-binary-20260206' of https://github.com/philmd/qemu: (30 commits)
target-info: Statically initialize target_arch
meson: Add TARGET_ARCH to config_target_data
qapi: Add hexagon to SysEmuTarget
hw/or1k: Rename or1k-sim.c from openrisc_sim.c
docs/system/or1k: Rename from openrisc
tests/tcg/or1k: Rename from openrisc
hw/or1k: Rename from openrisc
include/hw/or1k: Rename from openrisc
target/or1k: Rename from openrisc
configs/targets: Restrict the legacy ldst_phys() API on x86 targets
hw/intc/ioapic: Replace legacy st_phys() -> address_space_st()
hw/intc: Mark x86-specific [IO]APIC peripherals as little-endian
target/i386: Use explicit little-endian LD/ST API
configs/targets: Restrict legacy ldst_phys() API on 32-bit SPARC target
target/sparc: Replace legacy st_phys() -> address_space_st()
configs/targets: Forbid SPARC to use legacy native endianness APIs
target/sparc: Replace MO_TE -> MO_BE
target/sparc: Remove dubious swapping in LD_code() helper
target/arm/arm-qmp-cmds.c: make compilation unit common
target/s390x: Expand tcg_global_mem_new() -> tcg_global_mem_new_i64()
...
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0b91040d23dc8820724a60c811223b777f3bc6b7
https://github.com/qemu/qemu/commit/0b91040d23dc8820724a60c811223b777f3bc6b7
Author: Peter Maydell <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/disas.c
M target/loongarch/insns.decode
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/tcg/insn_trans/trans_farith.c.inc
M target/loongarch/tcg/insn_trans/trans_memory.c.inc
M target/loongarch/tcg/insn_trans/trans_vec.c.inc
M target/loongarch/tcg/translate.c
M target/loongarch/translate.h
Log Message:
-----------
Merge tag 'pull-loongarch-20260210' of https://github.com/gaosong715/qemu
into staging
pull-loongarch-2026-02-10
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# gpg: Signature made Tue Feb 10 02:49:28 2026 GMT
# gpg: using RSA key CA473C44D6A09C189A193FCD452B96852B268216
# gpg: Good signature from "Song Gao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: CA47 3C44 D6A0 9C18 9A19 3FCD 452B 9685 2B26 8216
* tag 'pull-loongarch-20260210' of https://github.com/gaosong715/qemu:
target/loongarch: Add LA v1.1 instructions to max cpu
target/loongarch: Add sc.q instructions
target/loongarch: Add llacq/screl instructions
target/loongarch: Add estimated reciprocal instructions
target/loongarch: Add amcas[_db].{b/h/w/d}
target/loongarch: Add am{swap/add}[_db].{b/h}
target/loongarch: Require atomics to be aligned
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/b3abdfa4862f...0b91040d23dc
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