Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: d30b420c9cc4a0fe6882c7e6db5795948fed0352
https://github.com/qemu/qemu/commit/d30b420c9cc4a0fe6882c7e6db5795948fed0352
Author: Sebastian Ott <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/arm/kvm-consts.h
Log Message:
-----------
target/arm/kvm: add constants for new PSCI versions
Add constants for PSCI version 1_2 and 1_3.
Signed-off-by: Sebastian Ott <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7ca22ae3e6e451d3aec3414d77d93d83ebd51cd9
https://github.com/qemu/qemu/commit/7ca22ae3e6e451d3aec3414d77d93d83ebd51cd9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M include/system/hw_accel.h
Log Message:
-----------
accel/system: Introduce hwaccel_enabled() helper
hwaccel_enabled() return whether any hardware accelerator
is enabled.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: eb1c60997c4dff601f3cc0d6a24918e2068cf3c9
https://github.com/qemu/qemu/commit/eb1c60997c4dff601f3cc0d6a24918e2068cf3c9
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
qtest: hw/arm: virt: skip ACPI test for IORT with GICv2
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5f834ccdcf372f0bb67651ec582aa903f45d0205
https://github.com/qemu/qemu/commit/5f834ccdcf372f0bb67651ec582aa903f45d0205
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw: arm: virt: rework MSI-X configuration
Introduce a -M msi= argument to be able to control MSI-X support independently
from ITS, as part of supporting GICv3 + GICv2m platforms.
Remove vms->its as it's no longer needed after that change.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2e1bb23b444ddf5204f4ea8d2852d52186d8c682
https://github.com/qemu/qemu/commit/2e1bb23b444ddf5204f4ea8d2852d52186d8c682
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M tests/data/acpi/aarch64/virt/IORT
M tests/data/acpi/aarch64/virt/IORT.smmuv3-dev
M tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: data: update AArch64 ACPI tables
After the previous commit introducing GICv3 + GICv2m configurations,
update the AArch64 ACPI tables for the GICv2 case.
Changes to the ACPI tables:
tests/data/acpi/aarch64/virt/IORT.dsl:
@@ -11,68 +11,49 @@
*/
[000h 0000 004h] Signature : "IORT" [IO Remapping Table]
-[004h 0004 004h] Table Length : 00000080
+[004h 0004 004h] Table Length : 00000054
[008h 0008 001h] Revision : 05
-[009h 0009 001h] Checksum : B1
+[009h 0009 001h] Checksum : 3C
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[018h 0024 004h] Oem Revision : 00000001
[01Ch 0028 004h] Asl Compiler ID : "BXPC"
[020h 0032 004h] Asl Compiler Revision : 00000001
-[024h 0036 004h] Node Count : 00000002
+[024h 0036 004h] Node Count : 00000001
[028h 0040 004h] Node Offset : 00000030
[02Ch 0044 004h] Reserved : 00000000
-[030h 0048 001h] Type : 00
-[031h 0049 002h] Length : 0018
-[033h 0051 001h] Revision : 01
+[030h 0048 001h] Type : 02
+[031h 0049 002h] Length : 0024
+[033h 0051 001h] Revision : 03
[034h 0052 004h] Identifier : 00000000
[038h 0056 004h] Mapping Count : 00000000
-[03Ch 0060 004h] Mapping Offset : 00000000
+[03Ch 0060 004h] Mapping Offset : 00000024
-[040h 0064 004h] ItsCount : 00000001
-[044h 0068 004h] Identifiers : 00000000
-
-[048h 0072 001h] Type : 02
-[049h 0073 002h] Length : 0038
-[04Bh 0075 001h] Revision : 03
-[04Ch 0076 004h] Identifier : 00000001
-[050h 0080 004h] Mapping Count : 00000001
-[054h 0084 004h] Mapping Offset : 00000024
-
-[058h 0088 008h] Memory Properties : [IORT Memory Access Properties]
-[058h 0088 004h] Cache Coherency : 00000001
-[05Ch 0092 001h] Hints (decoded below) : 00
+[040h 0064 008h] Memory Properties : [IORT Memory Access Properties]
+[040h 0064 004h] Cache Coherency : 00000001
+[044h 0068 001h] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
-[05Dh 0093 002h] Reserved : 0000
-[05Fh 0095 001h] Memory Flags (decoded below) : 03
+[045h 0069 002h] Reserved : 0000
+[047h 0071 001h] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
Ensured Coherency of Accesses : 0
-[060h 0096 004h] ATS Attribute : 00000000
-[064h 0100 004h] PCI Segment Number : 00000000
-[068h 0104 001h] Memory Size Limit : 40
-[069h 0105 002h] PASID Capabilities : 0000
-[06Bh 0107 001h] Reserved : 00
+[048h 0072 004h] ATS Attribute : 00000000
+[04Ch 0076 004h] PCI Segment Number : 00000000
+[050h 0080 001h] Memory Size Limit : 40
+[051h 0081 002h] PASID Capabilities : 0000
+[053h 0083 001h] Reserved : 00
-[06Ch 0108 004h] Input base : 00000000
-[070h 0112 004h] ID Count : 0000FFFF
-[074h 0116 004h] Output Base : 00000000
-[078h 0120 004h] Output Reference : 00000030
-[07Ch 0124 004h] Flags (decoded below) : 00000000
- Single Mapping : 0
+Raw Table Data: Length 84 (0x54)
-Raw Table Data: Length 128 (0x80)
-
- 0000: 49 4F 52 54 80 00 00 00 05 B1 42 4F 43 48 53 20 // IORT......BOCHS
+ 0000: 49 4F 52 54 54 00 00 00 05 3C 42 4F 43 48 53 20 // IORTT....<BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
- 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0040: 01 00 00 00 00 00 00 00 02 38 00 03 01 00 00 00 // .........8......
- 0050: 01 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$...........
- 0060: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@.......
- 0070: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
+ 0020: 01 00 00 00 01 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
+ 0030: 02 24 00 03 00 00 00 00 00 00 00 00 24 00 00 00 // .$..........$...
+ 0040: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................
+ 0050: 40 00 00 00 // @...
tests/data/acpi/aarch64/virt/IORT.smmuv3-dev.dsl:
@@ -11,164 +11,120 @@
*/
[000h 0000 004h] Signature : "IORT" [IO Remapping Table]
-[004h 0004 004h] Table Length : 0000016C
+[004h 0004 004h] Table Length : 00000104
[008h 0008 001h] Revision : 05
-[009h 0009 001h] Checksum : C8
+[009h 0009 001h] Checksum : 49
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[018h 0024 004h] Oem Revision : 00000001
[01Ch 0028 004h] Asl Compiler ID : "BXPC"
[020h 0032 004h] Asl Compiler Revision : 00000001
-[024h 0036 004h] Node Count : 00000004
+[024h 0036 004h] Node Count : 00000003
[028h 0040 004h] Node Offset : 00000030
[02Ch 0044 004h] Reserved : 00000000
-[030h 0048 001h] Type : 00
-[031h 0049 002h] Length : 0018
-[033h 0051 001h] Revision : 01
+[030h 0048 001h] Type : 04
+[031h 0049 002h] Length : 0044
+[033h 0051 001h] Revision : 04
[034h 0052 004h] Identifier : 00000000
[038h 0056 004h] Mapping Count : 00000000
[03Ch 0060 004h] Mapping Offset : 00000000
-[040h 0064 004h] ItsCount : 00000001
-[044h 0068 004h] Identifiers : 00000000
-
-[048h 0072 001h] Type : 04
-[049h 0073 002h] Length : 0058
-[04Bh 0075 001h] Revision : 04
-[04Ch 0076 004h] Identifier : 00000001
-[050h 0080 004h] Mapping Count : 00000001
-[054h 0084 004h] Mapping Offset : 00000044
-
-[058h 0088 008h] Base Address : 000000000C000000
-[060h 0096 004h] Flags (decoded below) : 00000001
+[040h 0064 008h] Base Address : 000000000C000000
+[048h 0072 004h] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
DeviceID Valid : 0
-[064h 0100 004h] Reserved : 00000000
-[068h 0104 008h] VATOS Address : 0000000000000000
-[070h 0112 004h] Model : 00000000
-[074h 0116 004h] Event GSIV : 00000090
-[078h 0120 004h] PRI GSIV : 00000091
-[07Ch 0124 004h] GERR GSIV : 00000093
-[080h 0128 004h] Sync GSIV : 00000092
-[084h 0132 004h] Proximity Domain : 00000000
-[088h 0136 004h] Device ID Mapping Index : 00000000
+[04Ch 0076 004h] Reserved : 00000000
+[050h 0080 008h] VATOS Address : 0000000000000000
+[058h 0088 004h] Model : 00000000
+[05Ch 0092 004h] Event GSIV : 00000090
+[060h 0096 004h] PRI GSIV : 00000091
+[064h 0100 004h] GERR GSIV : 00000093
+[068h 0104 004h] Sync GSIV : 00000092
+[06Ch 0108 004h] Proximity Domain : 00000000
+[070h 0112 004h] Device ID Mapping Index : 00000000
-[08Ch 0140 004h] Input base : 00000000
-[090h 0144 004h] ID Count : 0000FFFF
-[094h 0148 004h] Output Base : 00000000
-[098h 0152 004h] Output Reference : 00000030
-[09Ch 0156 004h] Flags (decoded below) : 00000000
- Single Mapping : 0
+[074h 0116 001h] Type : 04
+[075h 0117 002h] Length : 0044
+[077h 0119 001h] Revision : 04
+[078h 0120 004h] Identifier : 00000001
+[07Ch 0124 004h] Mapping Count : 00000000
+[080h 0128 004h] Mapping Offset : 00000000
-[0A0h 0160 001h] Type : 04
-[0A1h 0161 002h] Length : 0058
-[0A3h 0163 001h] Revision : 04
-[0A4h 0164 004h] Identifier : 00000002
-[0A8h 0168 004h] Mapping Count : 00000001
-[0ACh 0172 004h] Mapping Offset : 00000044
-
-[0B0h 0176 008h] Base Address : 000000000C020000
-[0B8h 0184 004h] Flags (decoded below) : 00000001
+[084h 0132 008h] Base Address : 000000000C020000
+[08Ch 0140 004h] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
DeviceID Valid : 0
-[0BCh 0188 004h] Reserved : 00000000
-[0C0h 0192 008h] VATOS Address : 0000000000000000
-[0C8h 0200 004h] Model : 00000000
-[0CCh 0204 004h] Event GSIV : 00000094
-[0D0h 0208 004h] PRI GSIV : 00000095
-[0D4h 0212 004h] GERR GSIV : 00000097
-[0D8h 0216 004h] Sync GSIV : 00000096
-[0DCh 0220 004h] Proximity Domain : 00000000
-[0E0h 0224 004h] Device ID Mapping Index : 00000000
+[090h 0144 004h] Reserved : 00000000
+[094h 0148 008h] VATOS Address : 0000000000000000
+[09Ch 0156 004h] Model : 00000000
+[0A0h 0160 004h] Event GSIV : 00000094
+[0A4h 0164 004h] PRI GSIV : 00000095
+[0A8h 0168 004h] GERR GSIV : 00000097
+[0ACh 0172 004h] Sync GSIV : 00000096
+[0B0h 0176 004h] Proximity Domain : 00000000
+[0B4h 0180 004h] Device ID Mapping Index : 00000000
-[0E4h 0228 004h] Input base : 00000000
-[0E8h 0232 004h] ID Count : 0000FFFF
-[0ECh 0236 004h] Output Base : 00000000
-[0F0h 0240 004h] Output Reference : 00000030
-[0F4h 0244 004h] Flags (decoded below) : 00000000
- Single Mapping : 0
+[0B8h 0184 001h] Type : 02
+[0B9h 0185 002h] Length : 004C
+[0BBh 0187 001h] Revision : 03
+[0BCh 0188 004h] Identifier : 00000002
+[0C0h 0192 004h] Mapping Count : 00000002
+[0C4h 0196 004h] Mapping Offset : 00000024
-[0F8h 0248 001h] Type : 02
-[0F9h 0249 002h] Length : 0074
-[0FBh 0251 001h] Revision : 03
-[0FCh 0252 004h] Identifier : 00000003
-[100h 0256 004h] Mapping Count : 00000004
-[104h 0260 004h] Mapping Offset : 00000024
-
-[108h 0264 008h] Memory Properties : [IORT Memory Access Properties]
-[108h 0264 004h] Cache Coherency : 00000001
-[10Ch 0268 001h] Hints (decoded below) : 00
+[0C8h 0200 008h] Memory Properties : [IORT Memory Access Properties]
+[0C8h 0200 004h] Cache Coherency : 00000001
+[0CCh 0204 001h] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
-[10Dh 0269 002h] Reserved : 0000
-[10Fh 0271 001h] Memory Flags (decoded below) : 03
+[0CDh 0205 002h] Reserved : 0000
+[0CFh 0207 001h] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
Ensured Coherency of Accesses : 0
-[110h 0272 004h] ATS Attribute : 00000000
-[114h 0276 004h] PCI Segment Number : 00000000
-[118h 0280 001h] Memory Size Limit : 40
-[119h 0281 002h] PASID Capabilities : 0000
-[11Bh 0283 001h] Reserved : 00
+[0D0h 0208 004h] ATS Attribute : 00000000
+[0D4h 0212 004h] PCI Segment Number : 00000000
+[0D8h 0216 001h] Memory Size Limit : 40
+[0D9h 0217 002h] PASID Capabilities : 0000
+[0DBh 0219 001h] Reserved : 00
-[11Ch 0284 004h] Input base : 00000000
-[120h 0288 004h] ID Count : 000001FF
-[124h 0292 004h] Output Base : 00000000
-[128h 0296 004h] Output Reference : 00000048
-[12Ch 0300 004h] Flags (decoded below) : 00000000
+[0DCh 0220 004h] Input base : 00000000
+[0E0h 0224 004h] ID Count : 000001FF
+[0E4h 0228 004h] Output Base : 00000000
+[0E8h 0232 004h] Output Reference : 00000030
+[0ECh 0236 004h] Flags (decoded below) : 00000000
Single Mapping : 0
-[130h 0304 004h] Input base : 00001000
-[134h 0308 004h] ID Count : 000000FF
-[138h 0312 004h] Output Base : 00001000
-[13Ch 0316 004h] Output Reference : 000000A0
-[140h 0320 004h] Flags (decoded below) : 00000000
+[0F0h 0240 004h] Input base : 00001000
+[0F4h 0244 004h] ID Count : 000000FF
+[0F8h 0248 004h] Output Base : 00001000
+[0FCh 0252 004h] Output Reference : 00000074
+[100h 0256 004h] Flags (decoded below) : 00000000
Single Mapping : 0
-[144h 0324 004h] Input base : 00000200
-[148h 0328 004h] ID Count : 00000DFF
-[14Ch 0332 004h] Output Base : 00000200
-[150h 0336 004h] Output Reference : 00000030
-[154h 0340 004h] Flags (decoded below) : 00000000
- Single Mapping : 0
+Raw Table Data: Length 260 (0x104)
-[158h 0344 004h] Input base : 00001100
-[15Ch 0348 004h] ID Count : 0000EEFF
-[160h 0352 004h] Output Base : 00001100
-[164h 0356 004h] Output Reference : 00000030
-[168h 0360 004h] Flags (decoded below) : 00000000
- Single Mapping : 0
-
-Raw Table Data: Length 364 (0x16C)
-
- 0000: 49 4F 52 54 6C 01 00 00 05 C8 42 4F 43 48 53 20 // IORTl.....BOCHS
+ 0000: 49 4F 52 54 04 01 00 00 05 49 42 4F 43 48 53 20 // IORT.....IBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 04 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
- 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X......
- 0050: 01 00 00 00 44 00 00 00 00 00 00 0C 00 00 00 00 // ....D...........
- 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0070: 00 00 00 00 90 00 00 00 91 00 00 00 93 00 00 00 // ................
- 0080: 92 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
- 00A0: 04 58 00 04 02 00 00 00 01 00 00 00 44 00 00 00 // .X..........D...
- 00B0: 00 00 02 0C 00 00 00 00 01 00 00 00 00 00 00 00 // ................
- 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 94 00 00 00 // ................
- 00D0: 95 00 00 00 97 00 00 00 96 00 00 00 00 00 00 00 // ................
- 00E0: 00 00 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 // ................
- 00F0: 30 00 00 00 00 00 00 00 02 74 00 03 03 00 00 00 // 0........t......
- 0100: 04 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$...........
- 0110: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@.......
- 0120: FF 01 00 00 00 00 00 00 48 00 00 00 00 00 00 00 // ........H.......
- 0130: 00 10 00 00 FF 00 00 00 00 10 00 00 A0 00 00 00 // ................
- 0140: 00 00 00 00 00 02 00 00 FF 0D 00 00 00 02 00 00 // ................
- 0150: 30 00 00 00 00 00 00 00 00 11 00 00 FF EE 00 00 // 0...............
- 0160: 00 11 00 00 30 00 00 00 00 00 00 00 // ....0.......
+ 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
+ 0030: 04 44 00 04 00 00 00 00 00 00 00 00 00 00 00 00 // .D..............
+ 0040: 00 00 00 0C 00 00 00 00 01 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 90 00 00 00 // ................
+ 0060: 91 00 00 00 93 00 00 00 92 00 00 00 00 00 00 00 // ................
+ 0070: 00 00 00 00 04 44 00 04 01 00 00 00 00 00 00 00 // .....D..........
+ 0080: 00 00 00 00 00 00 02 0C 00 00 00 00 01 00 00 00 // ................
+ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 94 00 00 00 95 00 00 00 97 00 00 00 96 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 02 4C 00 03 02 00 00 00 // .........L......
+ 00C0: 02 00 00 00 24 00 00 00 01 00 00 00 00 00 00 03 // ....$...........
+ 00D0: 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 // ........@.......
+ 00E0: FF 01 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
+ 00F0: 00 10 00 00 FF 00 00 00 00 10 00 00 74 00 00 00 // ............t...
+ 0100: 00 00 00 00 // ....
tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy.dsl:
@@ -11,129 +11,92 @@
*/
[000h 0000 004h] Signature : "IORT" [IO Remapping Table]
-[004h 0004 004h] Table Length : 00000114
+[004h 0004 004h] Table Length : 000000C0
[008h 0008 001h] Revision : 05
-[009h 0009 001h] Checksum : 4A
+[009h 0009 001h] Checksum : 1C
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[018h 0024 004h] Oem Revision : 00000001
[01Ch 0028 004h] Asl Compiler ID : "BXPC"
[020h 0032 004h] Asl Compiler Revision : 00000001
-[024h 0036 004h] Node Count : 00000003
+[024h 0036 004h] Node Count : 00000002
[028h 0040 004h] Node Offset : 00000030
[02Ch 0044 004h] Reserved : 00000000
-[030h 0048 001h] Type : 00
-[031h 0049 002h] Length : 0018
-[033h 0051 001h] Revision : 01
+[030h 0048 001h] Type : 04
+[031h 0049 002h] Length : 0044
+[033h 0051 001h] Revision : 04
[034h 0052 004h] Identifier : 00000000
[038h 0056 004h] Mapping Count : 00000000
[03Ch 0060 004h] Mapping Offset : 00000000
-[040h 0064 004h] ItsCount : 00000001
-[044h 0068 004h] Identifiers : 00000000
-
-[048h 0072 001h] Type : 04
-[049h 0073 002h] Length : 0058
-[04Bh 0075 001h] Revision : 04
-[04Ch 0076 004h] Identifier : 00000001
-[050h 0080 004h] Mapping Count : 00000001
-[054h 0084 004h] Mapping Offset : 00000044
-
-[058h 0088 008h] Base Address : 0000000009050000
-[060h 0096 004h] Flags (decoded below) : 00000001
+[040h 0064 008h] Base Address : 0000000009050000
+[048h 0072 004h] Flags (decoded below) : 00000001
COHACC Override : 1
HTTU Override : 0
Proximity Domain Valid : 0
DeviceID Valid : 0
-[064h 0100 004h] Reserved : 00000000
-[068h 0104 008h] VATOS Address : 0000000000000000
-[070h 0112 004h] Model : 00000000
-[074h 0116 004h] Event GSIV : 0000006A
-[078h 0120 004h] PRI GSIV : 0000006B
-[07Ch 0124 004h] GERR GSIV : 0000006D
-[080h 0128 004h] Sync GSIV : 0000006C
-[084h 0132 004h] Proximity Domain : 00000000
-[088h 0136 004h] Device ID Mapping Index : 00000000
+[04Ch 0076 004h] Reserved : 00000000
+[050h 0080 008h] VATOS Address : 0000000000000000
+[058h 0088 004h] Model : 00000000
+[05Ch 0092 004h] Event GSIV : 0000006A
+[060h 0096 004h] PRI GSIV : 0000006B
+[064h 0100 004h] GERR GSIV : 0000006D
+[068h 0104 004h] Sync GSIV : 0000006C
+[06Ch 0108 004h] Proximity Domain : 00000000
+[070h 0112 004h] Device ID Mapping Index : 00000000
-[08Ch 0140 004h] Input base : 00000000
-[090h 0144 004h] ID Count : 0000FFFF
-[094h 0148 004h] Output Base : 00000000
-[098h 0152 004h] Output Reference : 00000030
-[09Ch 0156 004h] Flags (decoded below) : 00000000
- Single Mapping : 0
+[074h 0116 001h] Type : 02
+[075h 0117 002h] Length : 004C
+[077h 0119 001h] Revision : 03
+[078h 0120 004h] Identifier : 00000001
+[07Ch 0124 004h] Mapping Count : 00000002
+[080h 0128 004h] Mapping Offset : 00000024
-[0A0h 0160 001h] Type : 02
-[0A1h 0161 002h] Length : 0074
-[0A3h 0163 001h] Revision : 03
-[0A4h 0164 004h] Identifier : 00000002
-[0A8h 0168 004h] Mapping Count : 00000004
-[0ACh 0172 004h] Mapping Offset : 00000024
-
-[0B0h 0176 008h] Memory Properties : [IORT Memory Access Properties]
-[0B0h 0176 004h] Cache Coherency : 00000001
-[0B4h 0180 001h] Hints (decoded below) : 00
+[084h 0132 008h] Memory Properties : [IORT Memory Access Properties]
+[084h 0132 004h] Cache Coherency : 00000001
+[088h 0136 001h] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
-[0B5h 0181 002h] Reserved : 0000
-[0B7h 0183 001h] Memory Flags (decoded below) : 03
+[089h 0137 002h] Reserved : 0000
+[08Bh 0139 001h] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
Ensured Coherency of Accesses : 0
-[0B8h 0184 004h] ATS Attribute : 00000000
-[0BCh 0188 004h] PCI Segment Number : 00000000
-[0C0h 0192 001h] Memory Size Limit : 40
-[0C1h 0193 002h] PASID Capabilities : 0000
-[0C3h 0195 001h] Reserved : 00
+[08Ch 0140 004h] ATS Attribute : 00000000
+[090h 0144 004h] PCI Segment Number : 00000000
+[094h 0148 001h] Memory Size Limit : 40
+[095h 0149 002h] PASID Capabilities : 0000
+[097h 0151 001h] Reserved : 00
-[0C4h 0196 004h] Input base : 00000000
-[0C8h 0200 004h] ID Count : 000001FF
-[0CCh 0204 004h] Output Base : 00000000
-[0D0h 0208 004h] Output Reference : 00000048
-[0D4h 0212 004h] Flags (decoded below) : 00000000
+[098h 0152 004h] Input base : 00000000
+[09Ch 0156 004h] ID Count : 000001FF
+[0A0h 0160 004h] Output Base : 00000000
+[0A4h 0164 004h] Output Reference : 00000030
+[0A8h 0168 004h] Flags (decoded below) : 00000000
Single Mapping : 0
-[0D8h 0216 004h] Input base : 00001000
-[0DCh 0220 004h] ID Count : 000000FF
-[0E0h 0224 004h] Output Base : 00001000
-[0E4h 0228 004h] Output Reference : 00000048
-[0E8h 0232 004h] Flags (decoded below) : 00000000
+[0ACh 0172 004h] Input base : 00001000
+[0B0h 0176 004h] ID Count : 000000FF
+[0B4h 0180 004h] Output Base : 00001000
+[0B8h 0184 004h] Output Reference : 00000030
+[0BCh 0188 004h] Flags (decoded below) : 00000000
Single Mapping : 0
-[0ECh 0236 004h] Input base : 00000200
-[0F0h 0240 004h] ID Count : 00000DFF
-[0F4h 0244 004h] Output Base : 00000200
-[0F8h 0248 004h] Output Reference : 00000030
-[0FCh 0252 004h] Flags (decoded below) : 00000000
- Single Mapping : 0
+Raw Table Data: Length 192 (0xC0)
-[100h 0256 004h] Input base : 00001100
-[104h 0260 004h] ID Count : 0000EEFF
-[108h 0264 004h] Output Base : 00001100
-[10Ch 0268 004h] Output Reference : 00000030
-[110h 0272 004h] Flags (decoded below) : 00000000
- Single Mapping : 0
-
-Raw Table Data: Length 276 (0x114)
-
- 0000: 49 4F 52 54 14 01 00 00 05 4A 42 4F 43 48 53 20 // IORT.....JBOCHS
+ 0000: 49 4F 52 54 C0 00 00 00 05 1C 42 4F 43 48 53 20 // IORT......BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 03 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
- 0030: 00 18 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0040: 01 00 00 00 00 00 00 00 04 58 00 04 01 00 00 00 // .........X......
- 0050: 01 00 00 00 44 00 00 00 00 00 05 09 00 00 00 00 // ....D...........
- 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0070: 00 00 00 00 6A 00 00 00 6B 00 00 00 6D 00 00 00 // ....j...k...m...
- 0080: 6C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // l...............
- 0090: FF FF 00 00 00 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
- 00A0: 02 74 00 03 02 00 00 00 04 00 00 00 24 00 00 00 // .t..........$...
- 00B0: 01 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 // ................
- 00C0: 40 00 00 00 00 00 00 00 FF 01 00 00 00 00 00 00 // @...............
- 00D0: 48 00 00 00 00 00 00 00 00 10 00 00 FF 00 00 00 // H...............
- 00E0: 00 10 00 00 48 00 00 00 00 00 00 00 00 02 00 00 // ....H...........
- 00F0: FF 0D 00 00 00 02 00 00 30 00 00 00 00 00 00 00 // ........0.......
- 0100: 00 11 00 00 FF EE 00 00 00 11 00 00 30 00 00 00 // ............0...
- 0110: 00 00 00 00 // ....
+ 0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
+ 0030: 04 44 00 04 00 00 00 00 00 00 00 00 00 00 00 00 // .D..............
+ 0040: 00 00 05 09 00 00 00 00 01 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 6A 00 00 00 // ............j...
+ 0060: 6B 00 00 00 6D 00 00 00 6C 00 00 00 00 00 00 00 // k...m...l.......
+ 0070: 00 00 00 00 02 4C 00 03 01 00 00 00 02 00 00 00 // .....L..........
+ 0080: 24 00 00 00 01 00 00 00 00 00 00 03 00 00 00 00 // $...............
+ 0090: 00 00 00 00 40 00 00 00 00 00 00 00 FF 01 00 00 // ....@...........
+ 00A0: 00 00 00 00 30 00 00 00 00 00 00 00 00 10 00 00 // ....0...........
+ 00B0: FF 00 00 00 00 10 00 00 30 00 00 00 00 00 00 00 // ........0.......
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5f52ba1f341c98aea72f0695576da99f8510701a
https://github.com/qemu/qemu/commit/5f52ba1f341c98aea72f0695576da99f8510701a
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
A tests/data/acpi/aarch64/virt/APIC.msi_gicv2m
A tests/data/acpi/aarch64/virt/IORT.msi_gicv2m
Log Message:
-----------
qtest: hw/arm: virt: add ACPI tables for new GICv3 + GICv2m test case
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 72a231af4c66d7c94801266b3a73cd4e3454cb00
https://github.com/qemu/qemu/commit/72a231af4c66d7c94801266b3a73cd4e3454cb00
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
qtest: hw/arm: virt: add new test case for GICv3 + GICv2m
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5bc283d70540e480804e291496e45d5a7f8f5e2e
https://github.com/qemu/qemu/commit/5bc283d70540e480804e291496e45d5a7f8f5e2e
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M docs/system/arm/virt.rst
Log Message:
-----------
docs: arm: update virt machine model description
Update the documentation to match current QEMU.
Remove the mention of pre-2.7 machine models as those aren't provided
anymore.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1f1f9fd88c2affbe33f2497ae2142c9a27144305
https://github.com/qemu/qemu/commit/1f1f9fd88c2affbe33f2497ae2142c9a27144305
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M MAINTAINERS
M accel/meson.build
A accel/whpx/meson.build
A accel/whpx/whpx-accel-ops.c
A include/system/whpx-accel-ops.h
A include/system/whpx-internal.h
M target/i386/whpx/meson.build
R target/i386/whpx/whpx-accel-ops.c
R target/i386/whpx/whpx-accel-ops.h
M target/i386/whpx/whpx-all.c
M target/i386/whpx/whpx-apic.c
R target/i386/whpx/whpx-internal.h
Log Message:
-----------
whpx: Move around files before introducing AArch64 support
Switch to a design where we can share whpx code between x86 and AArch64 when it
makes sense to do so.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 4610fee324236cb4a3d2c12d2298ad5c06c4429a
https://github.com/qemu/qemu/commit/4610fee324236cb4a3d2c12d2298ad5c06c4429a
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M MAINTAINERS
M accel/whpx/meson.build
A accel/whpx/whpx-common.c
A include/system/whpx-all.h
A include/system/whpx-common.h
M target/i386/whpx/whpx-all.c
Log Message:
-----------
whpx: reshuffle common code
Some code can be shared between x86_64 and arm64 WHPX. Do so as much as
reasonable.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 69ac30ea1bc0dadbe84e4383841f3c3f1747551b
https://github.com/qemu/qemu/commit/69ac30ea1bc0dadbe84e4383841f3c3f1747551b
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M accel/whpx/whpx-common.c
M include/system/whpx-common.h
M include/system/whpx-internal.h
Log Message:
-----------
whpx: ifdef out winhvemulation on non-x86_64
winhvemulation is x86_64 only.
In the future, we might want to get rid of winhvemulation usage
entirely.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7573977b4e3c210a2021162978cecc3d50339d11
https://github.com/qemu/qemu/commit/7573977b4e3c210a2021162978cecc3d50339d11
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M accel/whpx/whpx-common.c
M include/system/whpx-common.h
Log Message:
-----------
whpx: common: add WHPX_INTERCEPT_DEBUG_TRAPS define
As of why: WHPX on arm64 doesn't have debug trap support as of today.
Keep the exception bitmap interface for now - despite that being entirely
unavailable on arm64 too.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: e4c95f78a4768c9bafe6154a765ac044b2f8c41b
https://github.com/qemu/qemu/commit/e4c95f78a4768c9bafe6154a765ac044b2f8c41b
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M MAINTAINERS
M accel/stubs/whpx-stub.c
M accel/whpx/whpx-accel-ops.c
M accel/whpx/whpx-common.c
M hw/arm/virt.c
M hw/i386/x86-cpu.c
M hw/intc/arm_gicv3_common.c
A hw/intc/arm_gicv3_whpx.c
M hw/intc/meson.build
M include/hw/intc/arm_gicv3_common.h
M include/system/whpx-internal.h
M include/system/whpx.h
M target/i386/cpu-apic.c
M target/i386/whpx/whpx-all.c
Log Message:
-----------
hw, target, accel: whpx: change apic_in_platform to kernel_irqchip
Change terminology to match the KVM one, as APIC is x86-specific.
And move out whpx_irqchip_in_kernel() to make it usable from common
code even when not compiling with WHPX support.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 59432082cef09dd0bd218c06e47a6a7323ef29d4
https://github.com/qemu/qemu/commit/59432082cef09dd0bd218c06e47a6a7323ef29d4
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M MAINTAINERS
M accel/whpx/whpx-common.c
M target/arm/meson.build
A target/arm/whpx/meson.build
A target/arm/whpx/whpx-all.c
Log Message:
-----------
whpx: add arm64 support
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: bf36e65bda7b62a704d1ec5552a47d846df43908
https://github.com/qemu/qemu/commit/bf36e65bda7b62a704d1ec5552a47d846df43908
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M accel/whpx/whpx-common.c
Log Message:
-----------
whpx: change memory management logic
This allows edk2 to work on Arm, although u-boot is still not functional.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5ae1609f00347614c2744a1bf74c24e6d5776571
https://github.com/qemu/qemu/commit/5ae1609f00347614c2744a1bf74c24e6d5776571
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: cpu: mark WHPX as supporting PSCI 1.3
Hyper-V supports PSCI 1.3, and that implementation is exposed through
WHPX.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: ea475a5ebb00a0f70810d75ff643d8d7f8b74306
https://github.com/qemu/qemu/commit/ea475a5ebb00a0f70810d75ff643d8d7f8b74306
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M hw/arm/virt.c
M include/hw/core/boards.h
M target/arm/whpx/meson.build
M target/arm/whpx/whpx-all.c
A target/arm/whpx/whpx-stub.c
A target/arm/whpx_arm.h
Log Message:
-----------
whpx: arm64: clamp down IPA size
Code taken from HVF and adapted for WHPX use. Note that WHPX doesn't
have a default vs maximum IPA distinction.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 293984563e53675ca409f0f36dd2682b88ce4e90
https://github.com/qemu/qemu/commit/293984563e53675ca409f0f36dd2682b88ce4e90
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M accel/hvf/hvf-all.c
M hw/arm/virt.c
M include/hw/core/boards.h
M include/system/hvf_int.h
R target/arm/hvf-stub.c
M target/arm/hvf/hvf.c
M target/arm/hvf_arm.h
M target/arm/meson.build
M target/arm/whpx/whpx-all.c
M target/i386/hvf/hvf.c
Log Message:
-----------
hw/arm, accel/hvf, whpx: unify get_physical_address_range between WHPX and HVF
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: f7fa2b88084c22299b347cea8fd9fadb0b136b22
https://github.com/qemu/qemu/commit/f7fa2b88084c22299b347cea8fd9fadb0b136b22
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/arm/cpu64.c
M target/arm/whpx/whpx-all.c
M target/arm/whpx_arm.h
Log Message:
-----------
whpx: arm64: implement -cpu host
Logic to fetch MIDR_EL1 for cpu 0 adapted from:
https://github.com/FEX-Emu/FEX/blob/e6de17e72ef03aa88ba14fa0ec13163061608c74/Source/Windows/Common/CPUFeatures.cpp#L62
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 515bf55441981a99ab8abd529df5c5c9a589aa62
https://github.com/qemu/qemu/commit/515bf55441981a99ab8abd529df5c5c9a589aa62
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/arm/whpx/whpx-all.c
Log Message:
-----------
target/arm: whpx: instantiate GIC early
While figuring out a better spot for it, put it in whpx_accel_init.
Needs to be done before WHvSetupPartition.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: b21fa1218d8976241f32c463f4c96f6245876c64
https://github.com/qemu/qemu/commit/b21fa1218d8976241f32c463f4c96f6245876c64
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M meson.build
Log Message:
-----------
whpx: enable arm64 builds
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: ac4af772ade858aa2a7cd23150fe43b3748ceb11
https://github.com/qemu/qemu/commit/ac4af772ade858aa2a7cd23150fe43b3748ceb11
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M include/system/whpx-internal.h
M target/arm/whpx/whpx-all.c
Log Message:
-----------
whpx: arm64: add partition-wide reset on the reboot path
This resets non-architectural state to allow for reboots to succeed.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5484e94cd473a1ca3b799503a83911a1b9b0ff54
https://github.com/qemu/qemu/commit/5484e94cd473a1ca3b799503a83911a1b9b0ff54
Author: Eric Auger <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Rename arm_virt_compat into arm_virt_compat_defaults
Renaming arm_virt_compat into arm_virt_compat_defaults
makes more obvious that those compats apply to all machine
types by default, if not overriden for specific ones. This also
matches the terminology used for pc-q35.
Suggested-by: Igor Mammedov <[email protected]>
Signed-off-by: Eric Auger <[email protected]>
Reviewed-by: Sebastian Ott <[email protected]>
Reviewed-by: Cornelia Huck <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: bc3d2e70673fc4b1a1c1e29a941d6f15a88fae00
https://github.com/qemu/qemu/commit/bc3d2e70673fc4b1a1c1e29a941d6f15a88fae00
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M target/arm/tcg/cpu32.c
Log Message:
-----------
target/arm: Remove entry for "any" from cpu32 arm_tcg_cpus[] list
Since commit a0032cc5427 ("target/arm: Make 'any' CPU just an alias
for 'max'") the 'any' CPU QOM type is never used, because we change
"any" to "max" before creating the object. The array entry means we
have an unnecessary type in the system, and the only user-visible
effect is that "any" is listed in the "-cpu help" output for
qemu-arm. (System emulation already doesn't include this array
entry.)
Since qemu-aarch64 already doesn't include "any" in its "-cpu help"
output, we can reasonably drop it for qemu-arm also; remove the
not-very-useful array entry.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
[PMM: update commit message to note effect on help output.]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d238858bff60a08557ed713678613625a4ef8313
https://github.com/qemu/qemu/commit/d238858bff60a08557ed713678613625a4ef8313
Author: Ashish Anand <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/machine.c
M target/arm/tcg/helper.h
M target/arm/tcg/m_helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/t16.decode
M target/arm/tcg/t32.decode
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Implement WFE, SEV and SEVONPEND for Cortex-M
Currently, QEMU implements the 'Wait For Event' (WFE) instruction as a
simple yield. This causes high host CPU usage because guest
RTOS idle loops effectively become busy-wait loops.
To improve efficiency, this patch transitions WFE to use the architectural
'Halt' state (EXCP_HLT) for M-profile CPUs. This allows the host thread
to sleep when the guest is idle.
To support this transition, we implement the full architectural behavior
required for WFE, specifically the 'Event Register', 'SEVONPEND' logic,
and 'R_BPBR' exception handling requirements defined in the ARM
Architecture Reference Manual.
This patch enables resource-efficient idle emulation for Cortex-M.
Signed-off-by: Ashish Anand <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: a2834b853d9e0f3e193671ab1f20b27329a02ece
https://github.com/qemu/qemu/commit/a2834b853d9e0f3e193671ab1f20b27329a02ece
Author: Alex Bennée <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu-features.h
M target/arm/helper.c
Log Message:
-----------
target/arm: implement FEAT_E2H0
FEAT_E2H0 is a formalisation of the existing behaviour of HCR_EL2.E2H
being programmable to switch between EL2 host mode and the
"traditional" nVHE EL2 mode. This implies at some point we might want
to model CPUs without FEAT_E2H0 which will always have EL2 host mode
enabled.
There are two values to represent no E2H0 systems of which 0b1110 will
make HCR_EL2.NV1 RES0 for FEAT_NV systems. For FEAT_NV2 the NV1 bit is
always valid.
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Mohamed Mediouni <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: e4244f84b3482fe491e246118d93c5685d09c166
https://github.com/qemu/qemu/commit/e4244f84b3482fe491e246118d93c5685d09c166
Author: Vladimir Sementsov-Ogievskiy <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M backends/tpm/tpm_emulator.c
Log Message:
-----------
tpm_emulator: print error on error-ignore path
Commit 3469a56fa3dc985 introduced errp passthrough for many
errors in the file. But in this specific case in
tpm_emulator_get_buffer_size(), it simply used errp=NULL, so we lose
printed error. Let's bring it back
Note also, that 3469a56fa3dc985 was fixing another commit,
42e556fa3f7a "backends/tpm: Propagate vTPM error on migration failure"
and didn't mention it.
Fixes: 3469a56fa3dc985 "tmp_emulator: improve and fix use of errp"
Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Stefan Berger <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Signed-off-by: Stefan Berger <[email protected]>
Commit: 18264ce6d68f1d66d7d1a444c9516f21a98e7e67
https://github.com/qemu/qemu/commit/18264ce6d68f1d66d7d1a444c9516f21a98e7e67
Author: Vladimir Sementsov-Ogievskiy <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M backends/tpm/tpm_emulator.c
Log Message:
-----------
tpm_emulator: drop direct use of errno variable
The code tends to include errno into error messages after
tpm_util_test_tpmdev() and tpm_emulator_ctrlcmd() calls.
Both has error paths, where errno is not set, examples:
tpm_emulator_ctrlcmd()
qemu_chr_fe_write_all()
qemu_chr_write()
replay_char_write_event_load()
...
*res = replay_get_dword();
...
tpm_util_test_tpmdev()
tpm_util_test()
tpm_util_request()
...
if (n != requestlen) {
return -EFAULT;
}
...
Both doesn't document that they set errno.
Let's drop these explicit usage of errno. If we need this information,
it should be added to errp deeper in the stack.
Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Stefan Berger <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Signed-off-by: Stefan Berger <[email protected]>
Commit: 46565a8db1fd1e41485341fcf51527047551f6a8
https://github.com/qemu/qemu/commit/46565a8db1fd1e41485341fcf51527047551f6a8
Author: Vladimir Sementsov-Ogievskiy <[email protected]>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M backends/tpm/tpm_emulator.c
Log Message:
-----------
tpm_emulator: tpm_emulator_set_state_blobs(): move to boolean return
The returned error is only used to check for success, so no reason
to use specific errno values.
Also, this is the only function with -errno contract in the file,
so converting it simplifies the whole file from three types of
contract (0/-1, 0/-errno, true/false) to only two (0/-1, true/false).
Signed-off-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Stefan Berger <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Signed-off-by: Stefan Berger <[email protected]>
Commit: 2f0870fd6aaafe8b5c94bad5e0658f985c8d3ddb
https://github.com/qemu/qemu/commit/2f0870fd6aaafe8b5c94bad5e0658f985c8d3ddb
Author: Peter Maydell <[email protected]>
Date: 2026-02-11 (Wed, 11 Feb 2026)
Changed paths:
M MAINTAINERS
M accel/hvf/hvf-all.c
M accel/meson.build
M accel/stubs/whpx-stub.c
A accel/whpx/meson.build
A accel/whpx/whpx-accel-ops.c
A accel/whpx/whpx-common.c
M docs/system/arm/emulation.rst
M docs/system/arm/virt.rst
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/i386/x86-cpu.c
M hw/intc/arm_gicv3_common.c
A hw/intc/arm_gicv3_whpx.c
M hw/intc/armv7m_nvic.c
M hw/intc/meson.build
M include/hw/arm/virt.h
M include/hw/core/boards.h
M include/hw/intc/arm_gicv3_common.h
M include/system/hvf_int.h
M include/system/hw_accel.h
A include/system/whpx-accel-ops.h
A include/system/whpx-all.h
A include/system/whpx-common.h
A include/system/whpx-internal.h
M include/system/whpx.h
M meson.build
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
R target/arm/hvf-stub.c
M target/arm/hvf/hvf.c
M target/arm/hvf_arm.h
M target/arm/kvm-consts.h
M target/arm/machine.c
M target/arm/meson.build
M target/arm/tcg/cpu32.c
M target/arm/tcg/helper.h
M target/arm/tcg/m_helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/t16.decode
M target/arm/tcg/t32.decode
M target/arm/tcg/translate.c
A target/arm/whpx/meson.build
A target/arm/whpx/whpx-all.c
A target/arm/whpx/whpx-stub.c
A target/arm/whpx_arm.h
M target/i386/cpu-apic.c
M target/i386/hvf/hvf.c
M target/i386/whpx/meson.build
R target/i386/whpx/whpx-accel-ops.c
R target/i386/whpx/whpx-accel-ops.h
M target/i386/whpx/whpx-all.c
M target/i386/whpx/whpx-apic.c
R target/i386/whpx/whpx-internal.h
A tests/data/acpi/aarch64/virt/APIC.msi_gicv2m
M tests/data/acpi/aarch64/virt/IORT
A tests/data/acpi/aarch64/virt/IORT.msi_gicv2m
M tests/data/acpi/aarch64/virt/IORT.smmuv3-dev
M tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy
M tests/qtest/bios-tables-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20260210' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* Add whpx accelerator support for the virt board
* Implement FEAT_E2H0
* Implement WFE, SEV and SEVONPEND for Cortex-M
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# gpg: Signature made Tue Feb 10 13:51:21 2026 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [ultimate]
# gpg: aka "Peter Maydell <[email protected]>" [ultimate]
# gpg: aka "Peter Maydell <[email protected]>"
[ultimate]
# gpg: aka "Peter Maydell <[email protected]>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20260210' of https://gitlab.com/pm215/qemu: (26 commits)
target/arm: implement FEAT_E2H0
target/arm: Implement WFE, SEV and SEVONPEND for Cortex-M
target/arm: Remove entry for "any" from cpu32 arm_tcg_cpus[] list
hw/arm/virt: Rename arm_virt_compat into arm_virt_compat_defaults
whpx: arm64: add partition-wide reset on the reboot path
whpx: enable arm64 builds
target/arm: whpx: instantiate GIC early
whpx: arm64: implement -cpu host
hw/arm, accel/hvf, whpx: unify get_physical_address_range between WHPX and HVF
whpx: arm64: clamp down IPA size
target/arm: cpu: mark WHPX as supporting PSCI 1.3
whpx: change memory management logic
whpx: add arm64 support
hw, target, accel: whpx: change apic_in_platform to kernel_irqchip
whpx: common: add WHPX_INTERCEPT_DEBUG_TRAPS define
whpx: ifdef out winhvemulation on non-x86_64
whpx: reshuffle common code
whpx: Move around files before introducing AArch64 support
docs: arm: update virt machine model description
qtest: hw/arm: virt: add new test case for GICv3 + GICv2m
...
Signed-off-by: Peter Maydell <[email protected]>
Commit: 44dba5a0c86fff68fdd013c29bba81d5a1e32825
https://github.com/qemu/qemu/commit/44dba5a0c86fff68fdd013c29bba81d5a1e32825
Author: Peter Maydell <[email protected]>
Date: 2026-02-11 (Wed, 11 Feb 2026)
Changed paths:
M backends/tpm/tpm_emulator.c
Log Message:
-----------
Merge tag 'pull-tpm-2026-02-10-1' of https://github.com/stefanberger/qemu-tpm
into staging
Merge tpm 2026/02/10 v1
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# gpg: Signature made Tue Feb 10 15:38:36 2026 GMT
# gpg: using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211
# gpg: Good signature from "Stefan Berger <[email protected]>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211
* tag 'pull-tpm-2026-02-10-1' of https://github.com/stefanberger/qemu-tpm:
tpm_emulator: tpm_emulator_set_state_blobs(): move to boolean return
tpm_emulator: drop direct use of errno variable
tpm_emulator: print error on error-ignore path
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/0b91040d23dc...44dba5a0c86f
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