Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 16786eb7bf8644398707e64fff12e4c9564ec131
https://github.com/qemu/qemu/commit/16786eb7bf8644398707e64fff12e4c9564ec131
Author: Helge Deller <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Add BMC on 64-bit machines only
Prevent adding the BMC with it's serial ports on 32-bit machines, even
if they have a PCI bus like the B160L. This fixes boot problems with
HP-UX on B160L.
Signed-off-by: Helge Deller <[email protected]>
Fixes: 557bc5260cfd ("hw/hppa: PCI devices depend on availability of PCI bus")
Cc: [email protected]
Reviewed-by: Anton Johansson <[email protected]>
Commit: 1546dc52046825ad9aeb8c6a9dd0e8de869ced97
https://github.com/qemu/qemu/commit/1546dc52046825ad9aeb8c6a9dd0e8de869ced97
Author: Helge Deller <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M pc-bios/hppa-firmware.img
M pc-bios/hppa-firmware64.img
M roms/seabios-hppa
Log Message:
-----------
target/hppa: Update SeaBIOS-hppa to version 22
The new firmware includes support for an A400-44 machine
with initial functional 64-bit PAT PDC support:
- Linux 64-bit kernel runs nicely.
- ODE 2006 works nicely on 715, B160L, and A400, but has problems on C3700.
- MPE and 64-bit HP-UX11 need more work, although HP-UX11 boot up to a crash
where it reports where it had problems.
Signed-off-by: Helge Deller <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Commit: 0a54ee20dd38959908904a2e261ca1c71da92f04
https://github.com/qemu/qemu/commit/0a54ee20dd38959908904a2e261ca1c71da92f04
Author: Helge Deller <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Require SeaBIOS version 22 for A400 machine
Require at least SeaBIOS version 22 before adding the A400 machine.
This is required, because version 22 adds the A400 machine definition
and provides the necessary 64-bit PAT firmware. All other machines up to
now used only the 32- or 64-bit PDC firmware without the PAT extensions.
Signed-off-by: Helge Deller <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Commit: 9e59b112b6c0e24831e1f28926df0bc917b14902
https://github.com/qemu/qemu/commit/9e59b112b6c0e24831e1f28926df0bc917b14902
Author: Helge Deller <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Add emulation for the 64-bit A400 server
The A400 machine is the very first 64-bit-only machines which uses the 64-bit
PAT firmware and doesn't support 32-bit PDC any longer. Long-term goal is to
support the MPE and HP-UX 11iv3 operating systems, which both require a machine
with PAT firmware.
Signed-off-by: Helge Deller <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Commit: 396d005e4b83aa4a65d81778d180d545046ba0a8
https://github.com/qemu/qemu/commit/396d005e4b83aa4a65d81778d180d545046ba0a8
Author: Pierrick Bouvier <[email protected]>
Date: 2026-02-19 (Thu, 19 Feb 2026)
Changed paths:
M contrib/plugins/cpp.cpp
Log Message:
-----------
contrib/plugins/cpp: use __has_include
This make sure we can include all possible headers without breaking
build for environments missing them. It fixes compilation on openbsd.
We don't want to pollute configure script, as it's really a special case
here to make sure we don't have a compilation regression with
qemu-plugins header.
Tested-by: John Snow <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Pierrick Bouvier <[email protected]>
Commit: 42d2c1cc9e89b77f1287ed433c655bc9e98bdc41
https://github.com/qemu/qemu/commit/42d2c1cc9e89b77f1287ed433c655bc9e98bdc41
Author: Yodel Eldar <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
A contrib/vhost-user-bridge/meson.build
A contrib/vhost-user-bridge/vhost-user-bridge.c
M docs/system/devices/virtio/vhost-user-contrib.rst
M meson.build
M tests/meson.build
R tests/vhost-user-bridge.c
Log Message:
-----------
tests/vhost-user-bridge: Move to contrib/vhost-user-bridge/
After the introduction of vhost-user-bridge and libvhost-user, we
formed the convention of placing vhost-user daemons in eponymous subdirs
of contrib/. Follow this convention.
Create a contrib/vhost-user-bridge/ directory and move vhost-user-bridge
into it. Extract its build target definition from tests/meson.build into
the new directory, and include its subdir in the root-level meson.build.
Add a section about it in the "vhost-user daemons in contrib" document.
Reviewed-by: Marc-André Lureau <[email protected]>
Signed-off-by: Yodel Eldar <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 051364b36b2c68058f7e6d2204ef2a877b0bb221
https://github.com/qemu/qemu/commit/051364b36b2c68058f7e6d2204ef2a877b0bb221
Author: Yodel Eldar <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M MAINTAINERS
M tests/functional/x86_64/meson.build
A tests/functional/x86_64/test_vhost_user_bridge.py
Log Message:
-----------
tests/functional/x86_64: Add vhost-user-bridge test
Introduce a functional test of vhost-user-bridge and enter it into
MAINTAINERS under the vhost section.
The test runs vhost-user-bridge as a subprocess, then launches a guest
with four backends: a unix domain socket for vhost-user, a UDP socket, a
user-mode net, and a hubport to hub the UDP and user backends; only the
vhost-user backend is exposed, the rest are deviceless. This
configuration mimics the testing setup described in the initial commit
of vhost-user-bridge in 3595e2eb0a23.
The test creates a scratch file containing a hardcoded UUID on the host
and exposes it to the the guest via the tftp parameter of the user
netdev. After the guest invokes tftp to request the file, the test
verifies the transfer by hashsum.
Similarly, the test creates a file with another hardcoded UUID in the
guest. A call to check_http_download() serves the file to the host via
http, whereupon a check of the file hashsum occurs on the host.
Lastly, add the test to the thorough tests suite in meson.build.
Suggested-by: Cédric Le Goater <[email protected]>
Suggested-by: Marc-André Lureau <[email protected]>
Suggested-by: Michael S. Tsirkin <[email protected]>
Suggested-by: Thomas Huth <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Marc-André Lureau <[email protected]>
Signed-off-by: Yodel Eldar <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: fa33e6815ee3926b485a12a6b654c7edbac8b373
https://github.com/qemu/qemu/commit/fa33e6815ee3926b485a12a6b654c7edbac8b373
Author: Yodel Eldar <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M contrib/vhost-user-bridge/vhost-user-bridge.c
Log Message:
-----------
contrib/vhost-user-bridge: Add UDP receive hexdump
vhost-user-bridge debug prints UDP TX hexdumps in its transmit handler,
but does not for receives, even though they are beneficial for testing.
Add an RX hexdump in the receive callback.
To delineate between transmits and receives, also add a debug print
indicating that the program is in the transmit handler.
Reviewed-by: Marc-André Lureau <[email protected]>
Signed-off-by: Yodel Eldar <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 27b370829294dcc4d1e9052e42bcd2b7cdd5c072
https://github.com/qemu/qemu/commit/27b370829294dcc4d1e9052e42bcd2b7cdd5c072
Author: Yanfeng Liu <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/audio/virtio-snd.c
M include/hw/audio/virtio-snd.h
Log Message:
-----------
audio/virtio-snd: fix latency calc
Media players needs meaningful latency_bytes update but it is
zero now most of the time. This adds stream-wise latency_bytes
calculation so that to improve the situation.
Signed-off-by: Yanfeng Liu <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 4d0830ea34abed563f15d3a236bef83a9026a7e8
https://github.com/qemu/qemu/commit/4d0830ea34abed563f15d3a236bef83a9026a7e8
Author: Mohamed Mediouni <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
A tests/data/acpi/disassemble-aml.sh
R tests/data/acpi/disassemle-aml.sh
M tests/data/acpi/rebuild-expected-aml.sh
Log Message:
-----------
tests/data/acpi: disassemble-aml: rename and change interpreter line
/usr/bin/bash isn't guaranteed to be present. Switch
to /usr/bin/env bash.
Specifically, on Darwin/macOS:
$ which bash
/opt/homebrew/bin/bash
Rename disassemle to disassemble in the same commit (typo fix).
Adapt the correponding message in rebuild-expected-aml.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Ani Sinha <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 843a97fa2c9f42685d714c00a1a812cb886017f5
https://github.com/qemu/qemu/commit/843a97fa2c9f42685d714c00a1a812cb886017f5
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/virtio/virtio.c
M include/hw/virtio/virtio.h
Log Message:
-----------
hw/virtio: Pass VirtIODevice* to virtio_reset()
virtio_reset() expects a VirtIODevice pointer, which
is what the single caller - virtio_bus_reset - passes.
Promote the opaque argument to a plain VirtIODevice.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 2fc064e23ecb1e83c26c7146aaa71ca5adec573e
https://github.com/qemu/qemu/commit/2fc064e23ecb1e83c26c7146aaa71ca5adec573e
Author: Shiju Jose <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M qapi/cxl.json
Log Message:
-----------
qapi: cxl: Refactor CXL event injection for common commands arguments
Refactor CXL event injection to use struct for common command
arguments.
Suggested-by: Markus Armbruster <[email protected]>
Signed-off-by: Shiju Jose <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Reviewed-by: Ravi Jonnalagadda <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: e5b7d31243dcd075f7f670bb105ac0f742176915
https://github.com/qemu/qemu/commit/e5b7d31243dcd075f7f670bb105ac0f742176915
Author: Shiju Jose <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-events.c
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M hw/mem/cxl_type3_stubs.c
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_events.h
M qapi/cxl.json
Log Message:
-----------
hw/cxl/events: Update for rev3.2 common event record format
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with optional Maintenance Operation Subclass,
LD ID and ID of the device head information.
Add updates for the above optional parameters in the related
CXL events reporting and in the QMP commands to inject CXL events.
Update all related specification references to CXL r3.2 to ensure
one consistent source.
Signed-off-by: Shiju Jose <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Reviewed-by: Ravi Jonnalagadda <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 1aa989a1767f91803493ec05d399f9c96bed3b90
https://github.com/qemu/qemu/commit/1aa989a1767f91803493ec05d399f9c96bed3b90
Author: Shiju Jose <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/mem/cxl_type3.c
M hw/mem/cxl_type3_stubs.c
M include/hw/cxl/cxl_events.h
M qapi/cxl.json
Log Message:
-----------
hw/cxl/events: Updates for rev3.2 general media event record
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
4. Support for component ID in the PLDM format.
Add updates for the above spec changes in the CXL general media event
reporting and QMP command to inject general media event.
In order to have one consistent source of references, update all to
references for this command to CXL r3.2.
Signed-off-by: Shiju Jose <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 94976b8631a11297b52826f51a638242b2767f9f
https://github.com/qemu/qemu/commit/94976b8631a11297b52826f51a638242b2767f9f
Author: Shiju Jose <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/mem/cxl_type3.c
M hw/mem/cxl_type3_stubs.c
M include/hw/cxl/cxl_events.h
M qapi/cxl.json
Log Message:
-----------
hw/cxl/events: Updates for rev3.2 DRAM event record
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error Count at Event
5. Memory Event Sub-Type
Add updates for the above spec changes in the CXL DRAM event
reporting and QMP command to inject DRAM event.
In order to ensure consistency update all specification references
for this command to CXL r3.2.
Signed-off-by: Shiju Jose <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 1fc57dd250944805a5d5f498ebf0775234be3851
https://github.com/qemu/qemu/commit/1fc57dd250944805a5d5f498ebf0775234be3851
Author: Shiju Jose <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/mem/cxl_type3.c
M hw/mem/cxl_type3_stubs.c
M include/hw/cxl/cxl_events.h
M qapi/cxl.json
Log Message:
-----------
hw/cxl/events: Updates for rev3.2 memory module event record
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-59, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command to inject memory module event.
Updated all references for this command to the CXL r3.2
specification.
Signed-off-by: Shiju Jose <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: d2c428ecd4b680456d759f78d8b8a18cffd00faf
https://github.com/qemu/qemu/commit/d2c428ecd4b680456d759f78d8b8a18cffd00faf
Author: Shiju Jose <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/cxl-mailbox-utils: Move declaration of scrub and ECS feature
attributes in cmd_features_set_feature()
Move the declaration of scrub and ECS feature attributes in
cmd_features_set_feature() to the local scope where they are used.
Signed-off-by: Shiju Jose <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 5e5a86bab8308a9d5db09cbfdf12cc3751dce0f7
https://github.com/qemu/qemu/commit/5e5a86bab8308a9d5db09cbfdf12cc3751dce0f7
Author: Davidlohr Bueso <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_events.h
Log Message:
-----------
hw/cxl: Add support for Maintenance command and Post Package Repair (PPR)
This adds initial support for the Maintenance command, specifically
the soft and hard PPR operations on a dpa. The implementation allows
to be executed at runtime, therefore semantically, data is retained
and CXL.mem requests are correctly processed.
Keep track of the requests upon a general media or DRAM event.
Post Package Repair (PPR) maintenance operations may be supported by CXL
devices that implement CXL.mem protocol. A PPR maintenance operation
requests the CXL device to perform a repair operation on its media.
For example, a CXL device with DRAM components that support PPR features
may implement PPR Maintenance operations. DRAM components may support two
types of PPR, hard PPR (hPPR), for a permanent row repair, and Soft PPR
(sPPR), for a temporary row repair. Soft PPR is much faster than hPPR,
but the repair is lost with a power cycle.
CXL spec 3.2 section 8.2.10.7.1.2 describes the device's sPPR (soft PPR)
maintenance operation and section 8.2.10.7.1.3 describes the device's
hPPR (hard PPR) maintenance operation feature.
CXL spec 3.2 section 8.2.10.7.2.1 describes the sPPR feature discovery and
configuration.
CXL spec 3.2 section 8.2.10.7.2.2 describes the hPPR feature discovery and
configuration.
CXL spec 3.2 section 8.2.10.2.1.4 Table 8-60 describes the Memory Sparing
Event Record.
Signed-off-by: Davidlohr Bueso <[email protected]>
Co-developed-by: Shiju Jose <[email protected]>
Signed-off-by: Shiju Jose <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: da5cafdc4dddc9e69983b99f01c8eb43a8140929
https://github.com/qemu/qemu/commit/da5cafdc4dddc9e69983b99f01c8eb43a8140929
Author: Shiju Jose <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_events.h
Log Message:
-----------
hw/cxl: Add emulation for memory sparing control feature
Memory sparing is defined as a repair function that replaces a portion of
memory with a portion of functional memory at that same DPA. The
subclasses for this operation vary in terms of the scope of the sparing
being performed. The Cacheline sparing subclass refers to a sparing
action that can replace a full cacheline. Row sparing is provided as an
alternative to PPR sparing functions and its scope is that of a single
DDR row. Bank sparing allows an entire bank to be replaced. Rank sparing
is defined as an operation in which an entire DDR rank is replaced.
Memory sparing maintenance operations may be supported by CXL devices
that implement CXL.mem protocol. A sparing maintenance operation requests
the CXL device to perform a repair operation on its media.
For example, a CXL device with DRAM components that support memory sparing
features may implement sparing Maintenance operations.
The host may issue a query command by setting Query Resources flag in the
Input Payload (CXL Spec 3.2 Table 8-120) to determine availability of
sparing resources for a given address. In response to a query request,
the device shall report the resource availability by producing the Memory
Sparing Event Record (CXL Spec 3.2 Table 8-60) in which the Channel, Rank,
Nibble Mask, Bank Group, Bank, Row, Column, Sub-Channel fields are a copy
of the values specified in the request.
During the execution of a sparing maintenance operation, a CXL memory
device:
- May or may not retain data
- May or may not be able to process CXL.mem requests correctly.
These CXL memory device capabilities are specified by restriction flags
in the memory sparing feature readable attributes.
When a CXL device identifies error on a memory component, the device
may inform the host about the need for a memory sparing maintenance
operation by using DRAM event record, where the 'maintenance needed' flag
may set. The event record contains some of the DPA, Channel, Rank,
Nibble Mask, Bank Group, Bank, Row, Column, Sub-Channel fields that
should be repaired. The userspace tool requests for maintenance operation
if the 'maintenance needed' flag set in the CXL DRAM error record.
CXL spec 3.2 section 8.2.10.7.2.3 describes the memory sparing feature
discovery and configuration.
CXL spec 3.2 section 8.2.10.7.1.4 describes the device's memory sparing
maintenance operation feature.
Add emulation for CXL memory device memory sparing control feature
and memory sparing maintenance operation command.
Signed-off-by: Shiju Jose <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: d29f3f5cddb2614b3eebe216cce59ef9350db0a0
https://github.com/qemu/qemu/commit/d29f3f5cddb2614b3eebe216cce59ef9350db0a0
Author: Davidlohr Bueso <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/mem/cxl_type3.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/cxl_upstream.c
M hw/pci/pcie.c
M include/hw/cxl/cxl_device.h
M include/hw/pci-bridge/cxl_upstream_port.h
M include/hw/pci/pcie.h
M include/hw/pci/pcie_port.h
Log Message:
-----------
hw/pcie: Support enabling flit mode
PCIe Flit Mode, introduced with the PCIe 6.0 specification, is a
fundamental change in how data is transmitted over the bus to
improve transfer rates. It shifts from variable-sized Transaction
Layer Packets (TLPs) to fixed 256-byte Flow Control Units (FLITs).
As with the link speed and width training, have ad-hoc property for
setting the flit mode and allow CXL components to make use of it.
For the CXL root port and dsp cases, always report flit mode but
the actual value after 'training' will depend on the downstream
device configuration.
Suggested-by: Jonathan Cameron <[email protected]>
Tested-by: Dongjoo Seo <[email protected]>
Signed-off-by: Davidlohr Bueso <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 5729c01a600d62c19202936481b06e84a14236ba
https://github.com/qemu/qemu/commit/5729c01a600d62c19202936481b06e84a14236ba
Author: Ira Weiny <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-component-utils.c
M include/hw/cxl/cxl_component.h
Log Message:
-----------
hw/cxl: Refactor component register initialization
CXL 3.2 8.2.4 Table 8-22 defines which capabilities are mandatory, not
permitted, or optional for each type of device.
cxl_component_register_init_common() uses a rather odd 'fall through'
mechanism to define each component register set. This assumes that any
device or capability being added builds on the previous devices
capabilities. This is not true as there are mutually exclusive
capabilities defined. For example, downstream ports can not have snoop
but it can have Back Invalidate capable decoders.
Refactor this code to make it easier to add individual capabilities as
defined by a device type. Any capability which is not specified by the
type is left NULL'ed out which complies with the packed nature of the
register array.
Update all spec references to 3.2.
No functional changes should be seen with this patch.
Signed-off-by: Ira Weiny <[email protected]>
Tested-by: Dongjoo Seo <[email protected]>
[rebased, no RAS for HBs, r3.2 references]
Signed-off-by: Davidlohr Bueso <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: de6eb4409525eb76a841911921a30a0ee1deddc7
https://github.com/qemu/qemu/commit/de6eb4409525eb76a841911921a30a0ee1deddc7
Author: Jonathan Cameron <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/bios-tables-test: Excluded CEDT.cxl for BI restriction relaxation.
The next patch will relax restrictions on the fixed memory window
to allow use with back invalidate capable devices.
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: e6742e71c24cf577a4677e9449269007c24ae4ab
https://github.com/qemu/qemu/commit/e6742e71c24cf577a4677e9449269007c24ae4ab
Author: Jonathan Cameron <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/acpi/cxl.c
Log Message:
-----------
hw/cxl: Update CXL Fixed Memory Window ACPI description to include Back
Invalidate support.
Defaults for these windows has always been to enable anything QEMU supports.
With the addition of back invalidate support it is necessary to specify that
host windows support this.
CXL emulation is currently only suitable for software stack verification.
The relaxation of the restrictions on this window to include BI have no
affect on the OS until BI capable devices are added and until now these
have not existed. As such no backwards compatibility impacts are expected
from this change.
Reviewed-by: Davidlohr Bueso <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 26cd3f8d96630d5735277a7fd5d5bc80fc8bb714
https://github.com/qemu/qemu/commit/26cd3f8d96630d5735277a7fd5d5bc80fc8bb714
Author: Jonathan Cameron <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M tests/data/acpi/x86/q35/CEDT.cxl
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi/cxl: Update CEDT.cxl to allow BI in CFWMS
With the addition of back invalidate support in the CXL emulation relax
the restriction on the CXL Fixed Memory Window Structures so all
advertised ranges continue to support being used with all features that
QEMU emulates.
[064h 0100 001h] Subtable Type : 01 [CXL Fixed Memory Window
Structure]
[065h 0101 001h] Reserved : 00
[066h 0102 002h] Length : 0028
[068h 0104 004h] Reserved : 00000000
[06Ch 0108 008h] Window base address : 0000000110000000
[074h 0116 008h] Window size : 0000000100000000
[07Ch 0124 001h] Interleave Members : 00
[07Dh 0125 001h] Interleave Arithmetic : 00
[07Eh 0126 002h] Reserved : 0000
[080h 0128 004h] Granularity : 00000005
[084h 0132 002h] Restrictions : 002F # Changed from 000F
[086h 0134 002h] QtgId : 0000
[088h 0136 004h] First Target : 0000000C
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 88ac457c88c237e1e025e88f71d8d1a2ff729aed
https://github.com/qemu/qemu/commit/88ac457c88c237e1e025e88f71d8d1a2ff729aed
Author: Davidlohr Bueso <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M docs/system/devices/cxl.rst
M hw/cxl/cxl-component-utils.c
M hw/mem/cxl_type3.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/cxl_upstream.c
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl: Support type3 HDM-DB
Add basic plumbing for memory expander devices that support Back
Invalidation. This introduces a 'hdm-db=on|off' parameter and
exposes the relevant BI RT/Decoder component cachemem registers.
Some noteworthy properties:
- Devices require enabling Flit mode across the CXL topology.
- Explicit BI-ID commit is required.
- HDM decoder support both host and dev coherency models.
Tested-by: Dongjoo Seo <[email protected]>
Signed-off-by: Davidlohr Bueso <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: defdfab32c78e8ad134e43494a835e0b3208705b
https://github.com/qemu/qemu/commit/defdfab32c78e8ad134e43494a835e0b3208705b
Author: Davidlohr Bueso <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-component-utils.c
Log Message:
-----------
hw/cxl: Remove register special_ops->read()
... this is unused, unlike its write counterpart.
Scope needs to be added to avoid _Static_assert() immediately
after a label. c23 makes this valid but before then it is compiler
dependent.
Suggested-by: [email protected]
Tested-by: Dongjoo Seo <[email protected]>
Signed-off-by: Davidlohr Bueso <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 25730acda4ada4f136e04b246b31dd54d3bb54b1
https://github.com/qemu/qemu/commit/25730acda4ada4f136e04b246b31dd54d3bb54b1
Author: Eugenio Pérez <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
net/vhost-vdpa: Whitelist virtio-net GSO for shadow virtqueue
Even if it is deprecated by the VirtIO standard it does not affect the
layout of the queue, or introduces new operations. So Shadow Virtqueue
can handle it just fine.
Tested with OVS DPDK and VDUSE.
Signed-off-by: Eugenio Pérez <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: a6e6a91c2ad1d5c9a770997a2ac3aad46a8e418c
https://github.com/qemu/qemu/commit/a6e6a91c2ad1d5c9a770997a2ac3aad46a8e418c
Author: Clement Mathieu--Drif <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Do not report recoverable faults to host
Signed-off-by: Clement Mathieu--Drif <[email protected]>
Reviewed-by: Zhenzhong Duan <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: b2a279094c3b86667969cc645f7fb1087e08dd19
https://github.com/qemu/qemu/commit/b2a279094c3b86667969cc645f7fb1087e08dd19
Author: Akihiko Odaki <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/display/virtio-gpu-virgl.c
Log Message:
-----------
virtio-gpu-virgl: Add virtio-gpu-virgl-hostmem-region type
Commit e27194e087ae ("virtio-gpu-virgl: correct parent for blob memory
region") made the name member of MemoryRegion unset, causing a NULL
pointer dereference[1]:
> Thread 2 "qemu-system-x86" received signal SIGSEGV, Segmentation fault.
> (gdb) bt
> #0 0x00007ffff56565e2 in __strcmp_evex () at /lib64/libc.so.6
> #1 0x0000555555841bdb in find_fd (head=0x5555572337d0 <cpr_state>,
> name=0x0, id=0) at ../migration/cpr.c:68
> #2 cpr_delete_fd (name=name@entry=0x0, id=id@entry=0) at
> ../migration/cpr.c:77
> #3 0x000055555582290a in qemu_ram_free (block=0x7ff7e93aa7f0) at
> ../system/physmem.c:2615
> #4 0x000055555581ae02 in memory_region_finalize (obj=<optimized out>)
> at ../system/memory.c:1816
> #5 0x0000555555a70ab9 in object_deinit (obj=<optimized out>,
> type=<optimized out>) at ../qom/object.c:715
> #6 object_finalize (data=0x7ff7e936eff0) at ../qom/object.c:729
> #7 object_unref (objptr=0x7ff7e936eff0) at ../qom/object.c:1232
> #8 0x0000555555814fae in memory_region_unref (mr=<optimized out>) at
> ../system/memory.c:1848
> #9 flatview_destroy (view=0x555559ed6c40) at ../system/memory.c:301
> #10 0x0000555555bfc122 in call_rcu_thread (opaque=<optimized out>) at
> ../util/rcu.c:324
> #11 0x0000555555bf17a7 in qemu_thread_start (args=0x555557b99520) at
> ../util/qemu-thread-posix.c:393
> #12 0x00007ffff556f464 in start_thread () at /lib64/libc.so.6
> #13 0x00007ffff55f25ac in __clone3 () at /lib64/libc.so.6
The intention of the aforementioned commit is to prevent a MemoryRegion
from parenting itself while its references is counted indendependently
of the device. To achieve the same goal, add a type of QOM objects that
count references and parent MemoryRegions.
[1]
https://lore.kernel.org/qemu-devel/[email protected]/
Cc: [email protected]
Fixes: e27194e087ae ("virtio-gpu-virgl: correct parent for blob memory region")
Signed-off-by: Akihiko Odaki <[email protected]>
Tested-by: Dmitry Osipenko <[email protected]>
Tested-by: Joelle van Dyne <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 7df839591cf9354f7cc054ff6d01e16d46ff9f33
https://github.com/qemu/qemu/commit/7df839591cf9354f7cc054ff6d01e16d46ff9f33
Author: Arpit Kumar <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
A include/hw/cxl/cxl_port.h
Log Message:
-----------
hw/cxl: Physical Port Info FMAPI - update to current spec and add defines.
Add a new cxl/cxl_ports.h header for field definitions related only to port
commands. Bring field naming up to date with spec as 'version' bitmasks
have been replaced with bitmasks of the specific features.
Fix a small issue where a reserved value for USP was set to 2 rather
than 0.
Signed-off-by: Arpit Kumar <[email protected]>
Co-developed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: be7ce15d350bad8ca636921448807b562bfa47c0
https://github.com/qemu/qemu/commit/be7ce15d350bad8ca636921448807b562bfa47c0
Author: Jonathan Cameron <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Get Physical Port State - update for PCIe flit mode
Recent support for 256B flits, was not accounted for in this FMAPI command
that should be retrieving the current status of Physical Switch Ports.
Note x-flit-mode control is via the downstream devices, so for USPs the
property must be checked to establish support, but for DSPs this mode is
always supported (control is with the next port downstream, typically the
end point. All cases the linksta2 register may be queried to obtain
current status. Note the PCI spec is a little confusing as it refers to
this bit only being non 0 if Device Readiness Status (DRS) is in particular
states (basically link trained) but Flit mode is a separate feature and DRS
may not be present. It is not yet emulated in QEMU. So assume that we
should reflect what states DRS would be reporting if it were actually
present.
One small thing to note is that the current link width for a port with
nothing connected reports the same as the capability. This is odd but valid
because the value under these circumstances is undefined (PCIe r6.2 table
7-26 Link Status Register - field Current Link Speed.)
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 6e1410fdcf7040b2c32a7845b423ab604384aded
https://github.com/qemu/qemu/commit/6e1410fdcf7040b2c32a7845b423ab604384aded
Author: Arpit Kumar <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_upstream.c
M include/hw/cxl/cxl_port.h
A include/hw/pci-bridge/cxl_downstream_port.h
M include/hw/pci-bridge/cxl_upstream_port.h
Log Message:
-----------
hw/cxl: Add Physical Port Control FMAPI Command (Opcode 5102h)
Added assert-deassert PERST implementation for physical ports (both USP
and DSP's).
Assert PERST involves bg operation for holding 100ms.
Reset PPB implementation for physical ports.
Signed-off-by: Arpit Kumar <[email protected]>
Co-developed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 5cf298a394f230d919a8b44a2bdc17fc3149c0dd
https://github.com/qemu/qemu/commit/5cf298a394f230d919a8b44a2bdc17fc3149c0dd
Author: Manos Pitsidianakis <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: add me as maintainer to virtio-snd
Cc: Michael S. Tsirkin <[email protected]>
Signed-off-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 34238f078a04f24b91199249b83846ab082b4e05
https://github.com/qemu/qemu/commit/34238f078a04f24b91199249b83846ab082b4e05
Author: Manos Pitsidianakis <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-snd: remove TODO comments
Replying with a VIRTIO_SND_S_BAD_MSG error does not warrant a device
reset. Instead, a device reset happens when the driver requests it from the
transport.
Signed-off-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 61679d7dcfa2dffc8fb115aa19b09e0e7cf5ea5c
https://github.com/qemu/qemu/commit/61679d7dcfa2dffc8fb115aa19b09e0e7cf5ea5c
Author: Manos Pitsidianakis <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-snd: handle 5.14.6.2 for PCM_INFO properly
The section 5.14.6.2 of the VIRTIO spec says:
5.14.6.2 Driver Requirements: Item Information Request
- The driver MUST NOT set start_id and count such that start_id +
count is greater than the total number of particular items that is
indicated in the device configuration space.
- The driver MUST provide a buffer of sizeof(struct virtio_snd_hdr) +
count * size bytes for the response.
While we performed some check for the second requirement, it failed to
check for integer overflow.
Add also a check for the first requirement, which should limit exposure
to any overflow, since realistically the number of streams will be low
enough in value such that overflow is improbable.
Cc: [email protected]
Reported-by: 罗铭源 <[email protected]>
Signed-off-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: bcb53328aa70023f1405fade4e253e7f77567261
https://github.com/qemu/qemu/commit/bcb53328aa70023f1405fade4e253e7f77567261
Author: Manos Pitsidianakis <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-snd: fix max_size bounds check in input cb
In 98e77e3d we calculated the max size and checked that each buffer is smaller
than it.
We neglected to subtract the size of the virtio_snd_pcm_status header
from the max size, and max_size was thus larger than the correct value,
leading to potential OOB writes.
If the buffer cannot fit the header or can fit only the header, return
the buffer immediately.
Cc: [email protected]
Fixes: 98e77e3dd8dd6e7aa9a7dffa60f49c8c8a49d4e3 ("virtio-snd: add max size
bounds check in input cb")
Reported-by: DARKNAVY <[email protected]>
Signed-off-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 7994203bb1b83a6604f3ab00fe9598909bb66164
https://github.com/qemu/qemu/commit/7994203bb1b83a6604f3ab00fe9598909bb66164
Author: Manos Pitsidianakis <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-snd: tighten read amount in in_cb
The amount of bytes to read passed to AUD_read() should never surpass
the maximum available buffer length. Tighten the current amount by
MIN(<amount>, max_size - <existing size>).
Cc: [email protected]
Fixes: 98e77e3dd8dd6e7aa9a7dffa60f49c8c8a49d4e3 ("virtio-snd: add max size
bounds check in input cb")
Reported-by: DARKNAVY <[email protected]>
Signed-off-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 72f663f575ab5e0f31320d7c9f25cc1f086313bd
https://github.com/qemu/qemu/commit/72f663f575ab5e0f31320d7c9f25cc1f086313bd
Author: Alexandr Moshkov <[email protected]>
Date: 2026-02-20 (Fri, 20 Feb 2026)
Changed paths:
M hw/virtio/vhost.c
Log Message:
-----------
vhost: fix vhost_inflight_buffer_pre_load
While I was rebasing my series about inflight migration, I missed a
small issue in vhost_inflight_buffer_preload:
* fix wrong return type in function
* fix error check
Signed-off-by: Alexandr Moshkov <[email protected]>
Fixes: tag pls?
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
Commit: 0954a965043b53738c838780c83dfed2f9874d72
https://github.com/qemu/qemu/commit/0954a965043b53738c838780c83dfed2f9874d72
Author: Peter Maydell <[email protected]>
Date: 2026-02-22 (Sun, 22 Feb 2026)
Changed paths:
M contrib/plugins/cpp.cpp
Log Message:
-----------
Merge tag 'pr-plugins-20260219' of https://gitlab.com/pbo-linaro/qemu into
staging
Changes:
- [PATCH] contrib/plugins/cpp: use __has_include (Pierrick Bouvier
<[email protected]>)
Link:
https://lore.kernel.org/qemu-devel/[email protected]
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# gpg: Signature made Thu Feb 19 20:35:01 2026 GMT
# gpg: using RSA key 66B994ECA14F7F2E5ABA081F7F90540D0A1CD00F
# gpg: Good signature from "Pierrick Bouvier <[email protected]>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 66B9 94EC A14F 7F2E 5ABA 081F 7F90 540D 0A1C D00F
* tag 'pr-plugins-20260219' of https://gitlab.com/pbo-linaro/qemu:
contrib/plugins/cpp: use __has_include
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1d893e5069494d27dba34346d85601fc238fd38d
https://github.com/qemu/qemu/commit/1d893e5069494d27dba34346d85601fc238fd38d
Author: Peter Maydell <[email protected]>
Date: 2026-02-22 (Sun, 22 Feb 2026)
Changed paths:
M MAINTAINERS
A contrib/vhost-user-bridge/meson.build
A contrib/vhost-user-bridge/vhost-user-bridge.c
M docs/system/devices/cxl.rst
M docs/system/devices/virtio/vhost-user-contrib.rst
M hw/acpi/cxl.c
M hw/audio/virtio-snd.c
M hw/cxl/cxl-component-utils.c
M hw/cxl/cxl-events.c
M hw/cxl/cxl-mailbox-utils.c
M hw/display/virtio-gpu-virgl.c
M hw/i386/intel_iommu.c
M hw/mem/cxl_type3.c
M hw/mem/cxl_type3_stubs.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/cxl_upstream.c
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci/pcie.c
M hw/virtio/vhost.c
M hw/virtio/virtio.c
M include/hw/audio/virtio-snd.h
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_events.h
A include/hw/cxl/cxl_port.h
A include/hw/pci-bridge/cxl_downstream_port.h
M include/hw/pci-bridge/cxl_upstream_port.h
M include/hw/pci/pcie.h
M include/hw/pci/pcie_port.h
M include/hw/virtio/virtio.h
M meson.build
M net/vhost-vdpa.c
M qapi/cxl.json
A tests/data/acpi/disassemble-aml.sh
R tests/data/acpi/disassemle-aml.sh
M tests/data/acpi/rebuild-expected-aml.sh
M tests/data/acpi/x86/q35/CEDT.cxl
M tests/functional/x86_64/meson.build
A tests/functional/x86_64/test_vhost_user_bridge.py
M tests/meson.build
R tests/vhost-user-bridge.c
Log Message:
-----------
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
virtio,pc,pci: features, fixes
cxl:
RAS features
Back-Invalidate
Flit mode
r3.2 spec event updates
FM-API Physical Switch Command Set support
vhost-vdpa: allow GSO for SVQ
misc fixes, cleanups in intel_iommu, vhost, virtio, acpi
Signed-off-by: Michael S. Tsirkin <[email protected]>
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# gpg: Signature made Fri Feb 20 19:33:13 2026 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "[email protected]"
# gpg: Good signature from "Michael S. Tsirkin <[email protected]>" [full]
# gpg: aka "Michael S. Tsirkin <[email protected]>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (33
commits)
vhost: fix vhost_inflight_buffer_pre_load
virtio-snd: tighten read amount in in_cb
virtio-snd: fix max_size bounds check in input cb
virtio-snd: handle 5.14.6.2 for PCM_INFO properly
virtio-snd: remove TODO comments
MAINTAINERS: add me as maintainer to virtio-snd
hw/cxl: Add Physical Port Control FMAPI Command (Opcode 5102h)
hw/cxl: Get Physical Port State - update for PCIe flit mode
hw/cxl: Physical Port Info FMAPI - update to current spec and add defines.
virtio-gpu-virgl: Add virtio-gpu-virgl-hostmem-region type
intel_iommu: Do not report recoverable faults to host
net/vhost-vdpa: Whitelist virtio-net GSO for shadow virtqueue
hw/cxl: Remove register special_ops->read()
hw/cxl: Support type3 HDM-DB
tests/acpi/cxl: Update CEDT.cxl to allow BI in CFWMS
hw/cxl: Update CXL Fixed Memory Window ACPI description to include Back
Invalidate support.
tests/bios-tables-test: Excluded CEDT.cxl for BI restriction relaxation.
hw/cxl: Refactor component register initialization
hw/pcie: Support enabling flit mode
hw/cxl: Add emulation for memory sparing control feature
...
Signed-off-by: Peter Maydell <[email protected]>
Commit: 05de1b53094c2b3b9d50fa60e38b93f660ed4d59
https://github.com/qemu/qemu/commit/05de1b53094c2b3b9d50fa60e38b93f660ed4d59
Author: Peter Maydell <[email protected]>
Date: 2026-02-22 (Sun, 22 Feb 2026)
Changed paths:
M hw/hppa/machine.c
M pc-bios/hppa-firmware.img
M pc-bios/hppa-firmware64.img
M roms/seabios-hppa
Log Message:
-----------
Merge tag 'hppa-a400-pull-request' of https://github.com/hdeller/qemu-hppa
into staging
hppa a400 machine support
Major enhancements to SeaBIOS-hppa to support an A400 server. This server
requires 64-bit PAT firmware, so SeaBIOS-hppa was extendend a lot. PAT firmware
is required as well to support 64-bit HP-UX 11i3 or MPE.
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu Feb 19 12:43:39 2026 GMT
# gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <[email protected]>" [unknown]
# gpg: aka "Helge Deller <[email protected]>" [unknown]
# gpg: aka "Helge Deller <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603
# Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F
* tag 'hppa-a400-pull-request' of https://github.com/hdeller/qemu-hppa:
hw/hppa: Add emulation for the 64-bit A400 server
hw/hppa: Require SeaBIOS version 22 for A400 machine
target/hppa: Update SeaBIOS-hppa to version 22
hw/hppa: Add BMC on 64-bit machines only
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/07f97d5da04a...05de1b53094c
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