Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 57b5d07c240ad4de983b769f6a60d27c573856cf
https://github.com/qemu/qemu/commit/57b5d07c240ad4de983b769f6a60d27c573856cf
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M hw/ppc/pnv_sbe.c
Log Message:
-----------
ppc/pnv: Move SBE host doorbell function to top of file
Moved 'pnv_sbe_set_host_doorbell' as-it-is to above
'pnv_sbe_power9_xscom_ctrl_write'.
This is done since in a future patch, S0 interrupt implementation uses
'pnv_sbe_set_host_doorbell', hence the host doorbell function needs to
be declared/defined before 'pnv_sbe_power9_xscom_ctrl_write' where we
implement the S0 interrupt.
No functional change.
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 2a864ec1afedd2cad24573af78cb6236ea9ced90
https://github.com/qemu/qemu/commit/2a864ec1afedd2cad24573af78cb6236ea9ced90
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M hw/ppc/meson.build
A hw/ppc/pnv_mpipl.c
M hw/ppc/pnv_sbe.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_mpipl.h
Log Message:
-----------
ppc/mpipl: Implement S0 SBE interrupt
During MPIPL (aka fadump), after a kernel crash, the kernel does
opal_cec_reboot2 opal call, signifying an abnormal termination.
When OPAL receives this opal call, it further triggers SBE S0 interrupt,
to trigger a MPIPL boot.
Currently S0 interrupt is unimplemented in QEMU.
Implement S0 interrupt as 'pause_vcpus' + 'guest_reset' in QEMU, as the
SBE's implementation of S0 seems to be basically "stop all clocks" and
then "host reset".
pause_vcpus is done in a later patch when register preserving support is
added
See 'stopClocksS0' in SBE source code for more information.
Also log both S0 and S1 interrupts.
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 3ca529809ba0653ebe5113c9dbe3dece96cf73f0
https://github.com/qemu/qemu/commit/3ca529809ba0653ebe5113c9dbe3dece96cf73f0
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M hw/ppc/pnv_sbe.c
M include/hw/ppc/pnv_mpipl.h
Log Message:
-----------
ppc/pnv: Handle stash command in PowerNV SBE
Earlier since the SBE_CMD_STASH_MPIPL_CONFIG command was not handled, so
skiboot used to not get any response from SBE:
[ 106.350742821,3] SBE: Message timeout [chip id = 0], cmd = d7, subcmd = 7
[ 106.352067746,3] SBE: Failed to send stash MPIPL config [chip id = 0x0,
rc = 254]
Fix this by handling the command in PowerNV SBE, and sending a response so
skiboot knows SBE has handled the STASH command
The stashed skiboot base is later used to access the relocated MDST/MDDT
tables when MPIPL is implemented.
The purpose of stashing relocated base address is explained in following
skiboot commit:
author Vasant Hegde <[email protected]> Fri Jul 12 16:47:51
2019 +0530
committer Oliver O'Halloran <[email protected]> Thu Aug 15 17:53:39 2019
+1000
SBE: Send OPAL relocated base address to SBE
OPAL relocates itself during boot. During memory preserving IPL hostboot
needs
to access relocated OPAL base address to get MDST, MDDT tables. Hence send
relocated base address to SBE via 'stash MPIPL config' chip-op. During
next
IPL SBE will send stashed data to hostboot... so that hostboot can access
these data.
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: ace7768938961d1472c7060153910489b9bf385b
https://github.com/qemu/qemu/commit/ace7768938961d1472c7060153910489b9bf385b
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M hw/ppc/pnv_mpipl.c
M include/hw/ppc/pnv_mpipl.h
Log Message:
-----------
pnv/mpipl: Preserve memory regions as per MDST/MDDT tables
Implement copying of memory region, as mentioned by MDST and MDDT
tables.
Copy the memory regions from source to destination in chunks of 32MB
Note, qemu can fail preserving a particular entry due to any reason,
such as:
* region length mis-matching in MDST & MDDT
* failed copy due to access/decode/etc memory issues
HDAT doesn't specify any field in MDRT to notify host about such errors.
Though HDAT section "15.3.1.3 Memory Dump Results Table (MDRT)" says:
The Memory Dump Results Table is a list of the memory ranges that
have been included in the dump
Based on above statement, it looks like MDRT should include only those
regions which are successfully captured in the dump, hence, regions
which qemu fails to dump, just get skipped, and will not have a
corresponding entry in MDRT
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 2fae1f2ebc60ec9554918f494743ae91059479c9
https://github.com/qemu/qemu/commit/2fae1f2ebc60ec9554918f494743ae91059479c9
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M hw/ppc/pnv_mpipl.c
M include/hw/ppc/pnv_mpipl.h
Log Message:
-----------
pnv/mpipl: Preserve CPU registers after crash
Kernel expects the platform to provide CPU registers after pausing
execution of the CPUs.
Currently only exporting the registers, used by Linux, for generating
the /proc/vmcore
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 5e0134de6b4db1c791052f9be16e174a1d8509a9
https://github.com/qemu/qemu/commit/5e0134de6b4db1c791052f9be16e174a1d8509a9
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
pnv/mpipl: Set thread entry size to be allocated by firmware
Set the "Thread Register State Entry Size" that is required by firmware
(OPAL), to know size of memory to allocate to capture CPU state, in the
event of a crash
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: ff9ff1acd87abeb72200b1cd62eb32eb8933d103
https://github.com/qemu/qemu/commit/ff9ff1acd87abeb72200b1cd62eb32eb8933d103
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_mpipl.c
M include/hw/ppc/pnv.h
Log Message:
-----------
pnv/mpipl: Write the preserved CPU and MDRT state
Logic for preserving the CPU registers and memory regions has been done
in previous patches.
Write those data at the relevant memory address, such as PROC_DUMP_AREA
for CPU registers, and MDRT for preserved memory regions.
Also export "mpipl-boot" device tree node, for kernel to know that it's
a 'dump active' boot
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: a2d469623731788d5f3fe33a4ec6f9aa3e1b99df
https://github.com/qemu/qemu/commit/a2d469623731788d5f3fe33a4ec6f9aa3e1b99df
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
pnv/mpipl: Enable MPIPL support
With all MPIPL support in place, export a "dump" node in device tree,
signifying that PowerNV QEMU platform supports MPIPL
Also, export fw-load-area dt node, which has details about where the
kernel & initrd were loaded, so that kernel can verify whether the
kernel/initrd images were loaded within the boot memory region. QEMU
just exports these details in fw-load-area, the check for boot memory
region is done in kernel.
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 86f90baf145eb1516709bea8a817ea9e74727e72
https://github.com/qemu/qemu/commit/86f90baf145eb1516709bea8a817ea9e74727e72
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M tests/functional/ppc64/test_fadump.py
Log Message:
-----------
tests/functional: Add test for MPIPL in PowerNV
With MPIPL support implemented, enable fadump's functional test for PowerNV
Also, current functional test for powernv uses op-build's Linux 5.10 image,
which doesn't support adding "fadump=on" in argument due to this:
Kernel is locked down from Kernel configuration; see man kernel_lockdown.7
Hence, instead of op-build's image, use the newer fedora vmlinuz as used
in FADump PSeries functional test
Also due to "bash#" string not showing up, rely on sh: no job control to
check if testcase has reached till shell
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: 8d00b61217814fa6809768b8d2ca13167ad4106a
https://github.com/qemu/qemu/commit/8d00b61217814fa6809768b8d2ca13167ad4106a
Author: Aditya Gupta <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add entry for MPIPL (PowerNV)
Add maintainer and reviewer for MPIPL subsystem.
Reviewed-by: Hari Bathini <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Shivang Upadhyay <[email protected]>
Reviewed-by: Sourabh Jain <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Harsh Prateek Bora <[email protected]>
Commit: d8ddafa8d9221a75e1d91b9aa6f4092e75b42f66
https://github.com/qemu/qemu/commit/d8ddafa8d9221a75e1d91b9aa6f4092e75b42f66
Author: Peter Maydell <[email protected]>
Date: 2026-03-10 (Tue, 10 Mar 2026)
Changed paths:
M MAINTAINERS
M hw/ppc/meson.build
M hw/ppc/pnv.c
A hw/ppc/pnv_mpipl.c
M hw/ppc/pnv_sbe.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_mpipl.h
M tests/functional/ppc64/test_fadump.py
Log Message:
-----------
Merge tag 'pull-ppc-for-11.0-softfreeze-20260310' of
https://gitlab.com/harshpb/qemu into staging
PPC PR for 11.0 soft-freeze
- MPIPL support for PowerNV
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# gpg: Signature made Tue Mar 10 14:56:36 2026 GMT
# gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <[email protected]>"
[full]
# gpg: aka "Harsh Prateek Bora <[email protected]>" [full]
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB
* tag 'pull-ppc-for-11.0-softfreeze-20260310' of
https://gitlab.com/harshpb/qemu:
MAINTAINERS: Add entry for MPIPL (PowerNV)
tests/functional: Add test for MPIPL in PowerNV
pnv/mpipl: Enable MPIPL support
pnv/mpipl: Write the preserved CPU and MDRT state
pnv/mpipl: Set thread entry size to be allocated by firmware
pnv/mpipl: Preserve CPU registers after crash
pnv/mpipl: Preserve memory regions as per MDST/MDDT tables
ppc/pnv: Handle stash command in PowerNV SBE
ppc/mpipl: Implement S0 SBE interrupt
ppc/pnv: Move SBE host doorbell function to top of file
Signed-off-by: Peter Maydell <[email protected]>
Compare: https://github.com/qemu/qemu/compare/d090f7e1fe80...d8ddafa8d922
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