[Stable-10.0.1 41/59] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

[Michael Tokarev]

From: Max Chou <max.c...@sifive.com>

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <ant...@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Signed-off-by: Max Chou <max.c...@sifive.com>
Message-ID: <20250408103938.3623486-10-max.c...@sifive.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Cc: qemu-sta...@nongnu.org
(cherry picked from commit db21c3eb05504c4cedaad4f7b19e588361b02385)
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index 2d067a59e2..445a0b72a5 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1043,7 +1043,8 @@ static bool ld_index_check(DisasContext *s, arg_rnfvm* a, 
uint8_t eew)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew);
+           vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew) &&
+           vext_check_input_eew(s, -1, 0, a->rs2, eew, a->vm);
 }
 
 GEN_VEXT_TRANS(vlxei8_v,  MO_8,  rnfvm, ld_index_op, ld_index_check)
@@ -1095,7 +1096,8 @@ static bool st_index_check(DisasContext *s, arg_rnfvm* a, 
uint8_t eew)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_st_index(s, a->rd, a->rs2, a->nf, eew);
+           vext_check_st_index(s, a->rd, a->rs2, a->nf, eew) &&
+           vext_check_input_eew(s, a->rd, s->sew, a->rs2, eew, a->vm);
 }
 
 GEN_VEXT_TRANS(vsxei8_v,  MO_8,  rnfvm, st_index_op, st_index_check)
-- 
2.39.5