On Wed, May 28, 2025 at 05:01:28PM -0300, Daniel Henrique Barboza wrote: > From: Fei Wu <wu.f...@sanechips.com.cn> > > The RISC-V Server Platform specification[1] defines a standardized set > of hardware and software capabilities, that portable system software, > such as OS and hypervisors can rely on being present in a RISC-V server > platform. > > A corresponding Qemu RISC-V server platform reference (rvsp-ref for > short) machine type is added to provide a environment for firmware/OS > development and testing. The main features included in rvsp-ref are: > > - Based on riscv virt machine type > - A new memory map as close as virt machine as possible > - A new virt CPU type rvsp-ref-cpu for server platform compliance > - AIA > - PCIe AHCI > - PCIe NIC > - No virtio device > - No fw_cfg device > - No ACPI table provided > - Only minimal device tree nodes
The server platform spec requires BRS-I (see FIRM_010). BRS-I requires ACPI, and even some specific ACPI tables, e.g. PPTT (see Chapter 6 of the BRS spec). However, I think the idea is we're suppose to generate a DT here and then leave it to edk2 to generate ACPI tables from that DT. > > [1] https://github.com/riscv-non-isa/riscv-server-platform > > Signed-off-by: Fei Wu <fei2...@intel.com> > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > --- > configs/devices/riscv64-softmmu/default.mak | 1 + > hw/riscv/Kconfig | 14 + > hw/riscv/meson.build | 1 + > hw/riscv/server_platform_ref.c | 1276 +++++++++++++++++++ > 4 files changed, 1292 insertions(+) > create mode 100644 hw/riscv/server_platform_ref.c > > diff --git a/configs/devices/riscv64-softmmu/default.mak > b/configs/devices/riscv64-softmmu/default.mak > index 39ed3a0061..0c4893b708 100644 > --- a/configs/devices/riscv64-softmmu/default.mak > +++ b/configs/devices/riscv64-softmmu/default.mak > @@ -9,5 +9,6 @@ > # CONFIG_SIFIVE_E=n > # CONFIG_SIFIVE_U=n > # CONFIG_RISCV_VIRT=n > +# CONFIG_SERVER_PLATFORM_REF=n > # CONFIG_MICROCHIP_PFSOC=n > # CONFIG_SHAKTI_C=n > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index e6a0ac1fa1..f626774c52 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -69,6 +69,20 @@ config RISCV_VIRT > select ACPI > select ACPI_PCI > > +config SERVER_PLATFORM_REF > + bool > + default y > + depends on RISCV64 > + select RISCV_NUMA > + select GOLDFISH_RTC > + select PCI > + select PCI_EXPRESS_GENERIC_BRIDGE > + select PFLASH_CFI01 > + select SERIAL > + select RISCV_ACLINT We shouldn't need ACLINT. > + select RISCV_APLIC > + select RISCV_IMSIC > + > config SHAKTI_C > bool > default y > diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build > index c22f3a7216..7a663fac64 100644 > --- a/hw/riscv/meson.build > +++ b/hw/riscv/meson.build > @@ -4,6 +4,7 @@ riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: > files('numa.c')) > riscv_ss.add(files('riscv_hart.c')) > riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) > riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) > +riscv_ss.add(when: 'CONFIG_SERVER_PLATFORM_REF', if_true: > files('server_platform_ref.c')) > riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) > riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) > riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) > diff --git a/hw/riscv/server_platform_ref.c b/hw/riscv/server_platform_ref.c > new file mode 100644 > index 0000000000..5102286103 > --- /dev/null > +++ b/hw/riscv/server_platform_ref.c > @@ -0,0 +1,1276 @@ Missing SPDX > +/* > + * QEMU RISC-V Server Platform (RVSP) Reference Board > + * > + * Copyright (c) 2024 Intel, Inc. > + * Copyright (c) 2025 Ventana Micro Systems Inc. > + * > + * This board is compliant RISC-V Server platform specification and > leveraging > + * a lot of riscv virt code. This board provides a reference implementation of the RISC-V Server Platform specification. > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or later. > + * See the COPYING file in the top-level directory. Can be dropped, since we want SPDX instead. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/units.h" > +#include "qemu/error-report.h" > +#include "qemu/guest-random.h" > +#include "qapi/error.h" > +#include "qapi/qapi-visit-common.h" > +#include "hw/boards.h" > +#include "hw/loader.h" > +#include "hw/sysbus.h" > +#include "hw/qdev-properties.h" > +#include "hw/char/serial.h" > +#include "hw/block/flash.h" > +#include "hw/ide/pci.h" > +#include "hw/ide/ahci-pci.h" > +#include "hw/pci/pci.h" > +#include "hw/pci-host/gpex.h" > +#include "hw/core/sysbus-fdt.h" > +#include "hw/riscv/riscv_hart.h" > +#include "hw/riscv/boot.h" > +#include "hw/riscv/numa.h" > +#include "hw/intc/riscv_aclint.h" > +#include "hw/intc/riscv_aplic.h" > +#include "hw/intc/riscv_imsic.h" > +#include "chardev/char.h" > +#include "hw/char/serial-mm.h" > +#include "system/device_tree.h" > +#include "system/runstate.h" > +#include "system/system.h" > +#include "system/tcg.h" > +#include "system/qtest.h" > +#include "target/riscv/cpu.h" > +#include "target/riscv/pmu.h" > +#include "net/net.h" > + > +#define RVSP_CPUS_MAX_BITS 9 > +#define RVSP_CPUS_MAX (1 << RVSP_CPUS_MAX_BITS) > +#define RVSP_SOCKETS_MAX_BITS 2 > +#define RVSP_SOCKETS_MAX (1 << RVSP_SOCKETS_MAX_BITS) > + > +#define RVSP_IRQCHIP_NUM_MSIS 255 > +#define RVSP_IRQCHIP_NUM_SOURCES 96 > +#define RVSP_IRQCHIP_NUM_PRIO_BITS 3 > +#define RVSP_IRQCHIP_MAX_GUESTS_BITS 3 > +#define RVSP_IRQCHIP_MAX_GUESTS ((1U << RVSP_IRQCHIP_MAX_GUESTS_BITS) - 1U) > + > +#define FDT_PCI_ADDR_CELLS 3 > +#define FDT_PCI_INT_CELLS 1 > +#define FDT_APLIC_INT_CELLS 2 > +#define FDT_IMSIC_INT_CELLS 0 > +#define FDT_MAX_INT_CELLS 2 > +#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ > + 1 + FDT_MAX_INT_CELLS) > +#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ > + 1 + FDT_APLIC_INT_CELLS) > + > +#define NUM_SATA_PORTS 6 > + > +#define SYSCON_RESET 0x1 > +#define SYSCON_POWEROFF 0x2 nit: should align all the above defines > + > +#define TYPE_RVSP_REF_MACHINE MACHINE_TYPE_NAME("rvsp-ref") > +OBJECT_DECLARE_SIMPLE_TYPE(RVSPMachineState, RVSP_REF_MACHINE) > + > +struct RVSPMachineState { > + /*< private >*/ > + MachineState parent; > + > + /*< public >*/ > + Notifier machine_done; > + RISCVHartArrayState soc[RVSP_SOCKETS_MAX]; > + DeviceState *irqchip[RVSP_SOCKETS_MAX]; > + PFlashCFI01 *flash[2]; > + > + int fdt_size; > + int aia_guests; This can be hard coded to 5, as required by the server-soc spec. Thanks, drew
