Hello, The following allows support for component basic back invalidation discovery and config, by exposing the BI routing table and decoder registers. Instead of going the type2[0] route, this series proposes adding support for type3 hdm-db, which allows a more direct way of supporting BI in qemu.
Changes from rfc (https://lore.kernel.org/qemu-devel/20250729165441.1898150-1-d...@stgolabs.net/) o Added 256b-flit parameter, per Jonathan. o Added window restrictions changes. o Dropped rfc tag. Patch 1 introduces the flit mode parameter. Patch 2 is lifted from Ira's series with some small (but non-trivial) changes. Patch 3 updates the cfmw restrictions option. Patch 4 adds BI decoder/rt register support. Testing wise, this has passed relevant kernel side BI register IO flows for BI-ID setup and deallocation. The next step for this would be to add UIO support to qemu. Applies against branch 'origin/cxl-2025-07-03' from Jonathan's repository. Thanks! [0] https://lore.kernel.org/linux-cxl/20230517-rfc-type2-dev-v1-0-6eb2e4709...@intel.com/ Davidlohr Bueso (3): hw/pcie: Support enabling flit mode hw/cxl: Allow BI by default in Window restrictions hw/cxl: Support Type3 HDM-DB Ira Weiny (1): hw/cxl: Refactor component register initialization docs/system/devices/cxl.rst | 26 +++ hw/core/qdev-properties-system.c | 11 ++ hw/cxl/cxl-component-utils.c | 206 ++++++++++++++++------ hw/cxl/cxl-host.c | 2 +- hw/mem/cxl_type3.c | 13 +- hw/pci-bridge/cxl_downstream.c | 1 + hw/pci-bridge/cxl_root_port.c | 1 + hw/pci-bridge/cxl_upstream.c | 3 +- hw/pci-bridge/gen_pcie_root_port.c | 1 + hw/pci/pcie.c | 13 +- include/hw/cxl/cxl_component.h | 87 +++++++-- include/hw/cxl/cxl_device.h | 4 + include/hw/pci-bridge/cxl_upstream_port.h | 1 + include/hw/pci/pcie.h | 2 +- include/hw/pci/pcie_port.h | 1 + include/hw/qdev-properties-system.h | 3 + qapi/common.json | 14 ++ qapi/machine.json | 3 +- qemu-options.hx | 4 +- 19 files changed, 317 insertions(+), 79 deletions(-) -- 2.39.5
