This commit implements shl, shr and sar operations using Wasm
instructions. The Wasm backend uses 64bit variables so the right shift
operation for 32bit values extract the lower 32bit of the operand before
shifting.
Signed-off-by: Kohei Tokunaga <ktokunaga.m...@gmail.com>
---
tcg/wasm/tcg-target.c.inc | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/tcg/wasm/tcg-target.c.inc b/tcg/wasm/tcg-target.c.inc
index e1b10c57b0..81e83a8bdf 100644
--- a/tcg/wasm/tcg-target.c.inc
+++ b/tcg/wasm/tcg-target.c.inc
@@ -120,12 +120,22 @@ typedef enum {
OPC_GLOBAL_GET = 0x23,
OPC_GLOBAL_SET = 0x24,
+ OPC_I32_SHL = 0x74,
+ OPC_I32_SHR_S = 0x75,
+ OPC_I32_SHR_U = 0x76,
+
OPC_I64_ADD = 0x7c,
OPC_I64_SUB = 0x7d,
OPC_I64_MUL = 0x7e,
OPC_I64_AND = 0x83,
OPC_I64_OR = 0x84,
OPC_I64_XOR = 0x85,
+ OPC_I64_SHL = 0x86,
+ OPC_I64_SHR_S = 0x87,
+ OPC_I64_SHR_U = 0x88,
+
+ OPC_I32_WRAP_I64 = 0xa7,
+ OPC_I64_EXTEND_I32_U = 0xad,
} WasmInsn;
#define BUF_SIZE 1024
@@ -199,6 +209,27 @@ static void tcg_wasm_out_o1_i2(
tcg_wasm_out_op(s, opc);
tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret));
}
+static void tcg_wasm_out_o1_i2_type(
+ TCGContext *s, TCGType type, WasmInsn opc32, WasmInsn opc64,
+ TCGReg ret, TCGReg arg1, TCGReg arg2)
+{
+ switch (type) {
+ case TCG_TYPE_I32:
+ tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg1));
+ tcg_wasm_out_op(s, OPC_I32_WRAP_I64);
+ tcg_wasm_out_op_idx(s, OPC_GLOBAL_GET, REG_IDX(arg2));
+ tcg_wasm_out_op(s, OPC_I32_WRAP_I64);
+ tcg_wasm_out_op(s, opc32);
+ tcg_wasm_out_op(s, OPC_I64_EXTEND_I32_U);
+ tcg_wasm_out_op_idx(s, OPC_GLOBAL_SET, REG_IDX(ret));
+ break;
+ case TCG_TYPE_I64:
+ tcg_wasm_out_o1_i2(s, opc64, ret, arg1, arg2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
static bool patch_reloc(tcg_insn_unit *code_ptr_i, int type,
intptr_t value, intptr_t addend)
@@ -930,11 +961,14 @@ static const TCGOutOpBinary outop_rotr = {
static void tgen_sar(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
+ TCGReg orig_a1 = a1;
if (type < TCG_TYPE_REG) {
tcg_out_ext32s(s, TCG_REG_TMP, a1);
a1 = TCG_REG_TMP;
}
tcg_out_op_rrr(s, INDEX_op_sar, a0, a1, a2);
+ tcg_wasm_out_o1_i2_type(s, type, OPC_I32_SHR_S, OPC_I64_SHR_S,
+ a0, orig_a1, a2);
}
static const TCGOutOpBinary outop_sar = {
@@ -946,6 +980,7 @@ static void tgen_shl(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_op_rrr(s, INDEX_op_shl, a0, a1, a2);
+ tcg_wasm_out_o1_i2(s, OPC_I64_SHL, a0, a1, a2);
}
static const TCGOutOpBinary outop_shl = {
@@ -956,11 +991,14 @@ static const TCGOutOpBinary outop_shl = {
static void tgen_shr(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
+ TCGReg orig_a1 = a1;
if (type < TCG_TYPE_REG) {
tcg_out_ext32u(s, TCG_REG_TMP, a1);
a1 = TCG_REG_TMP;
}
tcg_out_op_rrr(s, INDEX_op_shr, a0, a1, a2);
+ tcg_wasm_out_o1_i2_type(s, type, OPC_I32_SHR_U, OPC_I64_SHR_U,
+ a0, orig_a1, a2);
}
static const TCGOutOpBinary outop_shr = {
--
2.43.0
