On Thu, 21 Aug 2025 at 22:37, Vacha Bhavsar
<vacha.bhav...@oss.qualcomm.com> wrote:
>
> Hi,
>
> Regarding having the SME check inside the "if we have SVE" check, we were
> looking the the
> Arm ARM, specifically the following excerpt from section A1.4:
>
> The architecture provides the following:
>
> - A general-purpose register file.
> - A SIMD&FP register file.
> - If FEAT_SVE or FEAT_SME is implemented, an SVE scalable vector register
> file and an
> SVE scalable predicate register file.
> - if FEAT_SME is implemented, the scalable ZA storage.
>
> Based on this, we were considering the following update to the change in
> gdbstub64.c and
> we wanted to get your input.
>
> if (isar_feature_aa64_sve(&cpu->isar) || isar_feature_aa64_sme(&cpu->isar)) {
> GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs,
> cs->gdb_num_regs);
> gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
> aarch64_gdb_set_sve_reg, feature, 0);
> } else {
> gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
> aarch64_gdb_set_fpu_reg,
>
> gdb_find_static_feature("aarch64-fpu.xml"),
> 0);
> }
>
> if (isar_feature_aa64_sme(&cpu->isar)) {
> GDBFeature *sme_feature = arm_gen_dynamic_smereg_feature(cs,
> cs->gdb_num_regs);
> gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg,
> aarch64_gdb_set_sme_reg, sme_feature, 0);
> }
Yes, I think that will be right.
thanks
-- PMM
