On Fri, Aug 15, 2025 at 11:01:04AM +0200, Corvin Köhne wrote:
> From: YannickV <y.vos...@beckhoff.com>
>
> Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT
> should indicate that the reset is finished successfully.
>
> In order to add a MMIO-Device as part of the PL in the Zynq, the
> reset logic must succeed. The PCFG_INIT flag is now set when the
> PL reset is triggered by PCFG_PROG_B. Indicating the reset was
> successful.
>
> Signed-off-by: Yannick Voßen <y.vos...@beckhoff.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
> ---
> hw/dma/xlnx-zynq-devcfg.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
> index 60ea351494..c699df6ad4 100644
> --- a/hw/dma/xlnx-zynq-devcfg.c
> +++ b/hw/dma/xlnx-zynq-devcfg.c
> @@ -49,6 +49,7 @@
>
> REG32(CTRL, 0x00)
> FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored
> */
> + FIELD(CTRL, PCFG_PROG_B, 30, 1)
> FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock
> */
> FIELD(CTRL, PCAP_MODE, 26, 1)
> FIELD(CTRL, MULTIBOOT_EN, 24, 1)
> @@ -116,6 +117,7 @@ REG32(STATUS, 0x14)
> FIELD(STATUS, PSS_GTS_USR_B, 11, 1)
> FIELD(STATUS, PSS_FST_CFG_B, 10, 1)
> FIELD(STATUS, PSS_CFG_RESET_B, 5, 1)
> + FIELD(STATUS, PCFG_INIT, 4, 1)
>
> REG32(DMA_SRC_ADDR, 0x18)
> REG32(DMA_DST_ADDR, 0x1C)
> @@ -204,6 +206,13 @@ static uint64_t r_ctrl_pre_write(RegisterInfo *reg,
> uint64_t val)
> val |= lock_ctrl_map[i] & s->regs[R_CTRL];
> }
> }
> +
> + if (FIELD_EX32(val, CTRL, PCFG_PROG_B)) {
> + s->regs[R_STATUS] |= R_STATUS_PCFG_INIT_MASK;
> + } else {
> + s->regs[R_STATUS] &= ~R_STATUS_PCFG_INIT_MASK;
> + }
> +
> return val;
> }
>
> --
> 2.50.1
>
