build/qemu-riscv64 -cpu rv64,v=on -d strace
build/tests/tcg/riscv64-linux-user/test-vstart-overflow
1118081 riscv_hwprobe(0xffffbc038200,1,0,0,0,0) = 0
1118081 brk(NULL) = 0x0000000000085000
1118081 brk(0x0000000000085b00) = 0x0000000000085b00
1118081 set_tid_address(0x850f0) = 1118081
1118081 set_robust_list(0x85100,24) = -1 errno=38 (Function not implemented)
1118081 rseq(0x857c0,32,0,0xf1401073) = -1 errno=38 (Function not implemented)
Signed-off-by: Joel Stanley <j...@jms.id.au>
---
linux-user/strace.list | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index ab818352a90c..51b5ead9696c 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -1719,3 +1719,6 @@
#ifdef TARGET_NR_riscv_hwprobe
{ TARGET_NR_riscv_hwprobe, "riscv_hwprobe" , "%s(%p,%d,%d,%d,%d,%d)", NULL,
NULL },
#endif
+#ifdef TARGET_NR_rseq
+{ TARGET_NR_rseq, "rseq" , "%s(%p,%u,%d,%#x)", NULL, NULL },
+#endif
--
2.47.2
