From: Richard Henderson <richard.hender...@linaro.org>
Bits [18:0] are not decoded with v7, and for v8 unused values
of rs1 simply produce undefined results.
Fixes: af25071c1d ("target/sparc: Move RDASR, STBAR, MEMBAR to decodetree")
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
Tested-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk>
(cherry picked from commit 49d669ccf33a772e3baf3fe4ebb996dc015f46c1)
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 1b1b85e9c2..74848996ae 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -91,6 +91,7 @@ CALL 01 i:s30
STBAR_v9 10 00000 101000 01111 0 0000000000000
MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
+ RDY_v9 10 rd:5 101000 00000 0 0000000000000
RDCCR 10 rd:5 101000 00010 0 0000000000000
RDASI 10 rd:5 101000 00011 0 0000000000000
RDTICK 10 rd:5 101000 00100 0 0000000000000
@@ -118,8 +119,15 @@ CALL 01 i:s30
# This confirms that bit 13 is ignored, as 0x8143c000 is STBAR.
STBAR_v8 10 ----- 101000 01111 - -------------
- # Before v8, all rs1 accepted; otherwise rs1==0.
- RDY 10 rd:5 101000 rs1:5 0 0000000000000
+ # For v7, bits [18:0] are ignored.
+ # For v8, bits [18:14], aka rs1, are repurposed and rs1 = 0 is RDY,
+ # and other values are RDASR. However, the v8 manual explicitly
+ # says that rs1 in 1..14 yield undefined results and do not cause
+ # an illegal instruction trap, and rs1 in 16..31 are available for
+ # implementation specific usage.
+ # Implement not causing an illegal instruction trap for v8 by
+ # continuing to interpret unused values per v7, i.e. as RDY.
+ RDY_v7 10 rd:5 101000 ----- - -------------
}
{
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 53183dc609..b54285e491 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2864,18 +2864,8 @@ static TCGv do_rdy(DisasContext *dc, TCGv dst)
return cpu_y;
}
-static bool trans_RDY(DisasContext *dc, arg_RDY *a)
-{
- /*
- * TODO: Need a feature bit for sparcv8. In the meantime, treat all
- * 32-bit cpus like sparcv7, which ignores the rs1 field.
- * This matches after all other ASR, so Leon3 Asr17 is handled first.
- */
- if (avail_64(dc) && a->rs1 != 0) {
- return false;
- }
- return do_rd_special(dc, true, a->rd, do_rdy);
-}
+TRANS(RDY_v7, 32, do_rd_special, true, a->rd, do_rdy)
+TRANS(RDY_v9, 64, do_rd_special, true, a->rd, do_rdy)
static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
{
--
2.47.3
