On Sat, 2005-05-14 at 21:03 +0200, Pierre d'Herbemont wrote:
> On 14 mai 05, at 20:15, J. Mayer wrote:
>
> > Qemu assume all reserved fields are set to zero, not 1.
>
> > PowerPC specifications says: (section 8.1 of PEM)
[...]
> > In the case of mtcrf, the PowerPC specification says the bits 11,
> > 21 and
> > 31 (IBM notation) _must_ be zero.
> > This is what is described in 32 bits PEM as well as 64 bits PEM
> > (including the latest revision dated on 31/03/2005) and the 740/750
> > PowerPC user manual (which is the one currently emulated by Qemu).
> >
> > It would be acceptable to relax the check if it would make MacOS X
> > 10.4 boot.
> > But in this case, only the bit 11 (which causes the problem here)
> > should
> > be relaxed.
> > Then, the bit mask becomes 0x00000801 (not 0x00000000).
>
[...]
> In fact I was referring to my old PowerPC Spec book in french from
> IBM (titled Architecture PowerPC), this link was the first google
> returned. After looking again in my book, I found what you said. I am
> confused, I wrote this a bit quickly. But the fact remains, would you
> send a correct patch for that? It'll definitely be compulsory in
> order to boot Mac OS X 10.4, and for darwin-user.
OK, I did put this in my working repository and I'll submit this to
Fabrice.
Please try to do this change to check if other bits need to be relax or
not:
Index: target-ppc/translate.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-ppc/translate.c,v
retrieving revision 1.31
diff -u -r1.31 translate.c
--- target-ppc/translate.c 12 May 2005 18:46:11 -0000 1.31
+++ target-ppc/translate.c 14 May 2005 17:14:35 -0000
@@ -2123,7 +2123,7 @@
}
/* mtcrf */
-GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
+GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
{
gen_op_load_gpr_T0(rS(ctx->opcode));
gen_op_store_cr(CRM(ctx->opcode));
And maybe someone should fill an Apple bug report to tell them their as
is buggy ;-)
--
J. Mayer <[EMAIL PROTECTED]>
Never organized
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