> > IIUC PCI cards don't really have "DMA engines" as such. The PCI bridge > > just maps PCI address space onto physical memory. A Busmaster PCI device > > can then make arbitrary acceses whenever it wants. I expect the default > > mapping is a 1:1 mapping of the first 4G of physical ram. > > I was under the impression that the on-card bus-mastering engines were > often one of a few standard designs - this was suggested to me by someone > more knowledgeable than myself but must admit I don't have any hard > evidence that it's the case ;-)
What about 64-bit systems that use an IOMMU? Don't they already have a 64-bit physical -> 32-bit IO address space mapping? I don't know if this mapping is per-bus or system global. Paul _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
