? target-mips/translate_init.c
Index: Makefile.target
===================================================================
RCS file: /cvsroot/qemu/qemu/Makefile.target,v
retrieving revision 1.147
diff -u -r1.147 Makefile.target
--- Makefile.target	28 Feb 2007 21:36:41 -0000	1.147
+++ Makefile.target	6 Mar 2007 18:17:43 -0000
@@ -550,6 +550,7 @@
 ifeq ($(TARGET_ARCH), mips)
 op.o: op.c op_template.c fop_template.c op_mem.c
 op_helper.o: op_helper_mem.c
+translate.o: translate.c translate_init.c
 endif
 
 loader.o: loader.c elf_ops.h
Index: vl.c
===================================================================
RCS file: /cvsroot/qemu/qemu/vl.c,v
retrieving revision 1.261
diff -u -r1.261 vl.c
--- vl.c	5 Mar 2007 19:44:01 -0000	1.261
+++ vl.c	6 Mar 2007 18:17:46 -0000
@@ -7007,6 +7007,8 @@
                 if (optarg[0] == '?') {
 #if defined(TARGET_PPC)
                     ppc_cpu_list(stdout, &fprintf);
+#elif defined(TARGET_MIPS)
+                    mips_cpu_list(stdout, &fprintf);
 #endif
                     exit(1);
                 } else {
Index: vl.h
===================================================================
RCS file: /cvsroot/qemu/qemu/vl.h,v
retrieving revision 1.191
diff -u -r1.191 vl.h
--- vl.h	5 Mar 2007 19:44:02 -0000	1.191
+++ vl.h	6 Mar 2007 18:17:47 -0000
@@ -713,6 +713,10 @@
 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 #endif
 
+#if defined(TARGET_MIPS)
+void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
+#endif
+
 /* ISA bus */
 
 extern target_phys_addr_t isa_mem_base;
Index: hw/mips_malta.c
===================================================================
RCS file: /cvsroot/qemu/qemu/hw/mips_malta.c,v
retrieving revision 1.15
diff -u -r1.15 mips_malta.c
--- hw/mips_malta.c	5 Mar 2007 19:44:02 -0000	1.15
+++ hw/mips_malta.c	6 Mar 2007 18:17:47 -0000
@@ -626,8 +626,20 @@
     /* fdctrl_t *floppy_controller; */
     MaltaFPGAState *malta_fpga;
     int ret;
+    mips_def_t *def;
 
+    /* init CPUs */
+    if (cpu_model == NULL) {
+#ifdef MIPS_HAS_MIPS64
+        cpu_model = "R4000";
+#else
+        cpu_model = "4KEc";
+#endif
+    }
+    if (mips_find_by_name(cpu_model, &def) != 0)
+        def = NULL;
     env = cpu_init();
+    cpu_mips_register(env, def);
     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
     qemu_register_reset(main_cpu_reset, env);
 
Index: hw/mips_r4k.c
===================================================================
RCS file: /cvsroot/qemu/qemu/hw/mips_r4k.c,v
retrieving revision 1.37
diff -u -r1.37 mips_r4k.c
--- hw/mips_r4k.c	5 Mar 2007 19:44:02 -0000	1.37
+++ hw/mips_r4k.c	6 Mar 2007 18:17:47 -0000
@@ -138,8 +138,20 @@
     CPUState *env;
     static RTCState *rtc_state;
     int i;
+    mips_def_t *def;
 
+    /* init CPUs */
+    if (cpu_model == NULL) {
+#ifdef MIPS_HAS_MIPS64
+        cpu_model = "R4000";
+#else
+        cpu_model = "4KEc";
+#endif
+    }
+    if (mips_find_by_name(cpu_model, &def) != 0)
+        def = NULL;
     env = cpu_init();
+    cpu_mips_register(env, def);
     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
     qemu_register_reset(main_cpu_reset, env);
 
@@ -148,7 +160,7 @@
 
     if (!mips_qemu_iomemtype) {
         mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
-						     mips_qemu_write, NULL);
+                                                     mips_qemu_write, NULL);
     }
     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 
Index: target-mips/cpu.h
===================================================================
RCS file: /cvsroot/qemu/qemu/target-mips/cpu.h,v
retrieving revision 1.23
diff -u -r1.23 cpu.h
--- target-mips/cpu.h	2 Mar 2007 20:48:00 -0000	1.23
+++ target-mips/cpu.h	6 Mar 2007 18:17:48 -0000
@@ -282,6 +282,11 @@
     struct QEMUTimer *timer; /* Internal timer */
 };
 
+typedef struct mips_def_t mips_def_t;
+int mips_find_by_name (const unsigned char *name, mips_def_t **def);
+void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
+int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
+
 #include "cpu-all.h"
 
 /* Memory access type :
Index: target-mips/mips-defs.h
===================================================================
RCS file: /cvsroot/qemu/qemu/target-mips/mips-defs.h,v
retrieving revision 1.7
diff -u -r1.7 mips-defs.h
--- target-mips/mips-defs.h	28 Feb 2007 22:37:42 -0000	1.7
+++ target-mips/mips-defs.h	6 Mar 2007 18:17:48 -0000
@@ -6,26 +6,15 @@
 /* If we want to use host float regs... */
 //#define USE_HOST_FLOAT_REGS
 
-#define MIPS_R4Kc 0x00018000
-#define MIPS_R4Kp 0x00018300
-
-/* Emulate MIPS R4Kc for now */
-#define MIPS_CPU MIPS_R4Kc
-
-#if (MIPS_CPU == MIPS_R4Kc)
 /* 32 bits target */
 #undef MIPS_HAS_MIPS64
 //#define MIPS_HAS_MIPS64 1
 /* real pages are variable size... */
 #define TARGET_PAGE_BITS 12
-/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
-#define MIPS_USES_R4K_EXT
 /* Uses MIPS R4Kc TLB model */
 #define MIPS_USES_R4K_TLB
 #define MIPS_TLB_NB 16
 #define MIPS_TLB_MAX 128
-/* basic FPU register support */
-#define MIPS_USES_FPU 1
 /* Define a implementation number of 1.
  * Define a major version 1, minor version 0.
  */
@@ -63,21 +52,6 @@
 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
  (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
-#elif (MIPS_CPU == MIPS_R4Kp)
-/* 32 bits target */
-#undef MIPS_HAS_MIPS64
-/* real pages are variable size... */
-#define TARGET_PAGE_BITS 12
-/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
-#define MIPS_USES_R4K_EXT
-/* Uses MIPS R4Km FPM MMU model */
-#define MIPS_USES_R4K_FPM
-#else
-#error "MIPS CPU not defined"
-/* Reminder for other flags */
-//#undef MIPS_HAS_MIPS64
-//#define MIPS_USES_FPU
-#endif
 
 #ifdef MIPS_HAS_MIPS64
 #define TARGET_LONG_BITS 64
Index: target-mips/translate.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-mips/translate.c,v
retrieving revision 1.36
diff -u -r1.36 translate.c
--- target-mips/translate.c	2 Mar 2007 20:48:00 -0000	1.36
+++ target-mips/translate.c	6 Mar 2007 18:17:50 -0000
@@ -5283,12 +5283,6 @@
     env->CP0_Wired = 0;
     /* SMP not implemented */
     env->CP0_EBase = 0x80000000;
-    env->CP0_Config0 = MIPS_CONFIG0;
-    env->CP0_Config1 = MIPS_CONFIG1;
-#ifdef MIPS_USES_FPU
-    /* basic FPU register support */
-    env->CP0_Config1 |= (1 << CP0C1_FP);
-#endif
     env->CP0_Config2 = MIPS_CONFIG2;
     env->CP0_Config3 = MIPS_CONFIG3;
     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
@@ -5296,7 +5290,6 @@
     env->hflags = MIPS_HFLAG_ERL;
     /* Count register increments in debug mode, EJTAG version 1 */
     env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
-    env->CP0_PRid = MIPS_CPU;
 #endif
     env->exception_index = EXCP_NONE;
 #if defined(CONFIG_USER_ONLY)
@@ -5308,3 +5301,5 @@
     env->SYNCI_Step = 16;
     env->CCRes = 2;
 }
+
+#include "translate_init.c"
Index: target-mips/translate_init.c
===================================================================
--- /dev/null	?
+++ target-mips/translate_init.c	Tue Mar 06 19:22:18 2007
@@ -0,0 +1,91 @@
+/*
+ *  MIPS emulation for qemu: CPU initialisation routines.
+ *
+ *  Copyright (c) 2004-2005 Jocelyn Mayer
+ *  Copyright (c) 2007 Herve Poussineau
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+struct mips_def_t {
+    const unsigned char *name;
+    int32_t CP0_PRid;
+    int32_t CP0_Config0;
+    int32_t CP0_Config1;
+};
+
+/*****************************************************************************/
+/* MIPS CPU definitions */
+static mips_def_t mips_defs[] =
+{
+#ifndef MIPS_HAS_MIPS64
+    {
+        .name = "4KEc",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0,
+        .CP0_Config1 = MIPS_CONFIG1,
+    },
+    {
+        .name = "24Kf",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0,
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
+    },
+#else
+    {
+        .name = "R4000",
+        .CP0_PRid = 0x00018000,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
+    },
+#endif
+};
+
+int mips_find_by_name (const unsigned char *name, mips_def_t **def)
+{
+    int i, ret;
+
+    ret = -1;
+    *def = NULL;
+    for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
+        if (strcasecmp(name, mips_defs[i].name) == 0) {
+            *def = &mips_defs[i];
+            ret = 0;
+            break;
+        }
+    }
+
+    return ret;
+}
+
+void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
+{
+    int i;
+
+    for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
+        (*cpu_fprintf)(f, "MIPS '%s'\n",
+                       mips_defs[i].name);
+    }
+}
+
+int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
+{
+    if (!def)
+        cpu_abort(env, "Unable to find MIPS CPU definition\n");
+    env->CP0_PRid = def->CP0_PRid;
+    env->CP0_Config0 = def->CP0_Config0;
+    env->CP0_Config1 = def->CP0_Config1;
+    return 0;
+}